Chip, preparation method and electronic equipment

Abstract

The invention discloses a chip, a preparation method and electronic equipment, the chip comprises a substrate and a vertical transmission field effect transistor, in the vertical transmission field effect transistor, a vertical channel structure comprises a first source-drain extension region, a channel region and a second source-drain extension region which are sequentially arranged in the vertical direction, the stacked structure comprises a first side wall isolation layer, a gate structure and a second side wall isolation layer which are sequentially arranged in the vertical direction. In the vertical direction, the area of the cross section of at least one of the first source-drain extension region and the second source-drain extension region is larger than the area of the cross section of the channel region. Under the condition that the thicknesses of the first source-drain extension region and the second source-drain extension region in the vertical direction are not changed, compared with the resistance in the prior art, the resistance of one or the combination of the first source-drain extension region and the second source-drain extension region is reduced, the electrical property of the VTFET can be effectively improved, the working current of the VTFET is improved, and the performance of the VTFET is improved. And the overall PPAC of the chip can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a chip, a preparation method, and an electronic device. Background Art

[0002] Continuously reducing the size of devices and increasing the integration level to obtain better performance are the goals pursued and the driving force for the development of integrated circuit technology. The most basic unit in an integrated circuit is a field-effect transistor (FET). A traditional FET is usually a planar structure, and its conduction path from the source through the channel to the drain is along the horizontal direction. However, with the continuous advancement of Moore's Law, the continuous miniaturization of the critical dimensions (CDs) (such as gate length, contact metal pitch, etc.) of traditional planar-structure FETs has reached the physical limit, resulting in a contradiction among power consumption, performance, and cost in the chip. For this reason, vertical transport field-effect transistors (VTFETs) have emerged, in which the conduction path from the source through the channel to the drain is along the vertical direction rather than the horizontal direction. In this way, further miniaturization of the FET area no longer depends on the compression of the FET's own critical dimensions.

[0003] Moreover, in an integrated circuit, the electrical properties of FETs are very important indicators. Generally, the universal curve of the on-state current (Ion) - off-state current (Ioff) is often used to characterize the quality of the electrical properties of FETs. Among them, the on-state current is strongly correlated with the on-state resistance (Ron), and the on-state resistance is usually determined by the channel resistance (Rch) and the external parasitic resistance (Rpara). As the size of the FET is further scaled down, the proportion of the channel resistance gradually decreases, and the proportion of the external parasitic resistance gradually increases, resulting in an increasing influence of the external parasitic resistance on the on-state current. Usually, side wall spacers (SWS) are provided on both sides of the gate in the FET. The channel part covered by the side wall spacers is the source-drain extension region, that is, the source-drain extension region is connected between the channel region and the source-drain electrode regions, so that the source-drain extension region resistance (Rext) is a very important component of the external parasitic resistance. Therefore, reducing the source-drain extension region resistance is of great significance for improving the electrical properties of FETs, improving the performance, power consumption, area, and cost (PPAC) of the chip. Summary of the Invention

[0004] The present application provides a chip, a preparation method, and an electronic device for reducing the source-drain extension region resistance and improving the PPAC of the chip.

[0005] In a first aspect, an embodiment of the present application provides a chip, which includes a substrate and a vertical transfer field effect transistor disposed on the substrate. The vertical transfer field effect transistor includes a vertical channel structure and a stacked structure. Among them, the vertical channel structure includes a first source-drain extension region, a channel region, and a second source-drain extension region arranged in sequence along the vertical direction. The stacked structure includes a first sidewall isolation layer, a gate structure, and a second sidewall isolation layer arranged in sequence along the vertical direction. The first sidewall isolation layer surrounds the first source-drain extension region, the gate structure surrounds the channel region, and the second sidewall isolation layer surrounds the second source-drain extension region. The vertical direction is perpendicular to the plane where the substrate is located. With this setting, the vertical channel structure can be a columnar structure extending in the vertical direction, and a gate-all-around VTFET can be formed. And, in the vertical direction, the cross-sectional area of at least one of the first source-drain extension region and the second source-drain extension region is larger than the cross-sectional area of the channel region. However, in the prior art, the cross-sectional areas of the first source-drain extension region, the second source-drain extension region, and the channel region are all the same. Therefore, the cross-sectional area of the first source-drain extension region in the present application is larger than the cross-sectional area of the first source-drain extension region in the prior art, and / or the cross-sectional area of the second source-drain extension region is also larger than the cross-sectional area of the second source-drain extension region in the prior art. Based on this, according to the resistance formula R = ρL / S, without changing the thickness of the first source-drain extension region and the second source-drain extension region in the vertical direction, the resistance of one or a combination of the first source-drain extension region and the second source-drain extension region in the present application is reduced compared with the resistance in the prior art, which can effectively improve the electrical properties of the VTFET, increase the operating current of the VTFET, and is beneficial to improving the overall PPAC of the chip.

[0006] In the VTFET of the present application, without changing the overall height of the VTFET, the area ratio between the cross-sectional area of the first source / drain extension region in the vertical direction, the cross-sectional area of the second source / drain extension region in the vertical direction, and the cross-sectional area of the channel region in the vertical direction can be freely adjusted, so as to realize the adjustment of different external parasitic resistances and channel resistances on the same wafer, and meet the electrical property requirements of different devices. Moreover, the VTFET in the present application can be formed in the front-end process and the back-end process of the chip. In addition, the manufacturing process of the VTFET in the present application has a relatively high compatibility with the manufacturing process of the current mainstream fin field-effect transistor (FinFET). Based on this, when the VTFET in the present application is applied to semiconductor devices, especially when applied to the standard cell of logic devices and memory devices, the VTFET can form a more compact FET arrangement, realize a more compact Standard cell, thereby improving the chip integration density and effectively improving the overall PPAC of logic devices and memory devices. In addition, the lower parasitic capacitance of the VTFET can also realize the benefit of the chip dynamic power consumption and improve the PPAC of the chip.

[0007] In the present application, by changing the CD of the cross-section of the first source / drain extension region in the vertical direction, the CD of the cross-section of the second source / drain extension region in the vertical direction, and the CD of the cross-section of the channel region in the vertical direction, the size relationship between their cross-sectional areas is realized. Among them, CD may include the length of the cross-section.

[0008] In some embodiments, the cross-section of the first source / drain extension region in the vertical direction has a first length along a first direction, and the cross-section of the channel region in the vertical direction has a second length along the first direction. The first length is greater than the second length, so that the cross-sectional area of the first source / drain extension region in the vertical direction is greater than the cross-sectional area of the channel region in the vertical direction. Among them, the first direction is perpendicular to the vertical direction.

[0009] Exemplarily, in the direction from the channel region to the first source / drain extension region, the first lengths are made the same, so that in the direction from the channel region to the first source / drain extension region, the cross-sectional areas of the first source / drain extension region in the vertical direction are the same. Or, in the direction from the channel region to the first source / drain extension region, the first lengths are gradually increased, so that in the direction from the channel region to the first source / drain extension region, the cross-sectional areas of the first source / drain extension region in the vertical direction are gradually increased.

[0010] In addition, considering the parasitic capacitance of the first source / drain extension region, in order to avoid too large parasitic capacitance of the first source / drain extension region, the first length can be set to 1.2 to 2 times the second length.

[0011] In some embodiments, the cross-section of the second source-drain extension region in the vertical direction has a third length along a first direction, and the cross-section of the channel region in the vertical direction has a second length along the first direction. The third length is greater than the second length, so that the area of the cross-section of the second source-drain extension region in the vertical direction is greater than the area of the cross-section of the channel region in the vertical direction. Herein, the first direction is perpendicular to the vertical direction.

[0012] Exemplarily, in the direction from the channel region towards the second source-drain extension region, the third length is made the same, so that in the direction from the channel region towards the second source-drain extension region, the areas of the cross-sections of the second source-drain extension region in the vertical direction are the same. Alternatively, in the direction from the channel region towards the second source-drain extension region, the third length is gradually increased, so that in the direction from the channel region towards the second source-drain extension region, the areas of the cross-sections of the second source-drain extension region in the vertical direction are gradually increased.

[0013] In addition, considering the parasitic capacitance of the second source-drain extension region, in order to avoid an excessive parasitic capacitance of the second source-drain extension region, the third length can be set to 1.2 to 2 times the second length.

[0014] In some embodiments, the area of the first cross-section of the first source-drain extension region in the vertical direction is set to be the same as the area of the second cross-section of the second source-drain extension region in the vertical direction. Moreover, there is a first distance between the interface of the channel region and the first source-drain extension region and the first cross-section, and there is a second distance between the interface of the channel region and the second source-drain extension region and the second cross-section. The first distance is the same as the second distance. With this setting, the first source-drain extension region and the second source-drain extension region can be symmetrically arranged.

[0015] Exemplarily, the first cross-section has a first length along the first direction, the second cross-section has a third length along the first direction, the first length is the same as the third length, and the first direction is perpendicular to the vertical direction.

[0016] In some embodiments, in the direction from the channel region towards the first source-drain extension region, the areas of the cross-sections of the first source-drain region are the same. Moreover, the area of the cross-section of the first source-drain region is the same as the area of the surface of the first source-drain extension region facing the first source-drain region, and the shape of the cross-section of the first source-drain region is the same as the shape of the surface of the first source-drain extension region facing the first source-drain region.

[0017] In some embodiments, in the direction from the channel region towards the second source-drain extension region, the areas of the cross-sections of the second source-drain region are the same. Moreover, the area of the cross-section of the second source-drain region is the same as the area of the surface of the second source-drain extension region facing the second source-drain region, and the shape of the cross-section of the second source-drain region is the same as the shape of the surface of the second source-drain extension region facing the second source-drain region.

[0018] In some embodiments, the VTFET in the embodiments of the present application is a junctionless FET. Moreover, one, two, three, four or more VTFETs can be provided in the chip, which is not limited herein. When multiple VTFETs are provided in the chip, the first length, the second length, and the third length of each VTFET can be the same. Alternatively, the first length, the second length, and the third length of some of the VTFETs can be the same, while the first length, the second length, and the third length of the remaining VTFETs are different. Alternatively, the first length, the second length, and the third length of each VTFET can be different. Of course, the specific values of the first length, the second length, and the third length of the VTFET can be determined according to the requirements of the actual application scenario. In addition, a shallow trench isolation (STI) structure is provided between different FETs in the chip.

[0019] In some embodiments, for the VTFET provided in the embodiments of the present application, the cross-sectional area of the first source / drain extension region can be made larger than the cross-sectional area of the channel region, and the cross-sectional area of the second source / drain extension region is the same as the cross-sectional area of the channel region. Alternatively, the cross-sectional area of the second source / drain extension region can be made larger than the cross-sectional area of the channel region, and the cross-sectional area of the first source / drain extension region is the same as the cross-sectional area of the channel region, which is not limited herein.

[0020] In some embodiments, the shape of the cross-section of the first source / drain extension region in the vertical direction is a first shape, the shape of the cross-section of the channel region in the vertical direction is a second shape, and the shape of the cross-section of the second source / drain extension region in the vertical direction is a third shape. The first shape, the second shape, and the third shape can be respectively set as a circle, a bar, a rectangle, a polygon, etc., which is not limited herein. Exemplarily, the first shape, the second shape, and the third shape can be the same. Alternatively, two of the first shape, the second shape, and the third shape can be the same, or the first shape, the second shape, and the third shape can be different, which is not limited herein.

[0021] In some possible embodiments, in order to further reduce the resistance of the first source / drain extension region, the doping concentration of the first source / drain extension region can be made greater than the doping concentration of the channel region.

[0022] In some possible embodiments, in order to further reduce the resistance of the second source / drain extension region, the doping concentration of the second source / drain extension region can be made greater than the doping concentration of the channel region.

[0023] In some possible embodiments, in order to further make the resistance of the first source-drain extension region and the resistance of the second source-drain extension region uniform, the doping concentrations of the first source-drain extension region and the second source-drain extension region can be the same. Of course, the doping concentrations of the first source-drain extension region and the second source-drain extension region can also be set to be different.

[0024] In some embodiments, the vertical channel structure further includes: a first source-drain region disposed on a side of the channel region facing the first source-drain extension region, a second source-drain region disposed on a side of the channel region facing the second source-drain extension region, the first source-drain region is connected to the first source-drain extension region, and the second source-drain region is connected to the second source-drain extension region. Exemplarily, the first source-drain region is set as the source of the VTFET, and the second source-drain region is set as the drain of the VTFET. Alternatively, the first source-drain region is set as the drain of the VTFET, and the second source-drain region is set as the source of the VTFET.

[0025] In some possible embodiments, in order to make the resistance from the channel region to the first source-drain region be a stepped transition, the doping concentration of the first source-drain extension region can be less than the doping concentration of the first source-drain region.

[0026] In some possible embodiments, in order to make the resistance from the channel region to the second source-drain region be a stepped transition, the doping concentration of the second source-drain extension region can be less than the doping concentration of the second source-drain region.

[0027] In some possible embodiments, in order to further make the resistance of the first source-drain region and the resistance of the second source-drain region uniform, the doping concentrations of the first source-drain region and the second source-drain region can be the same. Of course, the doping concentrations of the first source-drain region and the second source-drain region can also be set to be different.

[0028] In some embodiments, the second source-drain region is disposed on a side of the channel region facing away from the substrate, the second sidewall isolation layer further covers the second source-drain region, and the second sidewall isolation layer has a first contact hole for exposing the second source-drain region, and a first contact portion connected to the second source-drain region is filled in the first contact hole.

[0029] In some embodiments, it further includes: an insulating layer covering the second source-drain region and the second sidewall isolation layer, the insulating layer has a second contact hole for exposing the second source-drain region, and a second contact portion connected to the second source-drain region is filled in the second contact hole.

[0030] In a second aspect, an embodiment of the present application further provides an electronic device, which includes a circuit board and the chip in the first aspect or any embodiment of the first aspect. The chip is disposed on the circuit board and connected to the circuit board. Moreover, the electronic device can be any electrical device, such as but not limited to a terminal device, a communication device, and an electronic device, etc. Among them, the terminal device includes but is not limited to a mobile phone, a computer, a television, a set-top box, a watch, a personal computer (PC), a wearable device, a workstation, etc. The communication device includes but is not limited to a wireless network, a fixed network, a server, a smart broadband, etc. The electronic device includes but is not limited to a device module, a storage circuit, a logic circuit, a power device, etc., and will not be listed one by one here.

[0031] In a third aspect, an embodiment of the present application further provides a method for manufacturing a chip. The manufacturing method includes: First, form an initial vertical channel structure, a first sidewall isolation layer, a sacrificial layer, and a second sidewall isolation layer on a substrate. The initial vertical channel structure includes a first source / drain region, a first source / drain extension region, a channel region, a second source / drain extension region, and a second source / drain region arranged in sequence along the vertical direction. And in the vertical direction, the cross-sectional areas of the first source / drain extension region, the second source / drain extension region, and the channel region are the same; the first sidewall isolation layer surrounds the first source / drain extension region, the second sidewall isolation layer surrounds the second source / drain extension region, and the sacrificial layer surrounds the channel region. After that, etch away the sacrificial layer to expose the channel region. Then, etch the channel region in the initial vertical channel structure so that in the vertical direction, the cross-sectional areas of the first source / drain extension region and the second source / drain extension region are respectively larger than the cross-sectional area of the channel region, forming the channel region in the vertical channel structure. Then, form a gate structure surrounding the channel region of the vertical channel structure.

[0032] In order to form the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer, in some examples, forming the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer on the substrate includes but is not limited to the following process: First, perform ion doping in the substrate to form the first source / drain region. Then, epitaxially grow a first epitaxial layer on the substrate. The first epitaxial layer includes a first source / drain extension region, a channel region, a second source / drain extension region, and a second source / drain region arranged in sequence along the vertical direction. Then, perform patterning on the first epitaxial layer to form the initial vertical channel structure. Then, deposit the first sidewall isolation layer surrounding the first source / drain extension region of the initial vertical channel structure. Then, deposit the sacrificial layer surrounding the channel region of the initial vertical channel structure. Then, deposit the second sidewall isolation layer surrounding the second source / drain extension region of the initial vertical channel structure.

[0033] Further, the manufacturing method further includes: when depositing the second sidewall isolation layer around the second source / drain extension region surrounding the initial vertical channel structure, the second sidewall isolation layer also covers the second source / drain region. And, after forming the gate structure around the channel region of the vertical channel structure, the second sidewall isolation layer is patterned to form a first contact hole exposing the second source / drain region, and a metal material is deposited in the first contact hole to form a first contact portion connected to the second source / drain region.

[0034] To form the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer, in some examples, forming the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer on the substrate includes, but is not limited to, the following process: First, ion doping is performed in the substrate to form the first source / drain region. After that, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer are sequentially deposited on the substrate. After that, the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer are patterned to form a groove penetrating through the first sidewall isolation layer, the sacrificial layer, and the second sidewall isolation layer, exposing the first source / drain region. After that, a second epitaxial layer is epitaxially grown in the groove, and the second epitaxial layer includes a first source / drain extension region, a channel region, a second source / drain extension region, and a second source / drain region arranged in sequence along the vertical direction. The interface between the second source / drain extension region and the second source / drain region is aligned with the surface of the second sidewall isolation layer facing away from the sacrificial layer.

[0035] Further, the manufacturing method further includes: after epitaxially growing the initial vertical channel structure in the groove, an insulating layer is deposited to cover the second source / drain region and the second sidewall isolation layer. And, after forming the gate structure around the channel region of the vertical channel structure, the insulating layer is patterned to form a second contact hole exposing the second source / drain region, and a metal material is deposited in the second contact hole to form a second contact portion connected to the second source / drain region. Description of the Drawings

[0036] Figure 1 It is a schematic structural diagram of an electronic device in an embodiment of the present application;

[0037] Figure 2 It is a schematic structural diagram of a chip in an embodiment of the present application;

[0038] Figures 3a to 3k They are respectively schematic cross-sectional structural diagrams of the chip in the preparation process in an embodiment of the present application;

[0039] Figure 4 It is a schematic structural diagram of a chip in an embodiment of the present application;

[0040] Figures 5a to 5hAnother cross-sectional structure schematic diagram of the chip in the embodiment of the present application during the manufacturing process;

[0041] Figure 6 A structure schematic diagram of the chip in the embodiment of the present application;

[0042] Figure 7 A structure schematic diagram of the chip in the embodiment of the present application.

[0043] Reference numerals

[0044] 100 - housing; 200 - circuit board; 300 - chip; 310 - substrate; 320 - vertical channel structure; 311 - channel region; 312 - first source / drain extension region; 313 - second source / drain extension region; 314 - first source / drain electrode region; 315 - second source / drain electrode region; 330 - stacked structure; 331 - first sidewall isolation layer; 332 - second sidewall isolation layer; 333 - gate structure; 3331 - metal gate; 3332 - gate oxide layer; 340 - insulating layer; 351 - first contact portion; 352 - second contact portion; 400 - first epitaxial layer; 411 - sacrificial material layer; 412 - sacrificial layer; 420 - initial vertical channel structure; 431 - first sidewall isolation material layer; 500 - second epitaxial layer; AX - groove; CT1 - first contact hole; CT2 - second contact hole; d1 - first length; d2 - second length; d3 - third length; h1 - first distance; h2 - second distance; F0 - vertical direction; F1 - first direction. Detailed implementation manners

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "a plurality of" can be understood as "at least two". In addition, it should be understood that in the description of the present application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0046] It should be noted that the same reference numerals in the drawings of the present application represent the same or similar structures, and thus the repeated descriptions thereof will be omitted. The terms expressing positions and directions in the present application are all described with reference to the drawings as examples, but can also be changed as needed, and all the changes are included in the protection scope of the present application. The drawings of the present application are only used to illustrate the relative position relationship and do not represent the actual ratio.

[0047] The chip provided by the embodiment of the present application can be various electronic devices or integrated circuit devices for implementing a certain or certain functions, and the chip can be widely used in various electronic devices. The electronic devices include, for example, but are not limited to, terminal devices, communication devices, and electronic devices, etc. Among them, the terminal devices include, for example, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, and other devices. The communication devices include, for example, but are not limited to, wireless networks, fixed networks, servers, intelligent broadband, etc. The electronic devices include, for example, but are not limited to, device modules, storage circuits, logic circuits, power devices, etc., and will not be listed one by one here. It can be understood that the specific implementation manners of the electronic devices can be determined according to the actual application scenarios and are not limited here.

[0048] Figure 1 It is a schematic structural diagram of an electronic device in the embodiment of the present application. Refer to Figure 1 , the electronic device includes: a housing 100, a circuit board 200 disposed in the housing 100, and a chip 300 fixed on the circuit board 200. Among them, the chip 300 and the circuit board 200 can adopt connection methods such as bonding and binding to achieve electrical connection between the chip 300 and the circuit board 200, so that signal transmission can be carried out between the chip 300 and the circuit board 200. Exemplarily, the circuit board 200 includes, for example, but is not limited to, a printed circuit board (PCB).

[0049] Figure 2 It is a schematic structural diagram of a chip in the embodiment of the present application. Refer to Figure 2, the chip 300 includes: a substrate 310 and a vertical transmission field-effect transistor (VTFET) disposed on the substrate 310. The VTFET includes: a vertical channel structure 320 and a stacked structure 330. Among them, the vertical channel structure 320 includes a first source / drain extension region 312, a channel region 311, a second source / drain extension region 313, a first source / drain region 314 disposed on one side of the channel region 311 facing the first source / drain extension region 312, and a second source / drain region 315 disposed on one side of the channel region 311 facing the second source / drain extension region 313, which are sequentially arranged along the vertical direction F0. The stacked structure 330 includes a first sidewall isolation layer 331, a gate structure 333, and a second sidewall isolation layer 332, which are sequentially arranged along the vertical direction F0. The first sidewall isolation layer 331 surrounds the first source / drain extension region 312, the gate structure 333 surrounds the channel region 311, and the second sidewall isolation layer 332 surrounds the second source / drain extension region 313. With such a setting, the vertical channel structure 320 can be a columnar structure extending in the vertical direction and form a surround gate type VTFET. Moreover, in the embodiment of the present application, in the vertical direction F0, the cross-sectional area S1 of the first source / drain extension region 312 can also be made larger than the cross-sectional area S3 of the channel region 311, and the cross-sectional area S2 of the second source / drain extension region 313 is also larger than the cross-sectional area S3 of the channel region 311. However, in the prior art, the cross-sectional areas of the first source / drain extension region 312, the second source / drain extension region 313, and the channel region 311 are the same. Therefore, the cross-sectional area S1 of the first source / drain extension region 312 in the present application is larger than the cross-sectional area of the first source / drain extension region 312 in the prior art, and the cross-sectional area S2 of the second source / drain extension region 313 is also larger than the cross-sectional area of the second source / drain extension region 313 in the prior art. Based on this, according to the resistance formula R = ρL / S, without changing the thickness of the first source / drain extension region 312 and the second source / drain extension region 313 in the vertical direction F0, the resistance of the first source / drain extension region 312 and the second source / drain extension region 313 in the present application is reduced compared with the resistance of the first source / drain extension region 312 and the second source / drain extension region 313 in the prior art, which can effectively improve the electrical properties of the VTFET, increase the working current of the VTFET, and is beneficial to improving the overall PPAC of the chip 300.

[0050] It is worth mentioning that for the VTFET in this application, without changing the overall height of the VTFET, the area S1 of the cross-section of the first source-drain extension region 312 in the vertical direction F0 can be freely adjusted, and the area ratio between the area S3 of the cross-section of the second source-drain extension region 313 in the vertical direction F0 and the area S2 of the cross-section of the channel region 311 in the vertical direction F0 can be adjusted, so as to realize the adjustment of different external parasitic resistances and channel resistances on the same wafer, and meet the electrical property requirements of different devices. Moreover, the VTFET in this application can be formed in the front-end process and the back-end process of the chip 300. In addition, the manufacturing process of the VTFET in this application has a relatively high compatibility with the current mainstream FinFET manufacturing process. Based on this, when the VTFET in this application is applied to semiconductor devices, especially when applied to the Standard cell of logic devices and memory devices, the VTFET can form a more compact FET arrangement, realize a more compact Standard cell, thereby improving the integration density of the chip 300, and effectively improving the overall PPAC of logic devices and memory devices. In addition, the lower parasitic capacitance of the VTFET can also realize the benefit of the dynamic power consumption of the chip 300 and improve the PPAC of the chip 300.

[0051] In this application, the size relationship among the areas S1, S2, and S3 can be realized by changing the CD of the cross-section of the first source-drain extension region 312 in the vertical direction F0, the CD of the cross-section of the second source-drain extension region 313 in the vertical direction F0, and the CD of the cross-section of the channel region 311 in the vertical direction F0. Among them, the CD can include the length of the cross-section. For example, referring to Figure 2 , the cross-section of the first source-drain extension region 312 in the vertical direction F0 has a first length d1 along the first direction F1, and the cross-section of the channel region 311 in the vertical direction F0 has a second length d2 along the first direction F1. The first length d1 can be made greater than the second length d2 so that the area S1 is greater than the area S2. Further, considering the parasitic capacitance of the first source-drain extension region 312, in order to avoid too large parasitic capacitance of the first source-drain extension region 312, the first length d1 can be made 1.2 to 2 times the second length d2, that is, d1 is 1.2*d2~2*d2. For example, d1 can be set to 1.2*d2, 1.5*d2, 1.7*d2, 2*d2, etc. Of course, in actual applications, the specific value of d1 can be determined according to the requirements of the actual application scenario and is not limited here.

[0052] Further, referring to Figure 2, in the direction along the channel region 311 pointing to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the area S1 can be made the same. For example, in the direction along the channel region 311 pointing to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the first length d1 can be made the same to make the area S1 the same in the direction along the channel region 311 pointing to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow). With this setting, the process preparation difficulty can be reduced.

[0053] Continue to refer to Figure 2 , the cross-section of the second source / drain extension region 313 in the vertical direction F0 has a third length d3 along the first direction F1, and the third length d3 can be made greater than the second length d2 so that the area S3 is greater than the area S2. Further, considering the parasitic capacitance of the second source / drain extension region 313, in order to avoid the parasitic capacitance of the second source / drain extension region 313 from being too large, the third length d3 can be 1.2 to 2 times the second length d2, that is, d3 is 1.2*d2 to 2*d2. For example, d3 can be set to 1.2*d2, 1.5*d2, 1.7*d2, 2*d2, etc. Of course, in actual applications, the specific value of d3 can be determined according to the requirements of the actual application scenario and is not limited here.

[0054] Further, refer to Figure 2 , in the direction along the channel region 311 pointing to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the area S3 can be made the same. For example, in the direction along the channel region 311 pointing to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the third length d3 can be made the same to make the area S3 the same in the direction along the channel region 311 pointing to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow). With this setting, the process preparation difficulty can be reduced.

[0055] Continue to refer to Figure 2 , the area (such as S1) of the first cross-section of the first source / drain extension region 312 in the vertical direction F0 can be the same as the area (such as S2) of the second cross-section of the second source / drain extension region 313 in the vertical direction F0. Among them, there is a first distance h1 between the interface of the channel region 311 and the first source / drain extension region 312 and the first cross-section, and there is a second distance h2 between the interface of the channel region 311 and the second source / drain extension region 313 and the second cross-section, and the first distance h1 is the same as the second distance h2. With this setting, the first source / drain extension region 312 and the second source / drain extension region 313 can be symmetrically arranged. Further, the first length d1 in the first cross-section is the same as the third length d3 in the second cross-section.

[0056] Further, in the direction along the channel region 311 pointing to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the cross-sectional areas of the first source / drain region 314 can be made the same. Moreover, the cross-sectional area of the first source / drain region 314 is the same as the area of the surface of the first source / drain extension region 312 facing the first source / drain region 314, and the cross-sectional shape of the first source / drain region 314 is the same as the shape of the surface of the first source / drain extension region 312 facing the first source / drain region 314. Also, in the direction along the channel region 311 pointing to the second source / drain extension region 313 (i.e., the direction pointed to by the F0 arrow), the cross-sectional areas of the second source / drain region 315 can be made the same. Moreover, the cross-sectional area of the second source / drain region 315 is the same as the area of the surface of the second source / drain extension region 313 facing the second source / drain region 315, and the cross-sectional shape of the second source / drain region 315 is the same as the shape of the surface of the second source / drain extension region 313 facing the second source / drain region 315.

[0057] It can be understood that the magnitude relationships among the above-mentioned first length, second length, and third length are all compared in the same vertical plane, which is parallel to the vertical direction. Additionally, the above-mentioned vertical direction is perpendicular to the plane where the substrate is located, and the first direction is perpendicular to the vertical direction.

[0058] It is worth mentioning that the VTFET in the embodiment of the present application is a junctionless FET. Moreover, one, two, three, four, or more VTFETs can be provided in the chip, which is not limited herein. When multiple VTFETs are provided in the chip, the first length, second length, and third length of each VTFET can be the same. Or, the first length, second length, and third length of some VTFETs can be the same, while the first length, second length, and third length of the remaining VTFETs are different. Or, the first length, second length, and third length of each VTFET can be different. Of course, the specific values of the first length, second length, and third length of the VTFET can be determined according to the requirements of the actual application scenario. Additionally, a Shallow Trench Isolation (STI) structure is provided between different FETs in the chip.

[0059] It can be understood that for the VTFET provided in the embodiment of the present application, the cross-sectional area of the first source / drain extension region can also be made larger than the cross-sectional area of the channel region, and the cross-sectional area of the second source / drain extension region is the same as the cross-sectional area of the channel region. Or, the cross-sectional area of the second source / drain extension region can also be made larger than the cross-sectional area of the channel region, and the cross-sectional area of the first source / drain extension region is the same as the cross-sectional area of the channel region, which is not limited herein.

[0060] Refer to Figure 2, the cross-sectional shape of the first source-drain extension region 312 in the vertical direction F0 is the first shape, the cross-sectional shape of the channel region 311 in the vertical direction F0 is the second shape, and the cross-sectional shape of the second source-drain extension region 313 in the vertical direction F0 is the third shape. The first shape, the second shape, and the third shape can be set to a circle, a bar, a rectangle, a polygon, etc., which is not limited herein. Exemplarily, the first shape, the second shape, and the third shape can be the same. Alternatively, two of the first shape, the second shape, and the third shape can be the same, or the first shape, the second shape, and the third shape can all be different, which is not limited herein.

[0061] Continuing to refer to Figure 2 , the first source-drain region 314 is connected to the first source-drain extension region 312, and the second source-drain region 315 is connected to the second source-drain extension region 313. Among them, the first source-drain region 314 can be set as the source of the VTFET, and the second source-drain region 315 can be set as the drain of the VTFET. Alternatively, the first source-drain region 314 can be set as the drain of the VTFET, and the second source-drain region 315 can be set as the source of the VTFET.

[0062] Exemplarily, in order to further reduce the resistance of the first source-drain extension region 312, the doping concentration of the first source-drain extension region 312 can be made greater than the doping concentration of the channel region 311. Alternatively, in order to make the resistance from the channel region 311 to the first source-drain region 314 transition in a stepped manner, the doping concentration of the first source-drain extension region 312 can be made less than the doping concentration of the first source-drain region 314. Alternatively, in order to further reduce the resistance of the second source-drain extension region 313, the doping concentration of the second source-drain extension region 313 can be made greater than the doping concentration of the channel region 311. Or, in order to make the resistance from the channel region 311 to the second source-drain region 315 transition in a stepped manner, the doping concentration of the second source-drain extension region 313 can be made less than the doping concentration of the second source-drain region 315.

[0063] Exemplarily, in order to further make the resistance of the first source-drain extension region 312 and the resistance of the second source-drain extension region 313 uniform, the doping concentrations of the first source-drain extension region 312 and the second source-drain extension region 313 can also be made the same. Of course, the doping concentrations of the first source-drain extension region 312 and the second source-drain extension region 313 can also be set to be different. Alternatively, in order to further make the resistance of the first source-drain region 314 and the resistance of the second source-drain region 315 uniform, the doping concentrations of the first source-drain region 314 and the second source-drain region 315 can also be made the same. Of course, the doping concentrations of the first source-drain region 314 and the second source-drain region 315 can also be set to be different.

[0064] It is understandable that the VTFET in the embodiment of the present application can be set as an N-type VTFET, and N-type ions can be doped in the first source-drain region 314, the second source-drain region 315, the first source-drain extension region 312, and the second source-drain extension region 313, and N-type ions or P-type ions can be doped in the channel region 311. Alternatively, the VTFET in the embodiment of the present application can also be set as a P-type VTFET, and P-type ions can be doped in the first source-drain region 314, the second source-drain region 315, the first source-drain extension region 312, and the second source-drain extension region 313, and N-type ions or P-type ions can be doped in the channel region 311.

[0065] In addition, continue to refer to Figure 2 The gate structure 333 includes a metal gate 3331 and a gate oxide layer 3332, the gate oxide layer 3332 covers the surface of the channel region 311, the gate oxide layer 3332 also covers the surface of the first spacer isolation layer 331 facing the channel region 311, and the gate oxide layer 3332 also covers the surface of the second spacer isolation layer 332 facing the channel region 311. The metal gate 3331 surrounds the channel region 311 through the gate oxide layer 3332. Exemplarily, the metal gate 3331 may include a single-layer metal structure (such as a work function metal or a low-resistance metal), or a multi-layer metal structure (such as a combined structure of a work function metal and a low-resistance metal). In addition, the first source and drain region 314 may be arranged on the side of the channel region 311 facing the substrate 310, and the second source and drain region 315 may be arranged on the side of the channel region 311 facing away from the substrate 310. Furthermore, the second sidewall isolation layer 332 also covers the second source-drain region 315, and the second sidewall isolation layer 332 has a first contact hole CT1, the first contact hole CT1 can expose the second source-drain region 315, and the first contact hole CT1 is filled with a first contact portion 351 connected to the second source-drain region 315. In addition, the metal gate 3331 is also connected to the gate contact portion, and the first source-drain region 314 is also connected to the third contact portion. Based on this, the first contact portion 351, the third contact portion and the gate contact portion are also connected to the interconnection line layer, and the signal is transmitted through the interconnection line layer. In addition, an ohmic contact can be formed between the first contact portion 351 and the second source-drain region 315, an ohmic contact can be formed between the gate contact portion and the metal gate 3331, and an ohmic contact can be formed between the third contact portion and the first source-drain region 314.

[0066] It is worth mentioning that due to the limitation of process conditions or other factors, there may be some deviations or errors in the actual process, resulting in that the "same" described above may not be completely accurate. For example, the "same" described above may be the same as allowed within the error tolerance range. Of course, "same" can also be understood as "substantially the same" or "completely the same", so the "same" relationship described above only needs to roughly meet the above conditions and is within the scope of protection of this application.

[0067] For the preparation of Figure 2 Taking the structure of the VTFET shown as an example, the method for preparing the chip provided by the embodiments of the present application may include the following content:

[0068] Referring to Figure 3a , Figure 3a FIG. is a schematic cross-sectional structure diagram of the chip in the preparation process in the embodiments of the present application. Exemplarily, a substrate 310 is provided, and the substrate 310 may include, for example, but not limited to: a silicon substrate 310, a silicon-on-insulator (SOI) substrate 310, etc. The present application takes the silicon substrate 310 as an example for illustration. After forming the STI structure on the substrate 310, an appropriate process such as an ion implantation process is used to perform ion doping in the region of the substrate 310 where the first source-drain region 314 needs to be formed, so as to form the heavily doped first source-drain region 314.

[0069] Referring to Figure 3b , Figure 3b FIG. is another schematic cross-sectional structure diagram of the chip in the preparation process in the embodiments of the present application. Exemplarily, by using an epitaxial growth process, a first epitaxial layer 400 is epitaxially grown on the substrate 310. The first epitaxial layer 400 includes a lightly doped first source-drain extension region 312, a channel region 311, a lightly doped second source-drain extension region 313, and a heavily doped second source-drain region 315 that are sequentially arranged along the vertical direction F0.

[0070] Referring to Figure 3c , Figure 3c FIG. is another schematic cross-sectional structure diagram of the chip in the preparation process in the embodiments of the present application. Exemplarily, by using a patterning process, the first epitaxial layer 400 is patterned to form an initial vertical channel structure 420. Among them, the initial vertical channel structure 420 includes a heavily doped first source-drain region 314, a lightly doped first source-drain extension region 312, a channel region 311, a lightly doped second source-drain extension region 313, and a heavily doped second source-drain region 315 that are sequentially arranged along the vertical direction F0. And, in the vertical direction F0, the cross-sectional areas of the first source-drain extension region 312, the second source-drain extension region 313, and the channel region 311 are the same. And, a first sidewall isolation layer 331 surrounds the first source-drain extension region 312, a second sidewall isolation layer 332 surrounds the second source-drain extension region 313, and a sacrificial layer surrounds the channel region 311. In addition, the initial vertical channel structure 420 may be a columnar structure extending along the vertical direction, and the shape of the cross-section of the initial vertical channel structure 420 in the vertical direction F0 may be set to be circular, strip-shaped, rectangular, polygonal, etc., which is not limited herein. It can be understood that when multiple VTFETs are provided in the chip 300, the initial vertical channel structures 420 with different feature sizes can be patterned according to the required feature sizes of different VTFETs.

[0071] Reference Figure 3d With Figure 3e , Figure 3d With Figure 3e are another cross-sectional structure diagrams of the chip in the preparation process in the embodiments of the present application. A first sidewall isolation layer 331 surrounding the first source / drain extension region 312 of the initial vertical channel structure 420 is deposited. Exemplarily, reference is made to Figure 3d , a first sidewall isolation material layer 431 is deposited on the substrate 310 using a dielectric material (such as silicon dioxide, silicon nitride, etc.). Then, reference is made to Figure 3e , the first sidewall isolation material layer 431 is etched so that the surface of the first sidewall isolation material layer 431 facing away from the substrate 310 is substantially flush with the surface of the first source / drain extension region 312 facing the channel region 311, forming a first sidewall isolation layer 331 surrounding the first source / drain extension region 312. It should be noted that due to process conditions or other factors, in the actual process, there may be some deviations or errors, resulting in the "flush" described above may not be completely accurate. For example, the "flush" described above can be the flush allowed within the error tolerance range. Of course, the "flush" can also be understood as "substantially flush" or "completely flush". Therefore, as long as the "flush" relationship described above generally meets the above conditions, it belongs to the protection scope of the present application. The same applies hereinafter and will not be repeated one by one.

[0072] Reference Figure 3f With Figure 3g , Figure 3f With Figure 3g are another cross-sectional structure diagrams of the chip in the preparation process in the embodiments of the present application. A sacrificial layer 412 surrounding the channel region 311 of the initial vertical channel structure 420 is deposited. Exemplarily, reference is made to Figure 3f , a dielectric material with a higher etching selectivity ratio compared to the first sidewall isolation layer 331 is used to deposit a sacrificial material layer 411 on the substrate 310. Then, reference is made to Figure 3g , the sacrificial material layer 411 is etched so that the surface of the sacrificial material layer 411 facing away from the substrate 310 is substantially flush with the surface of the channel region 311 facing away from the substrate 310, forming a sacrificial layer 412 surrounding the channel region 311.

[0073] Reference Figure 3h , Figure 3h is another cross-sectional structure diagram of the chip in the preparation process in the embodiments of the present application. Exemplarily, a dielectric material with a higher etching selectivity ratio compared to the sacrificial layer 412 is used to deposit a second sidewall isolation layer 332, and the second sidewall isolation layer 332 surrounds the second source / drain extension region 313 of the initial vertical channel structure 420, and the second sidewall isolation layer 332 also covers the second source / drain region 315.

[0074] Reference Figure 3i , Figure 3i Schematic diagram of another cross-sectional structure of the chip in the manufacturing process in the embodiment of the present application. Exemplarily, the sacrificial layer 412 is removed by etching to expose the channel region 311.

[0075] Reference Figure 3j , Figure 3j It is another schematic diagram of a cross-sectional structure of a chip in an embodiment of the present application during the preparation process. Exemplarily, the channel region 311 in the initial vertical channel structure 420 is etched so that the periphery of the channel region 311 is recessed relative to the periphery of the first source and drain extension region 312 and the second source and drain extension region 313, so that the cross-sectional area of ​​the first source and drain extension region 312 and the cross-sectional area of ​​the second source and drain extension region 313 are respectively larger than the cross-sectional area of ​​the channel region 311 in the vertical direction F0, thereby forming the channel region 311 in the vertical channel structure 320. In other words, the first length d1 and the third length d3 can be respectively larger than the second length d2.

[0076] Reference Figure 3k , Figure 3k This is another cross-sectional structural schematic diagram of the chip in the embodiment of the present application during the preparation process, forming a gate structure 333 surrounding the channel region 311 of the vertical channel structure 320. Exemplarily, a deposition process or a growth process is used to form a gate oxide layer 3332, and the gate oxide layer 3332 covers the surface of the channel region 311, and the gate oxide layer 3332 also covers the surface of the first sidewall isolation layer 331 facing the channel region 311, and the gate oxide layer 3332 also covers the surface of the second sidewall isolation layer 332 facing the channel region 311. Afterwards, a work function metal is deposited to form a metal gate 3331, and the metal gate 3331 surrounds the channel region 311 through the gate oxide layer 3332.

[0077] Reference Figure 2 , the second spacer isolation layer 332 is patterned by a patterning process to form a first contact CT1 penetrating the second spacer isolation layer 332, and the first contact hole CT1 exposes the second source and drain region 315. Afterwards, a metal material is deposited in the first contact hole CT1 to form a first contact portion 351 connected to the second source and drain region 315. In addition, a gate contact portion connected to the metal gate 3331 and a third contact portion connected to the first source and drain region 314 are also formed. In addition, an ohmic contact is formed between the first contact portion 351 and the second source and drain region 315, an ohmic contact is also formed between the gate contact portion and the metal gate 3331, and an ohmic contact is also formed between the third contact portion and the first source and drain region 314.

[0078] Figure 4 This is another schematic diagram of the structure of the chip in the embodiment of the present application, referring toFigure 4 , the chip 300 in the embodiment of the present application is a deformation of the implementation manner of the chip 300 in the Figure 2 illustrated embodiment. Only the differences between this embodiment and the above embodiment are described below, and the same parts are not elaborated here. The differences between this embodiment and the Figure 2 illustrated embodiment are as follows: The second sidewall isolation layer 332 does not cover the second source / drain region 315. Moreover, the VTFET further includes an insulating layer 340 covering the second source / drain region 315 and the second sidewall isolation layer 332, and the insulating layer 340 has a second contact hole CT2. Among them, the second contact hole CT2 can expose the second source / drain region 315, and the second contact hole CT2 is filled with a second contact portion 352 connected to the second source / drain region 315. Based on this, the second contact portion 352 will also be connected to the interconnection line layer, and signals are transmitted through the interconnection line layer. In addition, an ohmic contact is also formed between the second contact portion 352 and the second source / drain region 315.

[0079] Taking the preparation of the Figure 4 illustrated VTFET structure as an example, the preparation method of the chip provided by the embodiment of the present application may include the following contents:

[0080] Referring to Figure 5a , Figure 5a which is another cross-sectional structure schematic diagram of the chip in the embodiment of the present application during the preparation process. Exemplarily, a substrate 310 is provided, and the substrate 310 includes, for example, but is not limited to: a silicon substrate 310, a silicon-on-insulator (SOI) substrate 310, etc. The present application is described by taking the silicon substrate 310 as an example. After forming the STI structure on the substrate 310, an appropriate process such as an ion implantation process is used to perform ion doping in the region of the substrate 310 where the first source / drain region 314 needs to be formed to form the heavily doped first source / drain region 314.

[0081] Referring to Figure 5b , Figure 5b which is another cross-sectional structure schematic diagram of the chip in the embodiment of the present application during the preparation process. Exemplarily, a dielectric material is used to sequentially deposit a first sidewall isolation layer 331, a sacrificial layer 412, and a second sidewall isolation layer 332 on the substrate 310. Among them, the material of the sacrificial layer 412 has a higher etching selectivity compared to the materials of the first sidewall isolation layer 331 and the second sidewall isolation layer 332.

[0082] Referring to Figure 5c , Figure 5cAnother cross-sectional structure schematic diagram during the preparation of the chip in the embodiment of the present application. Exemplarily, a patterning process is used to pattern the first sidewall isolation layer 331, the sacrificial layer 412, and the second sidewall isolation layer 332 to form a groove AX penetrating through the first sidewall isolation layer 331, the sacrificial layer 412, and the second sidewall isolation layer 332, exposing the first source / drain region 314. Among them, the shape of the cross-section of the groove AX in the vertical direction F0 can be set to a circle, a strip, a rectangle, a polygon, etc., which is not limited herein. It can be understood that when multiple VTFETs are provided in the chip 300, grooves with different feature sizes can be patterned according to the feature sizes required by different VTFETs.

[0083] Referring to Figure 5d , Figure 5d Another cross-sectional structure schematic diagram during the preparation of the chip in the embodiment of the present application. Exemplarily, a second epitaxial layer 500 is epitaxially grown in the groove AX. The second epitaxial layer 500 includes a lightly doped first source / drain extension region 312, a channel region 311, a lightly doped second source / drain extension region 313, and a heavily doped second source / drain region 315 arranged in sequence along the vertical direction F0. And, the heavily doped first source / drain region 314 and the second epitaxial layer 500 together form an initial vertical channel structure 420. And, in the vertical direction F0, the cross-sectional areas of the first source / drain extension region 312, the second source / drain extension region 313, and the channel region 311 are the same. And, the interface between the second source / drain extension region 313 and the second source / drain region 315 is aligned with the surface of the second sidewall isolation layer 332 facing away from the sacrificial layer. The first sidewall isolation layer 331 surrounds the first source / drain extension region 312, the second sidewall isolation layer 332 surrounds the second source / drain extension region 313, and the sacrificial layer 412 surrounds the channel region 311. Additionally, the initial vertical channel structure 420 can be a columnar structure extending along the vertical direction F0, and the shape of the cross-section of the initial vertical channel structure 420 in the vertical direction F0 can be set to a circle, a strip, a rectangle, a polygon, etc., which is not limited herein. It can be understood that when multiple VTFETs are provided in the chip 300, initial vertical channel structures 420 with different feature sizes can be patterned according to the feature sizes required by different VTFETs.

[0084] Referring to Figure 5e , Figure 5e Another cross-sectional structure schematic diagram during the preparation of the chip in the embodiment of the present application. Exemplarily, a dielectric material is used to deposit an insulating layer 340, and the insulating layer 340 covers the second source / drain region 315 and the second sidewall isolation layer 332. Among them, the material of the insulating layer 340 has a higher etching selectivity compared to the materials of the first sidewall isolation layer 331, the second sidewall isolation layer 332, and the sacrificial layer.

[0085] Referring toFigure 5f , Figure 5f Schematic diagram of another cross-sectional structure of the chip in the manufacturing process in the embodiment of the present application. Exemplarily, the sacrificial layer 412 is removed by etching to expose the channel region 311.

[0086] Reference Figure 5g , Figure 5g It is another schematic diagram of a cross-sectional structure of a chip in an embodiment of the present application during the preparation process. Exemplarily, the channel region 311 in the initial vertical channel structure 420 is etched so that the periphery of the channel region 311 is recessed relative to the periphery of the first source and drain extension region 312 and the second source and drain extension region 313, so that the cross-sectional area of ​​the first source and drain extension region 312 and the cross-sectional area of ​​the second source and drain extension region 313 are respectively larger than the cross-sectional area of ​​the channel region 311 in the vertical direction F0, thereby forming the channel region 311 in the vertical channel structure 320. In other words, the first length d1 and the third length d3 can be respectively larger than the second length d2.

[0087] Reference Figure 5h , Figure 5h This is another cross-sectional structural schematic diagram of the chip in the embodiment of the present application during the preparation process, forming a gate structure 333 surrounding the channel region 311 of the vertical channel structure 320. Exemplarily, a deposition process or a growth process is used to form a gate oxide layer 3332, and the gate oxide layer 3332 covers the surface of the channel region 311, and the gate oxide layer 3332 also covers the surface of the first sidewall isolation layer 331 facing the channel region 311, and the gate oxide layer 3332 also covers the surface of the second sidewall isolation layer 332 facing the channel region 311. Afterwards, a work function metal is deposited to form a metal gate 3331, and the metal gate 3331 surrounds the channel region 311 through the gate oxide layer 3332.

[0088] Reference Figure 4 , a patterning process is used to pattern the insulating layer, and a second contact hole CT2 penetrating the insulating layer 340 is formed in the insulating layer 340, and the second contact hole CT2 exposes the second source and drain region 315. Afterwards, a metal material is deposited in the second contact hole CT2 to form a second contact portion 352 connected to the second source and drain region 315. In addition, a gate contact portion connected to the metal gate 3331 and a third contact portion connected to the first source and drain region 314 are also formed. In addition, an ohmic contact is formed between the second contact portion 352 and the second source and drain region 315, an ohmic contact is also formed between the gate contact portion and the metal gate 3331, and an ohmic contact is also formed between the third contact portion and the first source and drain region 314.

[0089] Figure 6 This is another schematic diagram of the structure of the chip in the embodiment of the present application, referring to Figure 6, in the chip 300 of the embodiments of the present application, a deformation is made to the implementation manner of the chip 300 in the Figure 2 illustrated embodiment. Only the differences between this embodiment and the above embodiments are described below, and the same parts are not elaborated herein. The differences between this embodiment and the Figure 2 illustrated embodiment are as follows: In the direction from the channel region 311 to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the area S1 can also be gradually increased. For example, in the direction from the channel region 311 to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the first length d1 can also be gradually increased so that the area S1 is gradually increased in the direction from the channel region 311 to the first source / drain extension region 312 (i.e., the direction away from the F0 arrow). And, in the direction from the channel region 311 to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the area S3 can be gradually increased. For example, in the direction from the channel region 311 to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the third length d3 can also be gradually increased so that the area S3 is gradually increased in the direction from the channel region 311 to the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow).

[0090] In addition, when manufacturing the Figure 6 illustrated chip, it can be obtained by performing corresponding etching on the first source / drain extension region 312 after manufacturing the Figure 3i illustrated structure. Among them, for the gap left between the first source / drain extension region 312 and the first sidewall isolation layer 331 after etching the first source / drain extension region 312, it can be filled with the material of the first sidewall isolation layer 331 or the material of the gate oxide layer, and the details are not elaborated herein. And, it can also be obtained by performing corresponding etching on the second source / drain extension region 313 after manufacturing the Figure 3i illustrated structure. Among them, for the gap left between the second source / drain extension region 313 and the second sidewall isolation layer 332 after etching the second source / drain extension region 313, it can be filled with the material of the second sidewall isolation layer 332 or the material of the gate oxide layer, and the details are not elaborated herein.

[0091] Figure 7 is another structural schematic diagram of the chip in the embodiments of the present application. Referring to Figure 7 , in the chip 300 of the embodiments of the present application, a deformation is made to the implementation manner of the chip 300 in the Figure 4 illustrated embodiment. Only the differences between this embodiment and the above embodiments are described below, and the same parts are not elaborated herein. The differences between this embodiment and the Figure 4The difference in the illustrated embodiment is that in the direction from the channel region 311 towards the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the area S1 can also be gradually increased. For example, in the direction from the channel region 311 towards the first source / drain extension region 312 (i.e., the direction away from the F0 arrow), the first length d1 can also be gradually increased to gradually increase the area S1 in the direction from the channel region 311 towards the first source / drain extension region 312 (i.e., the direction away from the F0 arrow). Also, in the direction from the channel region 311 towards the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the area S3 can be gradually increased. For example, in the direction from the channel region 311 towards the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow), the third length d3 can also be gradually increased to gradually increase the area S3 in the direction from the channel region 311 towards the second source / drain extension region 313 (i.e., the direction pointed by the F0 arrow).

[0092] In addition, when fabricating Figure 7 the illustrated chip, it can be obtained by performing corresponding etching on the first source / drain extension region 312 after fabricating Figure 5g the illustrated structure. Among them, for the gap left between the first source / drain extension region 312 and the first sidewall isolation layer 331 after etching the first source / drain extension region 312, it can be filled with the material of the first sidewall isolation layer 331 or the material of the gate oxide layer, and the details are not elaborated here. Also, it can be obtained by performing corresponding etching on the second source / drain extension region 313 after fabricating Figure 5g the illustrated structure. Among them, for the gap left between the second source / drain extension region 313 and the second sidewall isolation layer 332 after etching the second source / drain extension region 313, it can be filled with the material of the second sidewall isolation layer 332 or the material of the gate oxide layer, and the details are not elaborated here.

[0093] The above content is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application.

Claims

1. A chip, characterized in that, comprising: a substrate and a vertical transfer field effect transistor disposed on the substrate, the vertical transfer field effect transistor comprising: a vertical channel structure including a first source / drain extension region, a channel region, and a second source / drain extension region sequentially arranged in a vertical direction. In the vertical direction, the cross-sectional area of at least one of the first source / drain extension region and the second source / drain extension region is larger than the cross-sectional area of the channel region; the vertical direction is perpendicular to the plane where the substrate is located; a stacked structure including a first sidewall isolation layer, a gate structure, and a second sidewall isolation layer sequentially arranged in the vertical direction. The first sidewall isolation layer surrounds the first source / drain extension region, the gate structure surrounds the channel region, and the second sidewall isolation layer surrounds the second source / drain extension region.

2. The chip according to claim 1, characterized in that, the cross-section of the first source / drain extension region in the vertical direction has a first length along a first direction, the cross-section of the channel region in the vertical direction has a second length along the first direction, the first length is greater than the second length, and the first direction is perpendicular to the vertical direction.

3. The chip according to claim 2, characterized in that, in the direction from the channel region to the first source / drain extension region, the first length is the same or gradually increases.

4. The chip according to claim 2 or 3, characterized in that, the first length is 1.2 times to 2 times the second length.

5. The chip according to any one of claims 1-4, characterized in that, the cross-section of the second source / drain extension region in the vertical direction has a third length along a first direction, the cross-section of the channel region in the vertical direction has a second length along the first direction, the third length is greater than the second length, and the first direction is perpendicular to the vertical direction.

6. The chip according to claim 5, characterized in that, in the direction from the channel region to the second source / drain extension region, the third length is the same or gradually increases.

7. The chip according to claim 5 or 6, characterized in that, the third length is 1.2 times to 2 times the second length.

8. The chip according to any one of claims 1-7, characterized in that, the area of the first cross-section of the first source / drain extension region in the vertical direction is the same as the area of the second cross-section of the second source / drain extension region in the vertical direction; there is a first distance between the interface of the channel region and the first source / drain extension region and the first cross-section, and there is a second distance between the interface of the channel region and the second source / drain extension region and the second cross-section, and the first distance is the same as the second distance.

9. The chip according to claim 8, characterized in that, the first cross-section has a first length along a first direction, the second cross-section has a third length along the first direction, the first length is the same as the third length, and the first direction is perpendicular to the vertical direction.

10. The chip according to any one of claims 1-9, characterized in that, The doping concentration of the first source / drain extension region is greater than that of the channel region; or, The doping concentration of the second source / drain extension region is greater than that of the channel region; or, The doping concentrations of the first source / drain extension region and the second source / drain extension region are the same.

11. The chip according to any one of claims 1-10, characterized in that the vertical channel structure further includes: a first source / drain region disposed on a side of the channel region facing the first source / drain extension region, and a second source / drain region disposed on a side of the channel region facing the second source / drain extension region, the first source / drain region is connected to the first source / drain extension region, and the second source / drain region is connected to the second source / drain extension region.

12. The chip according to claim 11, characterized in that the doping concentration of the first source / drain extension region is less than that of the first source / drain region; or, the doping concentration of the second source / drain extension region is less than that of the second source / drain region; or, the doping concentrations of the first source / drain region and the second source / drain region are the same.

13. The chip according to claim 11 or 12, characterized in that the second source / drain region is disposed on a side of the channel region facing away from the substrate, the second sidewall isolation layer further covers the second source / drain region, and the second sidewall isolation layer has a first contact hole for exposing the second source / drain region, and a first contact portion connected to the second source / drain region is filled in the first contact hole.

14. The chip according to claim 11 or 12, characterized in that the second source / drain region is disposed on a side of the channel region facing away from the substrate, the vertical transmission field effect transistor further includes: an insulating layer covering the second source / drain region and the second sidewall isolation layer, the insulating layer has a second contact hole for exposing the second source / drain region, and a second contact portion connected to the second source / drain region is filled in the second contact hole.

15. An electronic device, characterized in that comprising: a circuit board and a chip according to any one of claims 1-14, the chip is disposed on the circuit board.

16. A method for manufacturing a chip, characterized in that comprising: forming an initial vertical channel structure, a first sidewall isolation layer, a sacrificial layer, and a second sidewall isolation layer on a substrate, the initial vertical channel structure includes a first source / drain region, a first source / drain extension region, a channel region, a second source / drain extension region, and a second source / drain region sequentially arranged along the vertical direction, and in the vertical direction, the cross-sectional areas of the first source / drain extension region, the second source / drain extension region, and the channel region are the same; the first sidewall isolation layer surrounds the first source / drain extension region, the second sidewall isolation layer surrounds the second source / drain extension region, and the sacrificial layer surrounds the channel region; etching and removing the sacrificial layer to expose the channel region; Etch the channel region in the initial vertical channel structure, and in the vertical direction, make the cross-sectional area of the first source / drain extension region and the cross-sectional area of the second source / drain extension region respectively larger than the cross-sectional area of the channel region to form the channel region in the vertical channel structure; Form a gate structure surrounding the channel region of the vertical channel structure.

17. The manufacturing method according to claim 16, characterized in that, the forming of the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer and the second sidewall isolation layer on the substrate includes: Performing ion doping in the substrate to form the first source / drain region; Epitaxially growing a first epitaxial layer on the substrate, the first epitaxial layer including a first source / drain extension region, a channel region, a second source / drain extension region and a second source / drain region arranged in sequence along the vertical direction; Performing patterning on the first epitaxial layer to form the initial vertical channel structure; Depositing the first sidewall isolation layer surrounding the first source / drain extension region of the initial vertical channel structure; Depositing the sacrificial layer surrounding the channel region of the initial vertical channel structure; Depositing the second sidewall isolation layer surrounding the second source / drain extension region of the initial vertical channel structure.

18. The manufacturing method according to claim 17, characterized in that, further comprising: When depositing the second sidewall isolation layer surrounding the second source / drain extension region of the initial vertical channel structure, also making the second sidewall isolation layer cover the second source / drain region; After forming the gate structure surrounding the channel region of the vertical channel structure, performing patterning on the second sidewall isolation layer to form a first contact hole exposing the second source / drain region, and depositing a metal material in the first contact hole to form a first contact portion connected to the second source / drain region.

19. The manufacturing method according to claim 16, characterized in that, the forming of the initial vertical channel structure, the first sidewall isolation layer, the sacrificial layer and the second sidewall isolation layer on the substrate includes: Performing ion doping in the substrate to form the first source / drain region; Sequentially depositing the first sidewall isolation layer, the sacrificial layer and the second sidewall isolation layer on the substrate; Performing patterning on the first sidewall isolation layer, the sacrificial layer and the second sidewall isolation layer to form a groove penetrating through the first sidewall isolation layer, the sacrificial layer and the second sidewall isolation layer, exposing the first source / drain region; Epitaxially growing a second epitaxial layer in the groove, the second epitaxial layer including a first source / drain extension region, a channel region, a second source / drain extension region and a second source / drain region arranged in sequence along the vertical direction, and the interface between the second source / drain extension region and the second source / drain region is aligned with the surface of the second sidewall isolation layer facing away from the sacrificial layer.

20. The manufacturing method according to claim 19, characterized in that, further comprising: After epitaxially growing the initial vertical channel structure in the groove, depositing an insulating layer to make the insulating layer cover the second source / drain region and the second sidewall isolation layer; After forming a gate structure for a channel region surrounding the vertical channel structure, the insulating layer is patterned to form a second contact hole exposing the second source / drain region, and a metal material is deposited in the second contact hole to form a second contact portion connected to the second source / drain region.

Images