Lock input and output logic detection method

Abstract

The invention discloses a locking input and output logic detection method, which belongs to the field of electronic circuit system fault detection, and comprises the following steps: determining a logic unit for executing a locking function, constructing a logic judgment function, and calculating a theoretical output signal and a logic judgment clock coefficient; setting a dynamic clock offset range of the input signal, and setting a dynamic clock offset threshold value of the input signal based on the importance degree; calculating a clock coefficient after the dynamic clock skew simulation and an average value of the clock coefficients after the dynamic clock skew simulation; evaluating a response fault condition of the logic unit; and calculating all theoretical output signals output by the logic unit based on the logic judgment function, calculating the matching degree of output response, and evaluating whether the output logic response of the logic unit is normal or not. According to the method, the detection efficiency of the locking logic is remarkably improved, and the method is also suitable for chip design verification, hardware circuit fault diagnosis and embedded system reliability evaluation.

Description

Technical Field

[0001] The present invention relates to the field of fault detection of electronic circuit systems, and particularly to a method for detecting the logic of latch input and output. Background Art

[0002] In a digital circuit system, the functional correctness of a latch logic unit (such as a latch, register, tri-state buffer, etc.) directly affects the system reliability; the delay detection of output and output logic judgment and the accuracy detection of output signals are very crucial for ensuring the normal use of the latch logic unit. In the prior art, the detection methods or systems for latch logic units mainly have the following defects: 1. Insufficient static detection coverage: Traditional logic detection only verifies fixed input combinations, cannot cover dynamic clock deviations, and cannot verify the fault conditions of random dynamic clock deviations; 2. Lack of a quantitative standard for response verification: It relies on manual interpretation of output waveforms, resulting in a high misjudgment rate. Therefore, there is an urgent need for a new method for detecting the logic of latch input and output. Summary of the Invention

[0003] In view of the above deficiencies of the prior art, the present invention provides a method for detecting the logic of latch input and output, which evaluates the response faults of the logic unit and the output logic response faults by randomly and dynamically simulating the clock offset of the logic unit.

[0004] To achieve the above invention objective, the technical solution adopted by the present invention is as follows: Provide a method for detecting the logic of latch input and output, which includes: Step S1: Determine the logic unit that performs the latch function, establish an input signal set and an output signal set, set the clock constraint of the logic unit, construct a logic judgment function, calculate the theoretical output signal and the clock coefficient of the logic judgment; Step S2: Characterize the importance of the input signal according to the frequency of the input signal input to the logic unit, set the dynamic clock offset range of the input signal, and set the dynamic clock offset threshold of the input signal based on the importance; Step S3: Randomly and dynamically simulate the clock offset of the input signal based on the dynamic clock offset range, and calculate the clock coefficient after the dynamic clock offset simulation and the average value of the clock coefficients simulated by the dynamic clock offset; Step S4: Evaluate the response fault condition of the logic unit according to the error value between the average value of the clock coefficients and the clock coefficient; Step S5: Calculate all the theoretical output signals output by the logic unit based on the logic judgment function, construct a matching degree function of the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal.

[0005] Further, step S1 includes: Step S11: Determine the logic unit that executes the locking function, and establish the input signal set and output signal set of the logic unit of the logic unit, where is the number of input signals, N is the number of output signals, M is the th input signal, N and the M th output signal; Step S12: Set the clock constraints of the logic unit, including the setup time , hold time and propagation delay . The setup time represents the minimum time for the input signal to remain stable before the active edge of the clock, and the hold time represents the minimum time for the input signal to remain stable after the active edge of the clock. The propagation delay represents the time interval from the input change to the output stability; Step S13: According to the clock constraints of the logic unit and the logic judgment function executed by the logic unit, establish the logic judgment function of each logic function, and calculate the theoretical output signal and the clock coefficient of the logic judgment.

[0006] Further, the logic judgment function is: ; where is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for the logic judgment, is the input signal set the I th input signal in i , is the number of the input signal in the input signal set is the input signal in the input signal set , I is the input signal set the number of input signals in is the clock coefficient of the logic judgment, is the mapping function of the input signal, is the total mapping function, are respectively the setup time, hold time and propagation delay of the input signal in the logic judgment process, is the natural logarithm function, They are the weight coefficients of the influence of setup time, hold time, and propagation delay on the clock coefficient respectively.

[0007] Further, step S2 includes: Step S21: Calculate the frequency of the input signal required for each output signal output by the logic unit , is the number of times the output signal is used, and the frequency is used as the importance degree coefficient of the input signal for the logic unit; Step S22: Set the dynamic clock offset range of the input signal , and calculate the dynamic clock offset threshold of the input signal ; ; is the maximum allowable clock deviation.

[0008] Further, step S3 includes: Step S31: Randomly select a dynamic clock offset value from the dynamic clock offset range , compare the dynamic clock offset value with the dynamic clock offset threshold . If is satisfied, then the dynamic clock offset value is used as the clock offset simulation value of the input signal , and step S32 is executed. Otherwise, randomly select a dynamic clock offset value again from the dynamic clock offset range ; Step S32: Allocate the clock offset simulation value according to the weight coefficient to obtain the setup time simulation value , hold time simulation value , and propagation delay simulation value corresponding to the input signal ; ; Step S33: Repeat steps S31 - S32 to obtain the setup time simulation value, hold time simulation value, and propagation delay simulation value of each input signal under the dynamic clock offset simulation condition; Step S34: Calculate the clock coefficient under the dynamic clock offset simulation condition ; ; wherein, are respectively the setup time simulation value, hold time simulation value, and propagation delay simulation value of the input signal under the dynamic clock offset simulation condition; Step S35: Repeat steps S31 - S34 to perform dynamic clock offset simulations within the dynamic clock offset range U for U times, and obtain the clock coefficients calculated after each dynamic clock offset simulation ; Step S36: Calculate the average value of the clock coefficients simulated by the dynamic clock offset ; wherein, u is the simulation number of the dynamic clock offset, is the u th clock coefficient calculated by the dynamic clock offset simulation.

[0009] Furthermore, step S4 is specifically as follows: Calculate the error value between the average value of the clock coefficients and the clock coefficient , and evaluate the response fault condition of the logic unit based on the allowed error threshold ; If , it is determined that the logic unit has a response fault; If , it is determined that the logic unit does not have a response fault.

[0010] Furthermore, step S5 specifically includes: Step S51: Based on the logic judgment function for each logic judgment function implemented by the logic unit, calculate all theoretical output signals output by the logic unit, construct a matching degree function for the output response, and calculate the matching degree of the output response of the logic unit according to the theoretical output signal and the actual output signal , Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the logic unit is normal; If , the output logic response of the logic unit is normal. If , the output logic response of the logic unit is abnormal.

[0011] Furthermore, the matching degree function of the output response is: ; wherein, , is the weight coefficient of the clock deviation, is the weight coefficient of the output signal error.

[0012] The beneficial effects of the present invention are as follows: By establishing a logical judgment function that realizes the logical judgment function within the logical unit, the present invention calculates the theoretical output signal and the clock coefficient of the logical judgment, constructs a matching degree function for the output response to evaluate whether there is a fault in the output logic response of the logical unit. Moreover, by randomly and dynamically simulating the clock offset to characterize the possible clock deviation that may actually occur in the logical unit, it is used to evaluate whether the logical unit has a response fault, solving the problem of insufficient timing coverage in traditional static detection. The present invention significantly improves the detection efficiency of the locking logic and can also be applied to chip design verification, hardware circuit fault diagnosis, and reliability evaluation of embedded systems. Description of the Drawings

[0013] Figure 1 It is a flowchart of the locking input / output logic detection method. Detailed Embodiment

[0014] The following describes the detailed embodiment of the present invention to facilitate those skilled in the art to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the detailed embodiment. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions created using the concept of the present invention are within the scope of protection.

[0015] As Figure 1 shown, a locking input / output logic detection method includes: Step S1: Determine the logical unit that performs the locking function, establish an input signal set and an output signal set, set the clock constraint of the logical unit, construct a logical judgment function, and calculate the theoretical output signal and the clock coefficient of the logical judgment. Step S1 specifically includes: Step S11: Determine the logical unit that performs the locking function and establish the input signal set and the output signal set , where N is the number of input signals, M is the number of output signals, is the N th input signal, the M th output signal; Step S12: Set the clock constraint of the logical unit, including the setup time , the hold time and the propagation delay . The setup time represents the minimum time for the input signal to remain stable before the active edge of the clock, and the hold time represents the minimum time for the input signal to remain stable after the active edge of the clock. The propagation delay Indicates the time interval from the input change to the output stabilization; Step S13: According to the clock constraint of the logic unit and the logic judgment function executed by the logic unit, establish the logic judgment function of each logic function, and calculate the theoretical output signal and the clock coefficient of the logic judgment.

[0016] ; Wherein, is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for the logic judgment, is the set of input signals in the I th input signal, i is the set of input signals in the number of input signals, is the set of input signals in the input signal, I is the set of input signals in the number of input signals, is the clock coefficient of the logic judgment, is the mapping function of the input signal, is the total mapping function, are respectively the setup time, hold time and propagation delay of the input signal in the logic judgment process, is the natural logarithm function, are respectively the weight coefficients of the influence of the setup time, hold time and propagation delay on the clock coefficient, and satisfy , generally take .

[0017] In this embodiment, the theoretical output signal of each logic judgment function executed by the logic unit is output through the logic judgment function, and the mapping function maps each input signal to the corresponding logic operator, for example, 0 and 1, 0 represents false, 1 represents true, and the total mapping function is used to integrate all logic operators and map them to the corresponding output signal function In, the output signal function generates the logic operation label required for the output output signal. The output signal function generates the logic operation label required for the output output signal.

[0018] In the substation automation system, the input signals of the embodiments include, but are not limited to, the signals accessed through the auxiliary contacts of equipment such as circuit breakers, disconnectors, and earthing switches in the circuit system. The logic unit realizes different anti-maloperation interlocking functions and forced interlocking functions through the judgment of the accessed signals, which can cover all aspects such as the operation, operation, and maintenance of the substation. An independent logic judgment function unit can be built in the logic unit to control and operate equipment such as circuit breakers and motor-operated disconnectors.

[0019] The input signal objects of the logic judgment function include: neutral earthing disconnector of the main transformer, on-load tap-changer of the main transformer, motor-operated disconnector, signal reset, input and withdrawal of the microcomputer protection device, switching of the microcomputer protection setting group, etc.

[0020] During the logic judgment process, a clock coefficient is calculated and generated for each output signal according to the clock error. The clock coefficient represents the clock offset degree during the logic judgment process, and the fault condition of the output response of the logic unit can be reflected through the clock coefficient.

[0021] Step S2: Characterize the importance degree of the input signal according to the frequency of the input signal input into the logic unit, set the dynamic clock offset range of the input signal, and set the dynamic clock offset threshold of the input signal based on the importance degree. Step S2 specifically includes: Step S21: Calculate the frequency of the input signal required for the logic unit to output each output signal , is the number of times the output signal is used, and the frequency is used as the importance degree coefficient of the input signal for the logic unit; When the logic unit executes different logic judgment functions, sometimes multiple input signals are required, and the input signals required between different logic judgment functions are neither independent nor unique. The higher the frequency of the input signal used by the logic unit, the more important it is to the logic unit. Abnormal clock offsets of the input signals often cause fluctuations and abnormalities in the signal output of the logic unit.

[0022] Step S22: Set the dynamic clock offset range of the input signal , and calculate the dynamic clock offset threshold of the input signal ; ; is the maximum allowable clock deviation.

[0023] The dynamic clock offset range, as the ideal clock fluctuation range during the processing of the input and output signals of the logic unit, can simulate the clock deviation caused by factors such as signal processing delay fluctuations during the signal processing of the actual logic unit by introducing the simulation of random dynamic clock offsets. Thus, the latching input / output logic can be detected more comprehensively. The simulation of the random dynamic clock offsets introduced in the present invention meets the randomness requirements of the delay fluctuations in processes such as signal transmission and processing.

[0024] Step S3: Perform random dynamic simulation on the clock offset of the input signal based on the dynamic clock offset range, and calculate the clock coefficient after the dynamic clock offset simulation, as well as the average value of the clock coefficients simulated by the dynamic clock offset. Step S3 specifically includes: Step S31: Randomly select a dynamic clock offset value from within the dynamic clock offset range , compare the dynamic clock offset value with the dynamic clock offset threshold . If is satisfied, then use the dynamic clock offset value as the clock offset simulation value of the input signal , and execute Step S32. Otherwise, randomly select another dynamic clock offset value from within the dynamic clock offset range ; Step S32: Allocate the clock offset simulation value according to the weight coefficient to obtain the setup time simulation value , hold time simulation value , and propagation delay simulation value corresponding to the input signal ; ; Step S33: Repeat Steps S31 - S32 to obtain the setup time simulation value, hold time simulation value, and propagation delay simulation value of each input signal under the dynamic clock offset simulation condition; Step S34: Calculate the clock coefficient under the dynamic clock offset simulation condition; ; where are respectively the setup time simulation value, hold time simulation value, and propagation delay simulation value of the input signal under the dynamic clock offset simulation condition; Step S35: Repeat Steps S31 - S34, and perform times of dynamic clock offset simulation within the dynamic clock offset range U to obtain the clock coefficients calculated after each dynamic clock offset simulation ; Step S36: Calculate the average value of the clock coefficients simulated by the dynamic clock offset ; ; wherein, u is the serial number of the simulation times of the dynamic clock offset, is the u th clock coefficient calculated by the simulation of the dynamic clock offset.

[0025] Step S4: Evaluate the response failure condition of the logic unit according to the error value between the average value of the clock coefficients and the clock coefficients. Specifically, it includes: Calculate the average value of the clock coefficients and the clock coefficient to calculate the error value therebetween, and evaluate the response failure condition of the logic unit based on the allowable error threshold ; If , it is determined that the logic unit has a response failure; If , it is determined that the logic unit does not have a response failure.

[0026] Step S5: Calculate all theoretical output signals output by the logic unit based on the logic judgment function, construct a matching degree function of the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal. Step S5 specifically includes: Step S51: Based on the logic judgment function for each logic judgment function implemented by the logic unit, calculate all theoretical output signals output by the logic unit, and calculate the matching degree of the output response of the logic unit according to the theoretical output signal and the true output signal ; ; ; wherein, , is the weight coefficient of the clock deviation, indicating the influence degree of the clock deviation on the output response, and is taken according to the requirement of the system for the delay of the output signal, generally taken as 0.6 - 0.8, is the weight coefficient of the output signal error, and is taken according to the influence degree of the output signal error on the system, generally taken as 0.7 - 0.95; Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the logic unit is normal; If , the output logic response of the logic unit is normal, if , the output logic response of the logic unit is abnormal.

[0027] Matching degree threshold It is set according to the accuracy requirements for logical units in the system, generally taking 0.85 - 0.95. The matching degree of the output response is quantified through the constructed membership function of the output response to provide the robustness of the detection result.

[0028] The present invention calculates the theoretical output signal and the clock coefficient of the logical judgment by establishing a logical judgment function for realizing the logical judgment function within the logical unit, constructs a matching degree function of the output response to evaluate whether there is a fault in the output logic response of the logical unit. Moreover, the actual possible clock deviation of the logical unit is characterized by randomly dynamically simulating the clock offset, which is used to evaluate whether the logical unit has a response fault, solving the problem of insufficient timing coverage in traditional static detection. The present invention significantly improves the detection efficiency of the locking logic and can also be applied to chip design verification, hardware circuit fault diagnosis and embedded system reliability evaluation.

Claims

1. A method for detecting a locking input and output logic, characterized in that: include: Step S1: determine the logic unit that performs the locking function, establish the input signal set and the output signal set, set the clock constraint of the logic unit, construct the logic judgment function, and calculate the theoretical output signal and the clock coefficient of the logic judgment; Step S2: characterizing the importance of the input signal according to the frequency of the input signal inputting the logic unit, setting the dynamic clock offset range of the input signal, and setting the dynamic clock offset threshold of the input signal based on the importance; Step S3: performing random dynamic simulation on the clock offset of the input signal based on the dynamic clock offset range, and calculating the clock coefficient after the dynamic clock offset simulation and the average value of the clock coefficient after the dynamic clock offset simulation; Step S4: evaluating the response fault condition of the logic unit according to the average value of the clock coefficient and the error value between the clock coefficients; Step S5: Calculate all theoretical output signals output by the logic unit based on the logic judgment function, construct a matching function of the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal.

2. The method for detecting the locked input and output logic according to claim 1, characterized in that: The step S1 comprises: Step S11: Determine the logic unit that performs the blocking function and establish the input signal set of the logic unit And the output signal set ,in, N is the number of input signals, M is the number of output signals, For the N Input signal, No. M Output signal; Step S12: Set the clock constraints of the logic unit, including the setup time , keep time and propagation delay , build time Indicates the minimum time that the input signal needs to remain stable before the clock is valid. Indicates the minimum time that the input signal needs to remain stable after the clock valid edge, propagation delay It indicates the time interval from input change to output stabilization; Step S13: According to the clock constraints of the logic unit and the logic judgment function performed by the logic unit, a logic judgment function of each logic function is established, and a theoretical output signal and a clock coefficient of the logic judgment are calculated.

3. The method for detecting locked input and output logic according to claim 2, characterized in that: The logic judgment function is: ； in, is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for logical judgment. The input signal set Middle I Input signal, i The input signal set The number of the input signal in The input signal set The input signal in I The input signal set The number of input signals in is the clock coefficient of the logic judgment, is the mapping function of the input signal, is the total mapping function, They are the setup time, hold time and propagation delay of the input signal in the logic judgment process. is the natural logarithm function, They are the weight coefficients of the effects of setup time, hold time and propagation delay on the clock coefficient.

4. The method for detecting locked input and output logic according to claim 1, characterized in that: The step S2 comprises: Step S21: Calculate the frequency of the input signal required for the logic unit to output each output signal , The frequency is the number of times the output signal is used. As the importance coefficient of the input signal to the logic unit; Step S22: Setting the dynamic clock offset range of the input signal , and calculate the input signal Dynamic clock skew threshold ; is the maximum allowed clock skew.

5. The method for detecting locked input and output logic according to claim 4, characterized in that: The step S3 comprises: Step S31: From the dynamic clock offset range A dynamic clock offset value is randomly selected within , compare the dynamic clock offset value With dynamic clock skew threshold If the size of , then the dynamic clock offset value As input signal The clock offset simulation value is, step S32 is executed, otherwise, the dynamic clock offset range is A dynamic clock offset value is randomly re-selected within the Step S32: According to the weight coefficient Distribute the clock offset analog value to get the input signal Corresponding setup time analog value , hold time analog value and propagation delay analog values ; ； Step S33: repeating steps S31-S32 to obtain a setup time simulation value, a hold time simulation value, and a propagation delay simulation value of each input signal under a dynamic clock offset simulation condition; Step S34: Calculate the clock coefficient under dynamic clock offset simulation conditions ; ； in, The input signals are The simulation values ​​of setup time, hold time and propagation delay under dynamic clock skew simulation conditions; Step S35: Repeat steps S31-S34, within the dynamic clock offset range Internal U Dynamic clock offset simulation is repeated to obtain the clock coefficient calculated after each dynamic clock offset simulation. ; Step S36: Calculate the average value of the clock coefficient simulated by the dynamic clock offset ; ； in, u is the number of simulations for dynamic clock offset, For the u The clock coefficient calculated by the sub-dynamic clock skew simulation.

6. The method for detecting locked input and output logic according to claim 5, characterized in that: The step S4 is specifically as follows: Calculate the average clock factor With clock coefficient The error value between Evaluate the logic unit's response to fault conditions; like , then it is determined that the logic unit has a response failure; like , it is determined that the logic unit has no response failure.

7. The method for detecting locked input and output logic according to claim 1, characterized in that: The step S5 specifically includes: Step S51: Based on the logic unit to implement the logic judgment function of each logic judgment function, calculate all theoretical output signals output by the logic unit, construct the matching function of the output response, and With the real output signal Calculate the matching degree of the output response of the logic unit , Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the logic unit is normal; If , then the output logic response of the logic unit is normal. , the output logic response of the logic unit is abnormal.

8. The method for detecting locked input and output logic according to claim 7, characterized in that: The matching function of the output response is: ； in, , is the weight coefficient of clock deviation, is the weight coefficient of the output signal error.

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