Chip module processing method, chip module and optical communication system

Abstract

The invention provides a chip module processing method, a chip module and an optical communication system, and the processing method comprises the steps: taking a substrate, and preparing an optical waveguide structure on the substrate; etching a first mounting groove in one side of the optical waveguide structure; performing a laser direct writing process in the first mounting groove to form a first mounting part and a second mounting part, wherein the height of the first mounting part is greater than or smaller than that of the second mounting part; and mounting the first laser on the first mounting part and mounting the second laser on the second mounting part by using a chip mounter. According to the chip module, the first mounting part and the second mounting part are processed through the laser direct writing process, so that the frequency of the preparation process required for processing the first mounting part and the second mounting part is reduced, the processing period of the first mounting part and the second mounting part is further shortened, and the processing production efficiency of the chip module is improved. The first laser and the second laser are installed through the chip mounter, and the precision of the installation positions of the first laser and the second laser is improved.

Description

Technical Field

[0001] This application relates to the technical field of optical communication systems, and particularly to a processing method for a chip module, a chip module, and an optical communication system. Background Art

[0002] With the gradual commercialization of the silicon-based photonics platform, silicon substrates and silicon nitride substrates, as the main photonics platforms, have proven to have excellent performance in both active components (such as high-speed photodetectors and modulators) and passive components (such as waveguides). However, due to the lack of a direct bandgap in silicon and silicon nitride, how to integrate efficient on-chip lasers (especially III-V materials) onto the silicon-based photonics platform has always been a key concern in the academic and industrial communities.

[0003] The silicon-based photonics platform includes a substrate, an optical waveguide structure disposed on the substrate, and a mounting groove. The laser is inverted and mounted on the mounting portion within the mounting groove. The mounting portion can control the precision of the mounting height of the laser, enabling the precise alignment of the laser with the optical waveguide structure. The optical signal emitted by the laser can be transmitted through the optical waveguide structure to the optical receiver to complete the propagation of the optical signal. In the prior art, the mounting groove and the mounting portion are formed by etching. When multiple lasers of different models are mounted on a silicon-based photonics platform, the heights of the mounting portions required for different models of lasers are different, resulting in a relatively high complexity of the etching process, that is, multiple etching processes are required, which makes the time required for etching the mounting groove and the mounting portion relatively long. At the same time, it is difficult to ensure the precision and consistency of multiple etching processes. Summary of the Invention

[0004] In view of this, this application provides a processing method for a chip module, a chip module, and an optical communication system to solve the problems of relatively high complexity of the etching process and great difficulty in ensuring the precision and consistency of multiple etching processes in the prior art.

[0005] The first aspect of the present application provides a processing method for a chip module. The chip module at least includes a silicon-based photonics platform, a first laser, and a second laser. The silicon-based photonics platform includes a substrate. The processing method of the chip module includes: taking the substrate and preparing an optical waveguide structure on the substrate, where the optical waveguide structure is used to propagate optical signals emitted by the first laser and the second laser; etching a first mounting groove on one side of the optical waveguide structure; performing a laser direct writing process in the first mounting groove to form a first mounting portion and a second mounting portion. Along the thickness direction of the substrate, the height of the first mounting portion is greater than or less than the height of the second mounting portion; using a pick-and-place machine to mount the first laser on the first mounting portion and the second laser on the second mounting portion. In the present application, the first mounting portion and the second mounting portion are processed by the laser direct writing process, reducing the number of preparation processes required for processing the first mounting portion and the second mounting portion, thereby shortening the processing cycle of the first mounting portion and the second mounting portion and improving the processing and production efficiency of the chip module. The first laser is placed on the first mounting portion by a pick-and-place machine, and the second laser is placed on the second mounting portion by a pick-and-place machine, improving the accuracy of the mounting positions of the first laser and the second laser, and further facilitating improving the stability and reliability of the optical signal transmission of the first laser and the second laser. Further, it is beneficial to improve the stability and reliability of the signal transmission between the chip module and the optical receiver.

[0006] In some embodiments, before the step of using a pick-and-place machine to mount the first laser on the first mounting portion and the second laser on the second mounting portion, the processing method of the chip module includes: performing a laser direct writing process in the first mounting groove and / or on the optical waveguide structure to form a first identifier and a second identifier; the step of using a pick-and-place machine to mount the first laser on the first mounting portion and the second laser on the second mounting portion includes: calibrating the pick-and-place machine with the first identifier; placing the first laser on the pick-and-place machine, and the pick-and-place machine attaching the first laser to the first mounting portion; calibrating the pick-and-place machine with the second identifier; placing the second laser on the pick-and-place machine, and the pick-and-place machine attaching the second laser to the second mounting portion. In the present application, the first identifier and the second identifier are processed by the laser direct writing process, improving the accuracy of the processing positions of the first identifier and the second identifier, and further facilitating improving the mounting position accuracy of the first laser and the second laser.

[0007] In some embodiments, the first laser includes a first electrode, and the second laser includes a third electrode; the step of attaching the first laser to the first mounting portion by a mounter includes: along the height direction of the first laser, the mounter attaches the side of the first laser provided with the first electrode to the first mounting portion; the step of attaching the second laser to the second mounting portion by the mounter includes: along the height direction of the second laser, the mounter attaches the side of the second laser provided with the third electrode to the second mounting portion. In the present application, the first laser and the second laser are inverted in the first mounting groove, so that the depth of the first mounting groove required in the height direction of the laser is smaller, reducing the processing difficulty of the first mounting groove and facilitating the improvement of the processing accuracy of the first mounting groove. At the same time, it is beneficial to shorten the processing time of the first mounting groove, shorten the processing cycle of the chip module, and improve the processing production efficiency of the chip module.

[0008] In some embodiments, before the step of using a mounter to mount the first laser on the first mounting portion and the second laser on the second mounting portion, the processing method of the chip module includes: processing a first electrode layer and a second electrode layer in the first mounting groove, the first electrode layer being used for electrically connecting with the first laser, and the second electrode layer being used for electrically connecting with the second laser. In the present application, the first electrode layer and the second electrode layer can facilitate the electrical connection between the first laser, the second laser and the silicon-based photon platform, facilitate the first laser to emit a first optical signal and the second laser to emit a second optical signal, simplify the electrical connection structure of the first laser and the second laser, and is beneficial to reducing the overall size of the chip module.

[0009] In some embodiments, the step of processing the first electrode layer and the second electrode layer in the first mounting groove is carried out simultaneously with the step of performing a laser direct writing process in the first mounting groove to form the first mounting portion and the second mounting portion; the step of performing a laser direct writing process in the first mounting groove to form the first mounting portion, the second mounting portion, the first electrode layer and the second electrode layer includes: coating a first photoresist in the first mounting groove, and the first photoresist is mixed with conductive particles; performing laser direct writing on the first photoresist to locally cure the first photoresist to form the first mounting portion, the second mounting portion, the first electrode layer and the second electrode layer; removing the uncured first photoresist. In the present application, the first electrode layer, the second electrode layer, the first mounting portion and the second mounting portion are processed simultaneously, shortening the processing cycle of the chip module and improving the processing production efficiency of the chip module. By processing the first electrode layer and the second electrode layer through the laser direct writing process, the position and size accuracy of the first electrode layer and the second electrode layer are improved, which is beneficial to improving the stability and reliability of the electrical connection between the silicon-based photon platform and the laser.

[0010] In some embodiments, the steps of processing the first electrode layer and the second electrode layer in the first installation groove are before or after the step of performing a laser direct writing process in the first installation groove to form the first installation portion and the second installation portion; the step of performing a laser direct writing process in the first installation groove to form the first installation portion and the second installation portion includes: coating a second photoresist in the first installation groove; performing laser direct writing on the second photoresist so that the second photoresist is locally cured to form the first installation portion and the second installation portion; removing the uncured second photoresist; the steps of processing the first electrode layer and the second electrode layer in the first installation groove include: sputtering a seed layer in the first installation groove; electroplating the seed layer to form an electroplated metal layer; covering a third photoresist on the surface of the electroplated metal layer; processing a first pattern and a second pattern on the third photoresist; etching the electroplated metal layer through the first pattern and the second pattern to form the first electrode layer and the second electrode layer; removing the third photoresist; or, the steps of processing the first electrode layer and the second electrode layer in the first installation groove include: covering a third photoresist in the first installation groove; processing a first pattern and a second pattern on the third photoresist; sputtering a seed layer in the first pattern, the second pattern, and on the surface of the third photoresist; electroplating the seed layer to form an electroplated metal layer; grinding the electroplated metal layer to remove the electroplated metal layer on the surface of the third photoresist and reduce the thickness of the electroplated metal layer in the first pattern and the second pattern to form the first electrode layer and the second electrode layer; removing the third photoresist. In the present application, since the processing steps of the first electrode layer and the second electrode layer are before or after the processing steps of the first installation portion and the second installation portion, therefore, it is not necessary to mix conductive metal particles in the first photoresist required for processing the first installation portion and the second installation portion, thereby increasing the range of optional materials for the first photoresist and reducing the material cost of processing the first installation portion and the second installation portion. By electroplating to process the first electrode layer and the second electrode layer, the processing difficulty and processing cost of the first electrode layer and the second electrode layer are reduced.

[0011] In some embodiments, after the steps of processing the first electrode layer and the second electrode layer in the first installation groove, the processing method of the chip module includes: preparing at least one first conductive bump on the first electrode layer and at least one second conductive bump on the second electrode layer, and the first electrode layer is electrically connected to the first laser through the first conductive bump, and the second electrode layer is electrically connected through the second conductive bump. In the present application, the first electrode layer is electrically connected to the first laser through the first conductive bump, and the second electrode layer is electrically connected to the second laser through the second conductive bump, reducing the thickness of the first electrode layer and the second electrode layer in the height direction of the laser, thereby reducing the material cost of the first electrode layer and the second electrode layer and facilitating shortening the processing cycle of the first electrode layer and the second electrode layer.

[0012] In some embodiments, before the steps of using a chip mounter to mount the first laser on the first mounting portion and the second laser on the second mounting portion, the processing method of the chip module includes: processing a second mounting groove on the first laser and a third mounting groove on the second laser; the steps of using a chip mounter to mount the first laser on the first mounting portion and the second laser on the second mounting portion include: placing the first laser on the first mounting portion so that the side wall of the first mounting portion abuts against the side wall of the second mounting groove, and placing the second laser on the second mounting portion so that the side wall of the second mounting portion abuts against the side wall of the third mounting groove. In the present application, the first mounting groove is used to accommodate at least part of the first mounting portion, and the first mounting portion can abut against the side wall of the first mounting groove to improve the accuracy of the mounting position of the first laser. The second mounting groove is used to accommodate at least part of the second mounting portion, and the second mounting portion can abut against the side wall of the second mounting groove to improve the accuracy of the mounting position of the second laser, improving the stability and reliability of the optical signal transmission of the first laser and the second laser, and improving the processing yield of the chip module.

[0013] In some embodiments, before the step of preparing an optical waveguide structure on a substrate, the processing method of the chip module includes: depositing a barrier layer on the substrate; covering a fourth photoresist on the barrier layer; using a lithography machine to process a third pattern on the fourth photoresist; etching a part of the barrier layer through the third pattern so that the barrier layer has a preset shape; removing the photoresist. In the present application, during the process of etching the first mounting groove, along the thickness direction of the substrate, the barrier layer can limit the etching depth of the etching material on the substrate, reducing the risk that the laser cannot be aligned with the optical waveguide structure due to too large or too small etching depth, thereby improving the working stability of the chip module.

[0014] The second aspect of the present application provides a chip module, which is made by the processing method of the chip module described in any one of the above. In the present application, using the processing method of the chip module described in any one of the above to process the chip module shortens the processing cycle of the chip module, improves the processing production efficiency of the chip module, and is beneficial to improving the processing accuracy of the chip module.

[0015] The third aspect of the present application provides an optical communication system, which includes a chip module and a photoreceiver. The chip module is made by the processing method of the chip module described in any one of the above. The photoreceiver is electrically connected or signal-connected to the chip module, and the photoreceiver is used to receive the light emitted by the first laser and / or the second laser. In the present application, using the processing method of the chip module described in any one of the above to process the chip module is beneficial to improving the processing accuracy of the chip module, and thus is beneficial to improving the stability and reliability of the signal transmission between the chip module and the photoreceiver. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0017] Figure 1 Schematic structural diagram of the chip module provided by the present application in one embodiment;

[0018] Figure 2 For Figure 1 Schematic structural diagram of the first laser in one embodiment in ;

[0019] Figure 3 For Figure 2 Partial enlarged view of part I in ;

[0020] Figure 4 For Figure 1 Schematic structural diagram of the second laser in one embodiment in ;

[0021] Figure 5 For Figure 4 Partial enlarged view of part II in ;

[0022] Figure 6 For Figure 1 Schematic structural diagram of the silicon-based photonics platform in one embodiment in ;

[0023] Figure 7 For Figure 1 Schematic structural diagram of the first laser in another embodiment in ;

[0024] Figure 8 For Figure 1 Schematic structural diagram of the second laser in another embodiment in ;

[0025] Figure 9 For Figure 1 Schematic structural diagram of the silicon-based photonics platform in another embodiment in ;

[0026] Figures 10 to 13 Flowchart of the processing method of the chip module provided by the present application in one embodiment;

[0027] Figures 14 to 20 Flowchart of the processing method of the chip module provided by the present application in another embodiment;

[0028] Figure 21 For Figure 1 Perspective view of the optical waveguide structure on the silicon-based photonics platform in one embodiment in.

[0029] Reference Signs:

[0030] 1 - Silicon Photonic Platform

[0031] 11 - Substrate

[0032] 12 - Optical Waveguide Structure

[0033] 121 - Upper Cladding

[0034] 122 - Waveguide Layer

[0035] 123 - Lower Cladding

[0036] 13 - First Installation Groove

[0037] 14 - First Installation Part

[0038] 15 - Second Installation Part

[0039] 16 - First Mark

[0040] 17 - Second Mark

[0041] 18 - First Electrode Layer

[0042] 181 - First Conductive Bump

[0043] 19 - Second Electrode Layer

[0044] 191 - Second Conductive Bump

[0045] 110 - Barrier Layer

[0046] 2 - First Laser

[0047] 21 - First Electrode

[0048] 22 - First Light - Emitting Region

[0049] 221 - First Waveguide Layer

[0050] 222 - First Active Layer

[0051] 223 - Second Waveguide Layer

[0052] 23 - First Substrate

[0053] 24 - Second Electrode

[0054] 25 - Second Installation Groove

[0055] 26 - First Cladding

[0056] 3 - Second Laser

[0057] 31 - Third Electrode

[0058] 32 - Second light-emitting region;

[0059] 321 - Third waveguide layer;

[0060] 322 - Second active layer;

[0061] 323 - Fourth waveguide layer;

[0062] 33 - Second substrate;

[0063] 34 - Fourth electrode;

[0064] 35 - Third mounting groove;

[0065] 36 - Second cladding. Detailed implementation manners

[0066] For a better understanding of the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0067] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0068] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0069] It should be understood that the term " / and / " used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0070] The embodiments of the present application provide an optical communication system, which can be applied to mobile phones, computers, smart helmets, AR devices, VR devices or communication base stations. The embodiments of the present application do not make special limitations on the application scenarios of the optical communication system. The optical communication system includes at least one chip module and at least one optical receiver. As Figure 1 shown, the chip module includes a silicon-based photonics platform 1 and a laser mounted on the silicon-based photonics platform 1. The laser is used to emit optical signals. An optical waveguide structure 12 for conducting optical signals is provided on the silicon-based photonics platform 1. That is, the optical signals emitted by the laser are transmitted to the optical receiver by the optical waveguide structure 12, and the optical receiver processes, identifies or re-transmits the received optical signals.

[0071] The laser is installed on the silicon-based photonics platform 1, which improves the integration of the laser and the silicon-based photonics platform 1, reduces the total installation size of the laser and the silicon-based photonics platform 1, thereby facilitating the reduction of the overall size of the optical communication system and the installation of the optical communication system, and further facilitating the reduction of the size of the device equipped with the optical communication system.

[0072] Among them, at least one laser is installed on one silicon-based photonics platform 1. When the number of lasers is multiple, as Figure 1 shown, according to the types of optical signals emitted by the lasers, the lasers are at least divided into a first laser 2 and a second laser 3 to improve the working performance of the chip module and the optical communication system.

[0073] As Figure 2 shown, the first laser 2 at least includes a first electrode 21, a first light-emitting region 22, a first substrate 23, and a second electrode 24 that are stacked along the height direction of the first laser 2 itself. Among them, along the height direction of the first laser 2, a first cladding layer 26 is covered on the side of the first light-emitting region 22 away from the first substrate 23, so that at least part of the first electrode 21 is exposed and the first light-emitting region 22 is covered. The first light-emitting region includes a first waveguide layer 221, a first active layer 222, and a second waveguide layer 223. The first waveguide layer 221 is located between the first active layer 222 and the first electrode 21, and the second waveguide layer 223 is located between the first active layer 222 and the first substrate 23. The first active layer 222 is used to emit a first optical signal. Along the height direction of the first laser 2, the vertical distance between the first active layer 222 and the first electrode 21 is less than the vertical distance between the first active layer 222 and the second electrode 24.

[0074] As Figure 4 shown, the second laser 3 at least includes a third electrode 31, a second light-emitting region 32, a second substrate 33, and a fourth electrode 34 that are stacked along the height direction of the second laser 3 itself. Among them, along the height direction of the second laser 3, a second cladding layer 36 is covered on the side of the second light-emitting region 32 away from the second substrate 33, so that at least part of the third electrode 31 is exposed and the second light-emitting region 32 is covered. The second light-emitting region 32 includes a third waveguide layer 321, a second active layer 322, and a fourth waveguide layer 323. The third waveguide layer 321 is located between the second active layer 322 and the third electrode 31, and the fourth waveguide layer 323 is located between the second active layer 322 and the fourth electrode 34. The second active layer 322 is used to emit a second optical signal. Along the height direction of the second laser 3, the vertical distance between the second active layer 322 and the third electrode 31 is less than the vertical distance between the second active layer 322 and the fourth electrode 34.

[0075] As Figure 6As shown in the figure, the silicon-based photonics platform 1 includes a substrate 11, an optical waveguide structure 12 disposed on the substrate 11, a first mounting groove 13 disposed on one side of the optical waveguide structure 12. In the first mounting groove 13, there is a first electrode layer 18 for electrically connecting with the first laser 2, a second electrode layer 19 for electrically connecting with the second laser 3, a first mounting portion 14 for fixing the first laser 2, and a second mounting portion 15 for fixing the second laser 3. The first mounting portion 14 is used to improve the accuracy of the mounting height of the first laser 2 in its own height direction, so as to facilitate the alignment of the first active layer 222 with the optical waveguide structure 12, thereby improving the stability and reliability of the transmission of the first optical signal between the first laser 2 and the optical waveguide structure 12. Similarly, the second mounting portion 15 is used to improve the accuracy of the mounting height of the second laser 3 in its own height direction, so as to facilitate the alignment of the second active layer 322 with the optical waveguide structure 12, thereby improving the stability and reliability of the transmission of the second optical signal between the second laser 3 and the optical waveguide structure 12.

[0076] The contour shape of the first electrode layer 18 can be circular, triangular, quadrilateral, L-shaped, U-shaped or other deformed structures. The embodiments of the present application do not make special limitations on the contour shape of the first electrode layer 18; the contour shape of the second electrode layer 19 can be circular, triangular, quadrilateral, L-shaped, U-shaped or other deformed structures. The embodiments of the present application do not make special limitations on the contour shape of the second electrode layer 19.

[0077] Among them, as Figure 21 shown, the optical waveguide structure 12 includes an upper cladding layer 121, a waveguide layer 122 and a lower cladding layer 123 stacked along its own thickness direction. The first active layer 222 of the first laser 2 and the second active layer 322 of the second laser 3 are both aligned with the waveguide layer 122.

[0078] Since the first optical signal is different from the second optical signal, the heights of the first laser 2 and the second laser 3 are different, that is, the vertical distance between the first active layer 222 and the first electrode 21 is different from the vertical distance between the second active layer 322 and the third electrode 31, and / or the vertical distance between the first active layer 222 and the second electrode 24 is different from the vertical distance between the second active layer 322 and the fourth electrode 34. Therefore, along the height direction of the laser, the heights of the first mounting portion 14 and the second mounting portion 15 are different, so that along the distribution direction of the optical waveguide structure 12 and the first mounting groove 13, the first active layer 222 and the second active layer 322 are simultaneously aligned with the optical waveguide structure 12, simplifying the complexity of the optical waveguide structure 12, thereby reducing the processing cost of the optical waveguide structure 12 and facilitating shortening the processing cycle of the optical waveguide structure 12.

[0079] In one embodiment, the first electrode layer 18 is directly electrically connected to the first laser 2 to simplify the structure of the first electrode layer 18 and shorten the processing cycle of the first electrode layer 18; in another embodiment, as Figure 6 shown, at least one first conductive bump 181 is provided on the first electrode layer 18, and the first electrode layer 18 is electrically connected to the first laser 2 through the first conductive bump 181 to reduce the thickness of the first electrode layer 18 in the height direction of the first laser 2 and reduce the material cost of the first electrode layer 18. Among them, the contour shape of the first conductive bump 181 can be spherical, hemispherical, pyramid, frustum or other deformed structures, and the number of the first conductive bumps 181 can be one or not less than two. A plurality of first conductive bumps 181 can be arranged in a linear shape, a two-character shape, an L shape, a Sichuan character shape or other deformed shapes. The embodiments of the present application do not make special limitations on the structural shape and distribution mode of the first conductive bumps 181.

[0080] In one embodiment, the second electrode layer 19 is directly electrically connected to the second laser 3 to simplify the structure of the second electrode layer 19 and shorten the processing cycle of the second electrode layer 19; in another embodiment, as Figure 6 shown, at least one second conductive bump 191 is provided on the second electrode layer 19, and the second electrode layer 19 is electrically connected to the second laser 3 through the second conductive bump 191 to reduce the thickness of the second electrode layer 19 in the height direction of the second laser 3 and reduce the material cost of the second electrode layer 19. Among them, the contour shape of the second conductive bump 191 can be spherical, hemispherical, pyramid, frustum or other deformed structures, and the number of the second conductive bumps 191 can be one or not less than two. A plurality of second conductive bumps 191 can be arranged in a linear shape, a two-character shape, an L shape, a Sichuan character shape or other deformed shapes. The embodiments of the present application do not make special limitations on the structural shape and distribution mode of the second conductive bumps 191.

[0081] As Figure 6 and Figure 9 shown, the contour shape of the first mounting portion 14 can be spherical, conical, rectangular, trapezoidal or other deformed structures. As Figure 6 shown, when the contour shape of the first mounting portion 14 is rectangular, the structure of the first laser 2 can be as Figure 2 shown, and the first laser 2 is directly pasted and fixed on the surface of the first mounting portion 14 to simplify the structures of the first laser 2 and the first mounting portion 14; as Figure 9 shown, when the contour shape of the first mounting portion 14 is spherical, as Figure 7As shown, a second mounting groove 25 is provided on the surface of the first laser 2 for abutting against the first mounting portion 14. The first mounting groove 13 is used to accommodate at least a part of the first mounting portion 14, and the first mounting portion 14 can abut against the side wall of the first mounting groove 13 to improve the accuracy of the mounting position of the first laser 2.

[0082] As Figure 6 and Figure 9 shown, the contour shape of the second mounting portion 15 can be spherical, conical, rectangular, trapezoidal or other deformed structures. As Figure 6 shown, when the contour shape of the second mounting portion 15 is rectangular, the structure of the second laser 3 can be as Figure 4 shown, the second laser 3 is directly pasted and fixed on the surface of the second mounting portion 15 to simplify the structures of the second laser 3 and the second mounting portion 15. As Figure 9 shown, when the contour shape of the second mounting portion 15 is spherical, as Figure 8 shown, a second mounting groove 25 is provided on the surface of the second laser 3 for abutting against the second mounting portion 15. The second mounting groove 25 is used to accommodate at least a part of the second mounting portion 15, and the second mounting portion 15 can abut against the side wall of the second mounting groove 25 to improve the accuracy of the mounting position of the second laser 3.

[0083] The first electrode 21 of the first laser 2 is electrically connected to the first electrode layer 18, or the second electrode 24 of the first laser 2 is electrically connected to the first electrode layer 18. The third electrode 31 of the second laser 3 is electrically connected to the second electrode layer 19, or the fourth electrode 34 of the second laser 3 is electrically connected to the second electrode layer 19. In this embodiment, the first electrode 21 of the first laser 2 is electrically connected to the first electrode layer 18, and the third electrode 31 of the second laser 3 is electrically connected to the second electrode layer 19, so that the depth of the first mounting groove 13 required in the height direction of the laser is smaller, thereby reducing the processing difficulty of the first mounting groove 13 and being beneficial to improving the processing accuracy of the first mounting groove 13.

[0084] In one embodiment, during the assembly of the laser and the silicon-based photonics platform 1, the first laser 2 is directly placed on the first mounting portion 14 by hand or a manipulator, and the second laser 3 is directly placed on the second mounting portion 15 by hand or a manipulator to simplify the installation operation of the laser. In another embodiment, the first laser 2 is placed on the first mounting portion 14 by a pick-and-place machine, and the second laser 3 is placed on the second mounting portion 15 by a pick-and-place machine to improve the mounting position accuracy of the first laser 2 and the second laser 3, and thus is beneficial to improving the stability and reliability of the optical signal transmission of the first laser 2 and the second laser 3.

[0085] When the first laser 2 is placed on the first mounting portion 14 by a pick-and-place machine, asFigure 6 and Figure 9 As shown in Figure 9 , a first identifier 16 is provided in the first installation groove 13 and / or on the optical waveguide structure 12. The mounter can calibrate the first identifier 16 with the origin of its own system to improve the installation accuracy of the first laser 2 by the mounter. When the second laser 3 is placed on the second installation portion 15 by the mounter, a second identifier 17 is provided in the first installation groove 13 and / or on the optical waveguide structure 12. The mounter can calibrate the second identifier 17 with the origin of its own system to improve the installation accuracy of the second laser 3 by the mounter.

[0086] Based on the chip module in any of the above embodiments, in the second aspect of the embodiments of the present application, a processing method for a chip module is provided. The processing method for the chip module includes:

[0087] As Figure 10 shown in Figure 10 , take the substrate 11, and prepare an optical waveguide structure 12 on the substrate 11. The optical waveguide structure 12 is used to propagate the optical signals emitted by the first laser 2 and the second laser 3;

[0088] As Figure 11 shown in Figure 11 , etch a first installation groove 13 on one side of the optical waveguide structure 12. The etching method can be dry etching or wet etching;

[0089] As Figure 12 shown in Figure 12 , perform a laser direct writing process in the first installation groove 13 to form a first installation portion 14 and a second installation portion 15. Along the thickness direction of the substrate 11, that is, along the height direction of the laser, the height of the first installation portion 14 is greater than or less than the height of the second installation portion 15;

[0090] Use a mounter to mount the first laser 2 on the first installation portion 14 and mount the second laser 3 on the second installation portion 15 to form the chip module as Figure 1 shown in Figure 1 .

[0091] In this embodiment, since the heights of the first mounting portion 14 and the second mounting portion 15 are different, compared with the etching process in the prior art, by using the laser direct writing process to process the first mounting portion 14 and the second mounting portion 15, the first mounting portion 14 and the second mounting portion 15 can be processed and completed simultaneously after one laser direct writing process, thereby reducing the number of preparation processes required to process the first mounting portion 14 and the second mounting portion 15, and further shortening the processing cycle of the first mounting portion 14 and the second mounting portion 15, and improving the processing and production efficiency of the chip module. The first laser 2 is placed on the first mounting portion 14 through a pick-and-place machine, and the second laser 3 is placed on the second mounting portion 15 through a pick-and-place machine, which improves the accuracy of the mounting positions of the first laser 2 and the second laser 3, and further is beneficial to improving the stability and reliability of the optical signal transmission of the first laser 2 and the second laser 3. Further, it is beneficial to improve the stability and reliability of the signal transmission between the chip module and the optical receiver.

[0092] The processing method of the chip module further includes:

[0093] As Figure 12 shown, perform a laser direct writing process in the first mounting groove 13 and / or on the optical waveguide structure 12 to form a first mark 16 and a second mark 17;

[0094] The steps of using a pick-and-place machine to mount the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15 include:

[0095] Calibrate the pick-and-place machine with the first mark 16;

[0096] Place the first laser 2 on the pick-and-place machine, and the pick-and-place machine adheres the first laser 2 to the first mounting portion 14;

[0097] Calibrate the pick-and-place machine with the second mark 17;

[0098] Place the second laser 3 on the pick-and-place machine, and the pick-and-place machine adheres the second laser 3 to the second mounting portion 15.

[0099] In this embodiment, by using the laser direct writing process to process the first mark 16 and the second mark 17, the accuracy of the processing positions of the first mark 16 and the second mark 17 is improved, and further it is beneficial to improve the mounting position accuracy of the first laser 2 and the second laser 3.

[0100] Among them, the steps of processing the first identifier 16 and the second identifier 17 by using the laser direct writing process can be before the steps of processing the first mounting portion 14 and the second mounting portion 15, can also be after the steps of processing the first mounting portion 14 and the second mounting portion 15, or can be carried out simultaneously with the steps of processing the first mounting portion 14 and the second mounting portion 15. When processing the first mounting portion 14, the second mounting portion 15, the first identifier 16 and the second identifier 17 simultaneously, the number of laser direct processes required is reduced, thereby shortening the processing cycle of the chip module, and further improving the processing production efficiency of the chip module.

[0101] In addition, the first identifier 16 and the second identifier 17 can also be processed by using an electroplating process to reduce the processing cost of the first identifier 16 and the second identifier 17.

[0102] Among them, the steps of the mounter attaching the first laser 2 to the first mounting portion 14 include:

[0103] Along the height direction of the first laser 2, the mounter attaches the side of the first laser 2 provided with the first electrode 21 to the first mounting portion 14, so that the first laser 2 is inverted in the first mounting groove 13;

[0104] The steps of the mounter attaching the second laser 3 to the second mounting portion 15 include;

[0105] Along the height direction of the second laser 3, the mounter attaches the side of the second laser 3 provided with the third electrode 31 to the second mounting portion 15, so that the second laser 3 is inverted in the first mounting groove 13.

[0106] In this embodiment, since the vertical distance between the first active layer 222 and the first electrode 21 is less than the vertical distance between the first active layer 222 and the second electrode 24, and the vertical distance between the second active layer 322 and the third electrode 31 is less than the vertical distance between the second active layer 322 and the fourth electrode 34, the first laser 2 and the second laser 3 are inverted in the first mounting groove 13, so that the depth of the first mounting groove 13 required in the height direction of the laser is smaller, thereby reducing the processing difficulty of the first mounting groove 13, and being beneficial to improving the processing accuracy of the first mounting groove 13. At the same time, it is beneficial to shorten the processing time of the first mounting groove 13, thereby shortening the processing cycle of the chip module, and further improving the processing production efficiency of the chip module.

[0107] Before the steps of using the mounter to mount the first laser 2 on the first mounting portion 14 and mount the second laser 3 on the second mounting portion 15, the processing method of the chip module includes:

[0108] As Figure 13 shown, the first electrode layer 18 and the second electrode layer 19 are processed in the first mounting groove 13.

[0109] In this embodiment, processing the first electrode layer 18 and the second electrode layer 19 facilitates the electrical connection between the first laser 2, the second laser 3 and the silicon-based photon platform 1, thereby facilitating the first laser 2 to emit a first optical signal and the second laser 3 to emit a second optical signal, simplifying the electrical connection structure of the first laser 2 and the second laser 3, and thus being beneficial to reducing the overall size of the chip module.

[0110] Among them, in one embodiment, as Figure 13 shown, the steps of processing the first electrode layer 18 and the second electrode layer 19 in the first installation groove 13 are carried out simultaneously with the steps of performing a laser direct writing process in the first installation groove 13 to form the first installation portion 14 and the second installation portion 15;

[0111] The steps of performing a laser direct writing process in the first installation groove 13 to form the first installation portion 14, the second installation portion 15, the first electrode layer 18 and the second electrode layer 19 include:

[0112] Coat a first photoresist in the first installation groove 13. The first photoresist is mixed with conductive particles. The conductive particles can be metal nanoparticles such as silver, aluminum, copper, etc., or can also be nanoparticles of a metal alloy. The metal alloy contains conductive metals such as silver, aluminum, copper, etc.;

[0113] Perform laser direct writing on the first photoresist to locally cure the first photoresist, forming the first installation portion 14, the second installation portion 15, the first electrode layer 18 and the second electrode layer 19;

[0114] Remove the uncured first photoresist.

[0115] In this embodiment, processing the first electrode layer 18, the second electrode layer 19, the first installation portion 14 and the second installation portion 15 simultaneously reduces the number of processes required for processing the first electrode layer 18, the second electrode layer 19, the first installation portion 14 and the second installation portion 15, thereby shortening the processing cycle of the chip module, and further improving the processing production efficiency of the chip module. By processing the first electrode layer 18 and the second electrode layer 19 through a laser direct writing process, the position and dimension accuracy of the first electrode layer 18 and the second electrode layer 19 are improved, which is beneficial to improving the stability and reliability of the electrical connection between the silicon-based photon platform 1 and the laser. Further, it is beneficial to improving the stability and reliability of the signal transmission between the chip module and the optical receiver.

[0116] In another embodiment, as Figure 12 and Figure 13As shown, the steps of processing the first electrode layer 18 and the second electrode layer 19 in the first installation groove 13 are before or after the step of performing a laser direct writing process in the first installation groove 13 to form the first installation portion 14 and the second installation portion 15. For example, as Figure 12 shown, first process the first installation portion 14 and the second installation portion 15 in the first installation groove 13, and then as Figure 13 shown, process the first electrode layer 18 and the second electrode layer 19 in the first installation groove 13; specifically, the step of performing a laser direct writing process in the first installation groove 13 to form the first installation portion 14 and the second installation portion 15 includes:

[0117] Coat a second photoresist in the first installation groove 13;

[0118] Perform laser direct writing on the second photoresist so that the second photoresist is locally cured to form the first installation portion 14 and the second installation portion 15;

[0119] Remove the uncured first photoresist.

[0120] In this embodiment, since the processing steps of the first electrode layer 18 and the second electrode layer 19 are before or after the processing steps of the first installation portion 14 and the second installation portion 15, therefore, it is not necessary to mix conductive metal particles in the second photoresist required for processing the first installation portion 14 and the second installation portion 15, thereby increasing the range of optional materials for the second photoresist, that is, the second photoresist can use other materials compatible with the subsequent packaging process, such as PI-based photoresists or composite materials containing silica fillers, etc., reducing the material cost of processing the first installation portion 14 and the second installation portion 15.

[0121] In one embodiment, the steps of processing the first electrode layer 18 and the second electrode layer 19 in the first installation groove 13 include:

[0122] Sputter a seed layer in the first installation groove 13;

[0123] Electroplate the seed layer to form an electroplated metal layer;

[0124] Cover a third photoresist on the surface of the electroplated metal layer;

[0125] Process a first pattern and a second pattern on the third photoresist, that is, dry, lithograph, and clean the third photoresist to form the first pattern and the second pattern;

[0126] Etch the electroplated metal layer through the first pattern and the second pattern, and the unetched part of the electroplated metal layer forms the first electrode layer 18 and the second electrode layer 19;

[0127] Remove the third photoresist.

[0128] In another embodiment, the steps of processing the first electrode layer 18 and the second electrode layer 19 in the first mounting groove 13 include:

[0129] Cover a third photoresist in the first mounting groove 13;

[0130] Process a first pattern and a second pattern on the third photoresist, that is, dry, lithograph, and clean the third photoresist to form the first pattern and the second pattern;

[0131] Sputter a seed layer within the first pattern, within the second pattern, and on the surface of the third photoresist;

[0132] Electroplate the seed layer to form an electroplated metal layer;

[0133] Grind the electroplated metal layer to remove the electroplated metal layer on the surface of the third photoresist and reduce the thickness of the electroplated metal layer within the first pattern and the second pattern, so as to form the first electrode layer 18 and the second electrode layer 19;

[0134] Remove the third photoresist.

[0135] Processing the first electrode layer 18 and the second electrode layer 19 by electroplating reduces the processing difficulty and cost of the first electrode layer 18 and the second electrode layer 19.

[0136] After the steps of processing the first electrode layer 18 and the second electrode layer 19 in the first mounting groove 13, the processing method of the chip module includes:

[0137] Prepare at least one first conductive bump 181 on the first electrode layer 18 and prepare at least one second conductive bump 191 on the second electrode layer 19, so as to form as Figure 6 or Figure 9 shown, the first electrode layer 18 is electrically connected to the first laser 2 through the first conductive bump 181, and the second electrode layer 19 is electrically connected through the second conductive bump 191.

[0138] In this embodiment, the first electrode layer 18 is electrically connected to the first laser 2 through the first conductive bump 181, and the second electrode layer 19 is electrically connected to the second laser 3 through the second conductive bump 191, so as to reduce the thickness of the first electrode layer 18 and the second electrode layer 19 in the height direction of the laser, thereby reducing the material cost of the first electrode layer 18 and the second electrode layer 19, and facilitating shortening the processing cycle of the first electrode layer 18 and the second electrode layer 19, thereby shortening the processing cycle of the chip module, and further improving the processing production efficiency of the chip module.

[0139] In one embodiment, after the first mounting portion 14, the second mounting portion 15, the first identifier 16, the second identifier 17, the first electrode layer 18, the second electrode layer 19, the first conductive bump 181 and the second conductive bump 191 are processed, the first laser 2 is directly mounted on the first mounting portion 14 and the second laser 3 is mounted on the second mounting portion 15 by using a chip mounter, so as to simplify the processing steps of the chip module, shorten the processing cycle of the chip module, and further improve the processing and production efficiency of the chip module.

[0140] In another embodiment, before the step of mounting the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15 by using a chip mounter, the processing method of the chip module includes:

[0141] As Figure 7 and Figure 8 shown, a second mounting groove 25 is processed on the first laser 2, and a third mounting groove 35 is processed on the second laser 3.

[0142] The step of mounting the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15 by using a chip mounter includes:

[0143] Placing the first laser 2 on the first mounting portion 14 so that the side wall of the first mounting portion 14 abuts against the side wall of the second mounting groove 25, and placing the second laser 3 on the second mounting portion 15 so that the side wall of the second mounting portion 15 abuts against the side wall of the third mounting groove 35.

[0144] In this embodiment, during the process of mounting the first laser 2 and the second laser 3 on the silicon-based photon platform 1, the first mounting groove 13 is used to accommodate at least part of the first mounting portion 14, and the first mounting portion 14 can abut against the side wall of the first mounting groove 13 to improve the accuracy of the mounting position of the first laser 2. The second mounting groove 25 is used to accommodate at least part of the second mounting portion 15, and the second mounting portion 15 can abut against the side wall of the second mounting groove 25 to improve the accuracy of the mounting position of the second laser 3, thereby improving the stability and reliability of the optical signal transmission of the first laser 2 and the second laser 3, and improving the processing yield of the chip module.

[0145] Among them, the processing of the second installation groove 25 can be carried out simultaneously with the processing of the first waveguide layer 221, that is, the second installation groove 25 is processed while processing the first waveguide layer 221 to improve the processing accuracy of the position and size of the second installation groove 25; alternatively, the first waveguide layer 221 can be processed first, and then the second installation groove 25 is processed on the first waveguide layer 221. The processing of the third installation groove 35 can be carried out simultaneously with the processing of the third waveguide layer 321, that is, the third installation groove 35 is processed while processing the third waveguide layer 321 to improve the processing accuracy of the position and size of the third installation groove 35; alternatively, the third waveguide layer 321 can be processed first, and then the third installation groove 35 is processed on the third waveguide layer 321.

[0146] In any of the above embodiments, before the step of preparing the optical waveguide structure 12 on the substrate 11, the processing method of the chip module includes:

[0147] Deposit a barrier layer 110 on the substrate 11;

[0148] Cover a fourth photoresist on the barrier layer 110;

[0149] Use a lithography machine to process a third pattern on the fourth photoresist;

[0150] Etch a part of the barrier layer 110 through the third pattern so that the barrier layer 110 has a preset shape;

[0151] Remove the photoresist.

[0152] In this embodiment, during the process of etching the first installation groove 13, along the thickness direction of the substrate 11, the barrier layer 110 can limit the etching depth of the etching material on the substrate 11, reducing the risk that the laser cannot be aligned with the optical waveguide structure 12 due to too large or too small etching depth, thereby improving the working stability of the chip module.

[0153] Alternatively, in another embodiment, the barrier layer 110 is not provided, and along the thickness direction of the substrate 11, the etching depth of the first installation groove 13 is adjusted by parameters such as etching material, etching temperature, and etching time to simplify the processing steps of the chip module.

[0154] Among them, when the barrier layer 110 is provided, the thickness of the optical waveguide structure 12 is H1, and when the barrier layer 110 is not provided, the thickness of the optical waveguide structure 12 is H2, then H1 > H2 to meet the depth requirement of the etching of the first installation groove 13.

[0155] In any of the above embodiments, the steps of preparing the optical waveguide structure 12 on the substrate 11 are common optical waveguide growth methods in the prior art. For example: growing SiO on the substrate 11 by chemical vapor deposition 2A thin film is used to form the lower cladding 123. Specifically, the low-pressure chemical vapor deposition method or the plasma-enhanced chemical vapor deposition method can be adopted.

[0156] The SiN thin film is grown by chemical vapor deposition. The SiN thin film serves as the waveguide layer 122. Specifically, the low-pressure chemical vapor deposition method or the plasma-enhanced chemical vapor deposition method can be adopted.

[0157] Through processes such as photolithography, dry etching, and photoresist stripping, a waveguide core region structure is fabricated on the surface of the high-refractive-index waveguide layer 122.

[0158] SiO thin film is grown by chemical vapor deposition to form the upper cladding 121. 2

[0159] In any of the above embodiments, the step of processing the first mounting groove 13 on one side of the optical waveguide structure 12 adopts the etching process commonly used in the prior art. For example, a fifth photoresist is coated on the surface of the substrate 11.

[0160] A fourth pattern is processed on the fifth photoresist using a photolithography machine.

[0161] The substrate 11 is dry-etched through the fourth pattern to form the first mounting groove 13 as shown in Figure 11 and Figure 16 .

[0162] In any of the above embodiments, the laser direct writing process can be an extrusion 3D printing process, a stereolithography 3D printing process, or a two-photon 3D printing process. The two-photon 3D printing process can improve the processing accuracy of structures such as the first mounting portion 14, the second mounting portion 15, the first identifier 16, and the second identifier 17.

[0163] In summary, in one embodiment, the processing method of the chip module is as follows:

[0164] Take the substrate 11, as shown in Figure 10 , and fabricate the optical waveguide structure 12 on the substrate 11.

[0165] As shown in Figure 11 , etch the first mounting groove 13 on one side of the optical waveguide structure 12.

[0166] As shown in Figure 13 , simultaneously process the first mounting portion 14, the second mounting portion 15, the first identifier 16, the second identifier 17, the first electrode layer 18, and the second electrode layer 19 using the laser direct writing process.

[0167] Process the first conductive bump 181 on the first electrode layer 18 and process the second conductive bump 191 on the second electrode layer 19.

[0168] Use a chip mounter to fix the first laser 2 on the first mounting portion 14 and fix the second laser 3 on the second mounting portion 15;

[0169] Optionally, before the step of using a chip mounter to fix the first laser 2 on the first mounting portion 14 and fix the second laser 3 on the second mounting portion 15, process a second mounting groove 25 on the first laser 2 and process a third mounting groove 35 on the second laser 3.

[0170] In one embodiment, the processing method of the chip module may also be:

[0171] Take a substrate 11, as Figure 10 shown, prepare an optical waveguide structure 12 on the substrate 11;

[0172] As Figure 11 shown, etch a first mounting groove 13 on one side of the optical waveguide structure 12;

[0173] As Figure 12 shown, use a laser direct writing process to simultaneously process the first mounting portion 14, the second mounting portion 15, the first identifier 16, and the second identifier 17;

[0174] As Figure 13 shown, electroplate a first electrode layer 18 and a second electrode layer 19 in the first mounting groove 13;

[0175] Process a first conductive bump 181 on the first electrode layer 18 and process a second conductive bump 191 on the second electrode layer 19;

[0176] Use a chip mounter to fix the first laser 2 on the first mounting portion 14 and fix the second laser 3 on the second mounting portion 15;

[0177] Optionally, before the step of using a chip mounter to fix the first laser 2 on the first mounting portion 14 and fix the second laser 3 on the second mounting portion 15, process a second mounting groove 25 on the first laser 2 and process a third mounting groove 35 on the second laser 3.

[0178] In one embodiment, the processing method of the chip module may also be:

[0179] Take a substrate 11, as Figure 14 shown, prepare a barrier layer 110 on the substrate 11;

[0180] As Figure 15 shown, prepare an optical waveguide structure 12 on the substrate 11;

[0181] As Figure 16 shown, etch a first mounting groove 13 on one side of the optical waveguide structure 12;

[0182] As shown Figure 17 in FIG. 1, the barrier layer 110 is removed;

[0183] As shown Figure 19 in FIG. 2, the first mounting portion 14, the second mounting portion 15, the first identifier 16, the second identifier 17, the first electrode layer 18, and the second electrode layer 19 are simultaneously processed by laser direct writing technology;

[0184] As shown Figure 20 in FIG. 3, a first conductive bump 181 is processed on the first electrode layer 18, and a second conductive bump 191 is processed on the second electrode layer 19;

[0185] The first laser 2 is fixed on the first mounting portion 14 and the second laser 3 is fixed on the second mounting portion 15 by a chip mounter;

[0186] Optionally, before the step of fixing the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15 by a chip mounter, a second mounting groove 25 is processed on the first laser 2, and a third mounting groove 35 is processed on the second laser 3.

[0187] In another embodiment, the processing method of the chip module may also be:

[0188] Take the substrate 11, as shown Figure 14 in FIG. 4, a barrier layer 110 is prepared on the substrate 11;

[0189] As shown Figure 15 in FIG. 5, an optical waveguide structure 12 is prepared on the substrate 11;

[0190] As shown Figure 16 in FIG. 6, a first mounting groove 13 is etched on one side of the optical waveguide structure 12;

[0191] As shown Figure 17 in FIG. 7, the barrier layer 110 is removed;

[0192] As shown Figure 18 in FIG. 8, the first mounting portion 14, the second mounting portion 15, the first identifier 16, and the second identifier 17 are simultaneously processed by laser direct writing technology;

[0193] As shown Figure 19 in FIG. 9, the first electrode layer 18 and the second electrode layer 19 are electroplated in the first mounting groove 13;

[0194] As shown Figure 20 in FIG. 10, a first conductive bump 181 is processed on the first electrode layer 18, and a second conductive bump 191 is processed on the second electrode layer 19;

[0195] Use a chip mounter to fix the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15;

[0196] Optionally, before the step of using a chip mounter to fix the first laser 2 on the first mounting portion 14 and the second laser 3 on the second mounting portion 15, process a second mounting groove 25 on the first laser 2 and a third mounting groove 35 on the second laser 3.

[0197] For the same or similar parts among the various embodiments in this specification, reference can be made to each other.

Claims

1. A processing method of a chip module, the chip module at least includes a silicon-based photonics platform, a first laser and a second laser, and the silicon-based photonics platform includes a substrate, characterized in that, the processing method of the chip module includes: taking the substrate, and preparing an optical waveguide structure on the substrate, the optical waveguide structure being used for propagating optical signals emitted by the first laser and the second laser; etching a first mounting groove on one side of the optical waveguide structure; performing a laser direct writing process in the first mounting groove to form a first mounting portion and a second mounting portion, along the thickness direction of the substrate, the height of the first mounting portion being greater than or less than the height of the second mounting portion; using a mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion.

2. The processing method of the chip module according to claim 1, characterized in that, before the step of using the mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion, the processing method of the chip module includes: performing a laser direct writing process in the first mounting groove and / or on the optical waveguide structure to form a first identifier and a second identifier; the step of using the mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion includes: calibrating the mounter with the first identifier; placing the first laser on the mounter, and the mounter attaching the first laser to the first mounting portion; calibrating the mounter with the second identifier; placing the second laser on the mounter, and the mounter attaching the second laser to the second mounting portion.

3. The processing method of the chip module according to claim 2, characterized in that, the first laser includes a first electrode, and the second laser includes a third electrode; the step of the mounter attaching the first laser to the first mounting portion includes: along the height direction of the first laser, the mounter attaching the side of the first laser provided with the first electrode to the first mounting portion; the step of the mounter attaching the second laser to the second mounting portion includes: along the height direction of the second laser, the mounter attaching the side of the second laser provided with the third electrode to the second mounting portion.

4. The processing method of the chip module according to claim 1, characterized in that, before the step of using a mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion, the processing method of the chip module includes: processing a first electrode layer and a second electrode layer in the first mounting groove, the first electrode layer being used for electrically connecting with the first laser, and the second electrode layer being used for electrically connecting with the second laser.

5. The processing method of the chip module according to claim 4, characterized in that, The step of processing the first electrode layer and the second electrode layer in the first installation groove is carried out simultaneously with the step of performing a laser direct writing process in the first installation groove to form the first installation portion and the second installation portion; The step of performing a laser direct writing process in the first installation groove to form the first installation portion, the second installation portion, the first electrode layer and the second electrode layer includes: Coating a first photoresist in the first installation groove, and conductive particles are mixed in the first photoresist; Performing laser direct writing on the first photoresist to locally cure the first photoresist, and forming the first installation portion, the second installation portion, the first electrode layer and the second electrode layer; Removing the uncured first photoresist.

6. The processing method of the chip module according to claim 4, wherein, The step of processing the first electrode layer and the second electrode layer in the first installation groove is before or after the step of performing a laser direct writing process in the first installation groove to form the first installation portion and the second installation portion; The step of performing a laser direct writing process in the first installation groove to form the first installation portion and the second installation portion includes: Coating a first photoresist in the first installation groove, and conductive particles are mixed in the first photoresist; Performing laser direct writing on the first photoresist to locally cure the first photoresist, and forming the first installation portion and the second installation portion; Removing the uncured first photoresist; The step of processing the first electrode layer and the second electrode layer in the first installation groove includes: Sputtering a seed layer in the first installation groove; Electroplating the seed layer to form an electroplated metal layer; Covering a third photoresist on the surface of the electroplated metal layer; Processing a first pattern and a second pattern on the third photoresist; Etching the electroplated metal layer through the first pattern and the second pattern to form the first electrode layer and the second electrode layer; Removing the third photoresist; Or, the step of processing the first electrode layer and the second electrode layer in the first installation groove includes: Covering a third photoresist in the first installation groove; Processing a first pattern and a second pattern on the third photoresist; Sputtering a seed layer in the first pattern, the second pattern and on the surface of the third photoresist; Electroplating the seed layer to form an electroplated metal layer; Grinding the electroplated metal layer to remove the electroplated metal layer on the surface of the third photoresist and reducing the thickness of the electroplated metal layer in the first pattern and the second pattern to form the first electrode layer and the second electrode layer; Removing the third photoresist.

7. The processing method of the chip module according to claim 4, wherein, After the step of processing the first electrode layer and the second electrode layer in the first installation groove, the processing method of the chip module includes: At least one first conductive bump is fabricated on the first electrode layer, and at least one second conductive bump is fabricated on the second electrode layer. The first electrode layer is electrically connected to the first laser through the first conductive bump, and the second electrode layer is electrically connected through the second conductive bump.

8. The processing method of the chip module according to any one of claims 1 to 7, wherein, before the step of using a mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion, the processing method of the chip module includes: processing a second mounting groove on the first laser and processing a third mounting groove on the second laser; the step of using a mounter to mount the first laser on the first mounting portion and mount the second laser on the second mounting portion includes: placing the first laser on the first mounting portion so that the side wall of the first mounting portion abuts against the side wall of the second mounting groove, and placing the second laser on the second mounting portion so that the side wall of the second mounting portion abuts against the side wall of the third mounting groove.

9. The processing method of the chip module according to any one of claims 1 to 7, wherein, before the step of fabricating the optical waveguide structure on the substrate, the processing method of the chip module includes: depositing a barrier layer on the substrate; covering a fourth photoresist on the barrier layer; using a lithography machine to process a third pattern on the fourth photoresist; etching a part of the barrier layer through the third pattern so that the barrier layer has a preset shape; removing the photoresist.

10. A chip module, wherein, the chip module is made by the processing method of the chip module according to any one of claims 1 to 9.

11. An optical communication system, wherein, the optical communication system includes: the chip module according to claim 10; a photoreceiver, the photoreceiver is electrically connected or signal-connected to the chip module, and the photoreceiver is used for receiving the light emitted by the first laser and / or the second laser.

Images