An optoelectronic chip packaging structure

Abstract

The present invention relates to the field of semiconductor technology, and particularly relates to an optoelectronic chip packaging structure, comprising: a substrate, on the upper surface of which a signal transmission layer is provided, and on the signal transmission layer a signal processing layer is provided; the signal transmission layer includes: a first electrical chip, which has a first surface and a second surface, and the first surface faces the substrate, and the second surface faces the signal processing layer; the signal processing layer includes: a signal conversion area and a data storage area; a photonic chip is correspondingly arranged in the signal conversion area, and the photonic chip includes: N*M photon computing units, and each photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer; a second electrical chip is correspondingly arranged in the data storage area, which is used for receiving and storing calculation data. The present invention solves the problems of high preparation difficulty and poor heat dissipation performance of the existing packaging structure.

Description

[0001] Divisional Application

[0002] This application is a divisional application of a Chinese patent application with the application number CN2024109616281, the application date of July 18, 2024, and the invention title "An optoelectronic chip packaging structure". Technical Field

[0003] The present invention relates to the technical field of chip packaging, and specifically relates to an optoelectronic chip packaging structure. Background Art

[0004] Currently, there are usually two solutions for integrated circuit packaging:

[0005] I. A photonic chip (also known as: optical chip) is disposed above an electronic chip (also known as: electrical chip)

[0006] For example, patent application CN115706058A discloses a semiconductor packaging device and a manufacturing method thereof. Among them, the photonic chip in the semiconductor packaging device is disposed on the upper surface of the electronic chip through structures such as a first interconnect structure, an optical device, and a redistribution structure, so that the photonic chip and the electronic chip achieve a better alignment and light coupling effect.

[0007] Again, for example, patent application CN115706108A discloses a semiconductor packaging structure and a manufacturing method thereof. In the semiconductor packaging structure, two electronic chips are arranged in parallel to jointly carry a photonic chip on its upper surface.

[0008] II. The electronic chip is disposed above the photonic chip

[0009] For example, patent application CN114063229A discloses a semiconductor device. The semiconductor device includes: a PIC chip (i.e., an optical chip), which includes a conductive structure in a hole; a first electronic integrated circuit chip, i.e., a first EIC chip (i.e., an electrical chip), the first EIC chip is disposed on a first surface of the PIC chip; a second electronic integrated circuit chip, i.e., a second EIC chip, the second EIC chip is disposed on a second surface of the PIC chip. However, this solution of disposing the optical chip under the electrical chip requires the setting of through-silicon vias (TSV) on the optical chip. And the processing technology of opening through-silicon vias on the optical chip is very difficult and the cost is also very high.

[0010] However, with the continuous development of big data, artificial intelligence, telemedicine, Internet of Things, e-commerce, and 5G communication, the global data traffic has increased explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging. However, when dealing with high-density circuit integration, the above traditional packaging solutions have certain defects in terms of processing difficulty and working stability. Summary of the Invention

[0011] The object of the present invention is to provide an optoelectronic chip packaging structure (or a 3D packaging structure of an optoelectronic chip), which can partially solve or alleviate the above deficiencies in the prior art, simplify the packaging structure of the optoelectronic chip (and thus simplify the processing technology), and improve the working stability of the optoelectronic chip.

[0012] To solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0013] In a first aspect of the present invention, there is provided an optoelectronic chip packaging structure, comprising:

[0014] A substrate, on the upper surface of which a signal transmission layer is provided, and on which a signal processing layer is provided;

[0015] The signal transmission layer includes: at least one first electrical chip, which has a first surface and a second surface, and the first surface faces the substrate, and the second surface faces the signal processing layer;

[0016] The signal processing layer includes: a signal conversion area and a data storage area;

[0017] At least one optical chip is correspondingly provided in the signal conversion area. The optical chip includes: N*M photon computing units, and each photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer;

[0018] The optical chip is used to receive the modulation signal input by the first electrical chip. At least one group of the photon computing units modulates the corresponding phase change material layer into a specific state in response to the modulation signal, and the photon computing unit completes the corresponding computing task in the specific state and outputs the corresponding computing data;

[0019] At least one second electrical chip is correspondingly provided in the data storage area, and the second electrical chip is used to receive and store the computing data; wherein, the electrical connection path from the signal processing layer to the signal transmission layer includes a first bonding structure, a first redistribution layer, a through-silicon via, and a second redistribution layer that are passed through in sequence.

[0020] In some embodiments, the size of at least one of the second electrical chips is smaller than the size of the signal transmission layer, and the size of the signal transmission layer is the total size of the at least one first electrical chip.

[0021] In some embodiments, at least two high-bandwidth memory chips are disposed on the second surface of the first electrical chip, and the at least two high-bandwidth memory chips are respectively disposed on both sides of the optical chip;

[0022] The first electrical chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit for communicating with the high-bandwidth memory chip; wherein,

[0023] The XDAC control circuit is configured to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is configured to receive the output signal of the photodetector in the photon computing unit, and the WDAC control signal is configured to provide a calculation input signal to the modulated photon computing unit, and the photon computing unit completes the calculation in response to the calculation input signal and outputs the calculation data.

[0024] In some embodiments, the signal processing layer further includes: a data conversion area communicatively connected to the data storage area, and at least one second electrical chip is correspondingly disposed in the data conversion area, and the corresponding second electrical chip receives the corresponding calculation data through the first electrical chip, so as to convert the calculation data into a specific format according to a set data conversion rule, and input the calculation data converted into the specific format into the second electrical chip located in the data storage area.

[0025] In some embodiments, it further includes: at least one task allocation unit, and the at least one task allocation unit is connected to the corresponding functional partition, and a plurality of the second electrical chips are arranged in the functional partition; the functional partition includes: a data storage area and / or a data conversion area; correspondingly, the task allocation unit is configured to perform the following steps:

[0026] When at least one of the second electrical chips receives the corresponding calculation data, monitor the power consumption data of the second electrical chip in the first time period;

[0027] When the power consumption data is greater than a first set threshold and less than or equal to a second set threshold, the first allocation rule is used to perform allocation processing on the current calculation data; wherein, the first allocation rule requires suspending the transmission of new calculation data to the current second electrical chip within the second time period, and selecting a second electrical chip whose distance from the current second electrical chip is greater than a first distance to receive the subsequent new calculation data to be processed;

[0028] When the power consumption data is greater than the second set threshold and less than or equal to the third set threshold, the second allocation rule is used to allocate the calculation data; wherein, the second allocation rule requires suspending the transmission of the new calculation data to the current second electrical chip during the second time period, and selecting a second electrical chip whose distance from the current second electrical chip is greater than the second distance to receive the subsequent new calculation data to be processed, and the second distance is greater than the first distance;

[0029] When the power consumption data is greater than the third set threshold, the third allocation rule is used to allocate the calculation data; wherein, the third allocation rule requires suspending the processing of the current calculation data by the current second electrical chip, and reallocating the current calculation data to at least one second electrical chip whose distance from the current second electrical chip is greater than the second distance.

[0030] In some embodiments, at least one of the second electrical chips is a field programmable gate array chip.

[0031] In some embodiments, the first electrical chip is an application specific integrated circuit chip.

[0032] In some embodiments, a heat sink is disposed on the signal processing layer, and the lower surface of the heat sink covers at least one of the optical chips and at least one of the second electrical chips.

[0033] In some embodiments, a system integration board is further disposed on the lower surface of the substrate through a second bonding structure.

[0034] In some embodiments, the lower surface of the heat sink, the upper surface of the system integration board, and the same-side end faces of the optical chip, the first electrical chip, and the substrate sequentially disposed between the heat sink and the system integration board together enclose a receiving space for arranging an optical fiber array, and a groove is disposed on the lower surface of the heat sink corresponding to the receiving space; wherein, the optical fiber array includes: a first substrate and a second substrate connected to each other;

[0035] Wherein, the first substrate is disposed at the groove through a first glue, and the second substrate is connected to the side surface of the optical chip through a second glue with a refractive index match; a V-shaped groove is disposed on the second substrate for accommodating an optical fiber and enabling the optical fiber to be optically coupled with the photosensitive area at the side surface.

[0036] Beneficial technical effects:

[0037] In order to simplify the packaging structure (simplify the process and reduce the cost), and at the same time improve the working stability of the packaging structure during actual application, the present invention proposes a multi-chip combined packaging scheme.

[0038] First, in terms of structure, the present invention adopts a structure in which a large-sized chip carries multiple small-sized chips (such as a "one-carries-many" packaging solution). This design with a small upper part and a large lower part is relatively simple in the packaging structure and is convenient for processing. Moreover, in order to reasonably distribute the overall computing power consumption, the present invention sets the large chip below as an optical chip for signal input and transmission, and sets at least one chip above as an optical chip made of phase change material, and the optical chip is used to complete the main computing tasks. Further, the remaining chips are set as electrical chips to convert and store the computing results output by the optical chips.

[0039] Looking at it from another perspective, the present invention optimally distributes the functions between and within the layers of the packaging structure. The inner layer is set as the signal transmission layer, and the outer layer is set as the signal processing layer. Different functional areas are sequentially divided within the signal processing layer, such as signal conversion, data conversion, and data storage areas.

[0040] In summary, this coordinated distribution in terms of position and function can simplify the packaging structure on the one hand, and ensure that the overall power consumption of the packaging structure is reasonably distributed during operation on the other hand, reduce its operation pressure when performing large data calculations such as artificial intelligence, and improve its working stability and the reliability of the calculation results.

[0041] Furthermore, for this packaging structure (or rather, the distributed chip setting structure) with optimized position and function, the present invention also provides a multi-level task allocation rule to coordinate and maintain the power consumption and working stability of this distributed chip setting structure. It can reduce the power consumption generated by the distributed computing form to a certain extent (such as reasonably calling local chips to complete the current calculation), and at the same time, quickly and reasonably allocate tasks in combination with different power consumption situations, ensuring that the overall structure's heat dissipation problem is reasonably optimized while maintaining the effective progress of the computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale. Obviously, the following-described drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic diagram of the overall structure of an exemplary optoelectronic chip packaging structure in the present invention;

[0044] Figure 2aSchematic diagram of the optoelectronic chip packaging structure in a specific embodiment;

[0045] Figure 2b Schematic diagram of the optoelectronic chip packaging structure in another specific embodiment;

[0046] Figure 2c Schematic diagram of the optoelectronic chip packaging structure in yet another specific embodiment;

[0047] Figure 3 Schematic diagram of the optical chip in an exemplary embodiment of the present invention.

[0048] Summary of the identification of reference numerals:

[0049] 1 is a substrate, 2 is a first electrical chip (also known as: first electronic chip), 21 is a first surface, 22 is a second surface, 201 is a WDAC control circuit, 202 is an XDAC control circuit, 203 is an XADC control circuit, 13 is an HBM chip; 3 is an optical chip (also known as: photonic chip), 301 is an optical waveguide layer, 302 is a modulation layer (also known as: phase change material layer), 303 is a first stop layer, 304 is a first oxide layer, 305 is a second stop layer, 306 is a second oxide layer; 4 is a second electrical chip (also known as: second electronic chip), 5 is a first bonding structure, 6 is a first redistribution layer, 7 is a through-silicon via, 8 is a second redistribution layer, 9 is a second bonding structure, 10 is a system integration board, 11 is an optical fiber array, 111 is a first substrate, 112 is a second substrate, 113 is an optical fiber, 114 is a first glue, 115 is a second glue, 12 is a heat dissipation layer. Detailed implementation manners

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] In this article, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of describing the present invention and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0052] In this document, the orientation or positional relationships indicated by terms such as "upper", "lower", "inner", "outer", "front", "rear", "one end", "the other end", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0053] In this document, unless otherwise clearly specified and defined, terms such as "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0055] In this document, "a plurality of" means two or more, that is, it includes two, three, four, five, etc.

[0056] It should be noted that in this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of another identical element in the process, method, article or device comprising that element.

[0057] As used in this specification, the term "about" typically represents + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0058] In this specification, certain embodiments may be disclosed in a format that is within a certain range. It should be understood that this description of "within a certain range" is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and individual numerical values within that range. For example, the description of the range 1-6 should be regarded as having specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as the individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0059] In this text, "Through Silicon Via" (abbreviated as TSV in English, also known as via silicon through) is a vertical interconnection that penetrates a silicon wafer or chip. TSV is an interconnection technology that enables 3D IC packaging to follow Moore's Law. TSV can stack multiple chips. Its design concept comes from printed circuit boards (PCBs). Small holes are drilled in the chip (the process can be divided into two types: drilling first and drilling later, Via First, Via Last), and metal is filled from the bottom. Holes (vias) are drilled in the silicon wafer by etching or laser, and then filled with conductive materials such as copper, polysilicon, tungsten, etc.

[0060] In this text, "RDL (ReDistribution Layer)" is also known as the redistribution layer or the rewiring layer. RDL refers to an additional metal layer on the chip that can reposition the electrodes or input / output pads (I / O pads) of the chip to other locations on the chip to facilitate connection with other integrated circuits or chips, or to connect the electrodes or I / O pads of different chips together.

[0061] In this text, HBM refers to high-bandwidth memory chips, and FPGA (Field Programmable Gate Array) refers to field-programmable gate arrays.

[0062] In this text, the modulation layer refers to any entity that affects the properties of light. Among them, the properties of light include transmission, refraction, absorption, etc.

[0063] See Figure 1 As shown, the present invention provides a novel optoelectronic chip packaging structure, and the packaging structure includes:

[0064] A first electrical chip 2, the first electrical chip 2 having a first surface 21 and a second surface 22; a second redistribution layer 8 is disposed on the first surface 21, and a second bonding structure 9 is disposed on the second redistribution layer 8 so that the first surface is connected to the substrate 1; a first redistribution layer 6 is disposed on the second surface 22, and a first bonding structure 5 is disposed on the first redistribution layer 6;

[0065] At least one optical chip 3 and at least one second electrical chip 4, the lower surfaces of the optical chip 3 and the second electrical chip 4 are disposed on the second surface 22 through the first bonding structure 5; heat dissipation layers 12 are disposed on the upper surfaces of the optical chip 3 and the second electrical chip 4; wherein, a plurality of through-silicon vias 7 are disposed in the first electrical chip 2 for connecting circuits between the first electrical chip 2 and the optical chip 3 and the second electrical chip 4;

[0066] At least two high-bandwidth memory chips are disposed on the second surface 22 of the first electrical chip 2, and at least two high-bandwidth memory chips are respectively disposed on both sides of the optical chip 3; the first electrical chip 2 includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit for communicating with the high-bandwidth memory chips.

[0067] To further illustrate the technical effects produced by the above packaging structure, the working mode thereof will be exemplarily described below in combination with the functional partition settings that the packaging structure can achieve. Refer to Figure 1 As shown, an optoelectronic chip packaging structure (i.e., a semiconductor device) includes:

[0068] A substrate 1, a signal transmission layer is disposed on the upper surface of the substrate, and a signal processing layer is disposed on the signal transmission layer;

[0069] For example, in some embodiments, the signal transmission layer can be used to receive external signals (for example, receive computing tasks input to the semiconductor device) and transmit the external signals to the signal processing layer. Preferably, the signal transmission layer can also be used to assist in realizing data transmission and communication between different regions (or chips) in the signal processing layer.

[0070] The signal transmission layer includes: at least one first electrical chip 2, the first electrical chip 2 having a first surface and a second surface, and the first surface faces the substrate 1, and the second surface faces the signal processing layer;

[0071] The signal processing layer includes: a signal conversion area and a data storage area; wherein, the signal conversion area is used to process computing tasks and provide corresponding computing results; data storage is used to store the computing results;

[0072] At least one optical chip 3 is correspondingly arranged in the signal conversion area. The optical chip 3 includes: N*M photon computing units, and each photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, where the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer;

[0073] The optical chip 3 is configured to receive the modulation signal input by the first electrical chip 2. At least one group of the photon computing units modulates the corresponding phase change material layer into a specific state in response to the modulation signal, and the photon computing units complete the corresponding computing tasks in the specific state and output the corresponding computing data;

[0074] At least one second electrical chip 4 is correspondingly arranged in the data storage area. The second electrical chip 4 is configured to receive and store the computing data; wherein, the electrical connection path from the signal processing layer to the signal transmission layer successively passes through a first bonding structure 5, a first redistribution layer 6, a through-silicon via 7, and a second redistribution layer 8.

[0075] It should be noted that, in order to simplify the packaging structure (simplify the process and reduce the cost), and at the same time improve the working stability of the packaging structure in the actual application process, the present invention proposes a multi-chip combined packaging scheme.

[0076] First, in terms of structure, the present invention adopts a structure in which a large-sized chip carries multiple small-sized chips. This design scheme with a small upper part and a large lower part is relatively simple in the packaging structure and convenient for processing. Moreover, in order to reasonably distribute the overall computing power consumption, the present invention sets the large chip below to be an optical chip for signal input and transmission, sets at least one chip above to be an optical chip made of phase change material, and sets the remaining chips to be electrical chips for converting and storing the computing results output by the optical chip.

[0077] In summary, such a collaborative distribution in terms of position and function can simplify the packaging structure on the one hand, and ensure a reasonable distribution of the overall power consumption of the packaging structure during operation on the other hand, reduce its operation pressure when running big data calculations such as artificial intelligence, and improve its working stability.

[0078] In some embodiments, the size of at least one of the second electrical chips 4 is smaller than the size of the signal transmission layer, and the size of the signal transmission layer is the total size of the at least one first electrical chip 2.

[0079] For example, in some embodiments, a first electrical chip 2 is provided in the signal transmission layer, an optical chip 3 is provided on the first electrical chip 2, and a plurality of second electrical chips 4 are provided adjacent to the optical chip 3. Among them, the size of the first electrical chip 2 is larger than that of the optical chip and the second electrical chips. In this embodiment, it is preferably to complete the cooperative installation of the optoelectronic chips by distributing a plurality of small-sized optical chips and electrical chips on a large-sized electrical chip (or, a design scheme of one carrying multiple).

[0080] In some embodiments, at least two high-bandwidth memory chips are provided on the second surface of the first electrical chip 2, and the at least two high-bandwidth memory chips are respectively provided on both sides of the optical chip;

[0081] The first electrical chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit 201, and a communication control circuit communicating with the high-bandwidth memory chips; among them,

[0082] The XDAC control circuit is used to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is used to receive the output signal of the photodetector in the photon computing unit, and the WDAC control signal is used to provide a calculation input signal to the modulated photon computing unit, and the photon computing unit completes the calculation in response to the calculation input signal and outputs the calculation data.

[0083] In some embodiments, the signal processing layer in the semiconductor device further includes: a data conversion area communicatively connected to the data storage area, and at least one second electrical chip is correspondingly provided in the data conversion area, and the corresponding second electrical chip receives the corresponding calculation data through the first electrical chip, so as to convert the calculation data into a specific format according to the set data conversion rule, and input the calculation data converted into a specific format into the second electrical chip located in the data storage area.

[0084] For example, in some embodiments, according to the different signal interfaces connected to the semiconductor device, it is necessary to convert the format of the calculation data into a format type matching the signal interface. Therefore, different types of electrical chips can be adaptively selected to complete the conversion of the signal (i.e., the calculation data) format. That is to say, the conversion rule is determined by the signal interface type in the actual application process.

[0085] For example, in some embodiments, the signal transmission layer (i.e., the first electrical chip 2) is also used to complete the signal transmission between the data conversion area and the data storage area.

[0086] It should be noted that in the existing package structure design, in order to simplify the structure and processing technology, usually only a limited number of electrical chips and optical chips are stacked, and the computing tasks are concentratedly completed on a single chip.

[0087] Conversely, the present invention proposes a cooperative packaging of multiple electrical chips and at least one optical chip. For this new packaging structure, the present invention also correspondingly proposes a distributed functional partition design to disassemble and allocate centralized computing tasks to different functional intervals of the packaging structure to complete, so as to ensure the reliability and accuracy of the calculation results while efficiently completing the computing tasks. Further, for this distributed functional design, the present invention also provides a task allocation scheme. For example, in some embodiments, the packaging structure further includes:

[0088] At least one task allocation unit; and the task allocation unit is connected to at least one functional partition; the functional partition refers to one or more of a signal transmission layer, a signal conversion area, a data storage area, and a data conversion area;

[0089] Taking the second electrical chip as an example, the working process of the task allocation unit is described as follows:

[0090] A plurality of second electrical chips 4 are provided in the corresponding functional partition; the second electrical chip is used to receive the data transmitted by the previous chip and perform corresponding processing on it (for example, for the second electrical chip 4 located in the data conversion area, its previous chip refers to the first electrical chip 2 connected to it);

[0091] Monitor the power consumption data of at least one of the second electrical chips in the first time period (which can be set by the user himself); wherein, the power consumption data can be the amount of data transmitted by the current second electrical chip (abbreviated as the current second electrical chip / current chip in this embodiment) in the first time period; or the power consumption data can be the intensity value of the signal transmitted by the current chip in the first time period;

[0092] When the power consumption data is greater than the first set threshold and less than or equal to the second set threshold, the first allocation rule is adopted for processing; wherein, the first allocation rule requires suspending the transmission of new calculation data to the current second electrical chip in the second time period, and selecting a second electrical chip with a distance greater than the first distance from the current second electrical chip to receive the new calculation data to be processed subsequently;

[0093] When the power consumption data is greater than the second set threshold and less than or equal to the third set threshold, the second allocation rule is adopted for processing; wherein, the second allocation rule requires suspending the transmission of new data to the second electrical chip in the second time period, and selecting a second electrical chip with a distance greater than the second distance from the current second electrical chip to receive the new data to be processed subsequently;

[0094] When the power consumption data is greater than a third set threshold, a third allocation rule is adopted for processing; wherein, the third allocation rule requires suspending the computing tasks of the second electric chip, and reallocating the current computing tasks to at least one second electric chip whose distance from the second electric chip is greater than a second distance; meanwhile, a second electric chip whose distance from the current second electric chip is greater than the second distance is selected to receive new data to be processed subsequently.

[0095] For example, in some embodiments, a first electric chip 2 is provided on the signal processing layer. A data conversion area is arranged above the first electric chip 2, and a plurality of second electric chips (i.e., electric chip I) are arranged in the data conversion area, which are used to convert the data format of the calculation result to meet the output conditions of the corresponding interface. The data conversion area is also connected to a data storage area, and a plurality of second electric chips (i.e., electric chip II) are arranged in the data storage area.

[0096] Among them, when the optoelectronic chip is working, the calculation result output by the optical chip will be transmitted to the electric chip I via the first electric chip 2. After the electric chip I performs format conversion on it, the converted data will be transmitted to the electric chip II for storage.

[0097] Among them, when the amount of calculation data is relatively limited, one (or several) of the electric chips I can be preferentially enabled for data format conversion. As the calculation process progresses, the electric chip I may cause abnormal power consumption due to reasons such as excessive computing tasks (or accidental failures). At this time, in this embodiment, different task allocation schemes are preferably selected according to the abnormal power consumption situation (such as the size of the power consumption data) to maintain the effective progress of the computing tasks.

[0098] In other words, the multi-level task allocation rule adopted by the present invention can coordinate and maintain the power consumption and working stability of this distributed chip setting structure, which can reduce the power consumption generated by the distributed computing form to a certain extent (such as reasonably calling local chips to complete the current calculation), and at the same time, quickly and reasonably allocate tasks in combination with different power consumption situations, while maintaining the effective progress of the computing tasks, ensuring that the heat dissipation problem of the overall structure is reasonably optimized.

[0099] It can be understood that the specific type of electric chip in this embodiment can be adaptively selected according to the function design, and the present invention makes no limitation.

[0100] In some embodiments, the task allocation unit can be implemented by an electric chip or other chips.

[0101] In some embodiments, at least one of the second electric chips 4 is a field programmable gate array chip.

[0102] In some embodiments, the second electrical chip may include one or more chips such as a chip that generates high-speed signals like Serdes, a data storage chip such as HBM for data from the outside and calculation results, a signal conversion and processing chip, and other customized ASIC chips.

[0103] In some embodiments, the first electrical chip 2 is an application-specific integrated circuit chip.

[0104] Figure 2a 、 Figure 2b respectively show a schematic diagram of a packaging structure of an exemplary optoelectronic chip.

[0105] See Figure 2a As shown, the optoelectronic chip packaging structure may include: a first electrical chip 2, a photonic chip 3 and a second electrical chip 4 are respectively disposed on the second surface of the first electrical chip 2; a plurality of HBM chips 13 are respectively disposed on both sides of the photonic chip 3 and the second electrical chip 4.

[0106] See Figure 2b As shown, the optoelectronic chip packaging structure may further include: a first electrical chip, a photonic chip 3 and a second electrical chip 4 are respectively disposed on the second surface of the first electrical chip; an XDAC control circuit 202 and an XADC control circuit 203 are respectively disposed on the first electrical chip, and one or more HBM chips 13 are respectively disposed on both sides of the second electrical chip 4.

[0107] In some embodiments, a heat sink 12 is disposed on the signal processing layer, and the lower surface of the heat sink 12 covers at least one of the photonic chip 3 and the at least one second electrical chip 4.

[0108] In some embodiments, a system integration board 10 is further disposed on the lower surface of the substrate through a second bonding structure 9.

[0109] For example, in some embodiments, the first and second bonding structures may be conductive bumps.

[0110] For example, in some embodiments, the first and second redistribution layers are wiring layers (Redistribution Layer, RDL).

[0111] In some embodiments, the lower surface of the heat sink 12, the upper surface of the system integration board 10, and the same-side end faces of the photonic chip 3, the first electrical chip 2, and the substrate 1 sequentially disposed between the heat sink 12 and the system integration board 10 together enclose a receiving space for arranging an optical fiber array, and a groove is disposed on the lower surface of the heat sink corresponding to the receiving space; wherein, the optical fiber array 11 includes: a first substrate 111 and a second substrate 112 connected to each other;

[0112] Among them, the first substrate 111 is disposed at the groove through the first glue 114, and the second substrate 112 is connected to the side surface of the optical chip 3 through the second glue 115 with a refractive index matching; a V-shaped groove is provided on the second substrate 112 for accommodating the optical fiber 113 and enabling optical coupling between the optical fiber 113 and the photosensitive region at the side surface.

[0113] Among them, the optical output interface in the optical fiber array corresponds to the optical port in the photosensitive end face to achieve end face optical coupling between the optical fiber array and the optical chip.

[0114] In some embodiments, the second bonding structure is a solder ball.

[0115] In some embodiments, the optical modulation layer includes a phase change material layer made of a phase change material, or may be made of a phase change material.

[0116] Preferably, in some embodiments, the optical waveguide structure includes: a silicon oxide substrate, an optical waveguide layer 301, and a phase change material layer 302 located on the optical waveguide layer 301. A first stop layer 303 (i.e., a first isolation layer) is provided between the optical waveguide layer 301 and the phase change material layer 302 (i.e., the modulation layer), and a first oxide layer 304 (i.e., a first protective layer) covers the phase change material layer 302.

[0117] See Figure 3 , on the substrate, a second stop layer 305 is provided around the first stop layer 303 and a first region on the phase change material layer 302 close to the first stop layer 303 (i.e., a partial sidewall region around the bottom where the phase change material layer 302 contacts the first stop layer 303). The first thickness of the second stop layer 305 is greater than the fourth thickness of the first stop layer 303 but less than the sum of the thicknesses of the phase change material layer 302 and the first isolation layer, so that the first stop layer and the second stop layer enclose a first region of the phase change material layer close to the optical waveguide layer side to form a wrapping layer that wraps upward (i.e., the peripheral edge of the wrapping component extends upward along the height direction of the peripheral sidewall of the wrapped component to form an enclosed sidewall); and a second oxide layer 306 is provided around the first oxide layer 304, the phase change material layer 302, a second region on the phase change material layer 302 close to the first oxide layer 304 (i.e., a partial sidewall region around the top where the phase change material layer 302 contacts the first oxide layer 304), the second stop layer 305, and the optical waveguide layer 301. Thus, the first oxide layer and the second oxide layer corresponding to the above second region enclose a second region of the phase change material layer far from the optical waveguide layer side to form a wrapping layer that wraps downward (i.e., the peripheral edge of the wrapping component extends downward along the height direction of the peripheral sidewall of the wrapped component to form an enclosed sidewall), that is, the above phase change material layer is wrapped in a sealed cavity formed by enclosing the first oxide layer 05, the second oxide layer, the first stop layer, and the second stop layer.

[0118] Preferably, the optical chip in the present invention can be fabricated from an optical waveguide in the patent application with the publication number CN117706811A.

[0119] It should be noted that the optical chip made of the phase change material in the present invention works in cooperation with the first electrical chip 2 and multiple second electrical chips 4. Among them, the non-volatile characteristic of the phase change material layer is beneficial to reducing the input signal pressure of the first electrical chip 2. For example, in a single calculation process, the first electrical chip 2 can input signals only once (or a limited number of times), and the optical chip can still complete the corresponding calculation work normally.

[0120] In this embodiment, a large-sized electrical chip can complete the input of external signals in the entire calculation process with limited power consumption. It can not only reduce its own high demand for heat dissipation (even if it is set in the middle layer, it will not cause malfunctions due to poor heat dissipation), but also avoid interfering with the multiple small-sized chips carried thereon.

[0121] Moreover, through test verification, the working stability and accuracy of the package structure obtained by this coordinated design of functions and positions have been significantly improved.

[0122] It should be noted that Figures 1 - 2c The cooperation relationship among the first electrical chip, the second electrical chip, and the optical chip shown can be one unit module of the package structure. For example, multiple first electrical chips can also be correspondingly provided in the package structure, and each of the multiple first electrical chips can carry and set the corresponding optical chip and second electrical chip.

[0123] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0124] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0125] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims. All of these fall within the protection scope of the present invention.

Claims

1. An optoelectronic chip packaging structure, characterized in that, Including: A substrate (1), on the upper surface of which a signal transmission layer is provided, and on which a signal processing layer is provided; The signal transmission layer includes: at least one first electrical chip (2), the first electrical chip (2) having a first surface and a second surface, and the first surface facing the substrate (1) and the second surface facing the signal processing layer; The signal processing layer includes: a signal conversion area and a data storage area; At least one optical chip (3) is correspondingly provided in the signal conversion area, the optical chip (3) including: N*M photon computing units, each photon computing unit including: an optical waveguide layer (301), and a modulation layer (302) located on the optical waveguide layer, the modulation layer being a phase change material layer or the modulation layer including a phase change material layer; The optical chip (3) is configured to receive the modulation signal input by the first electrical chip (2), at least one group of the photon computing units modulating the corresponding phase change material layer into a specific state in response to the modulation signal, and the photon computing units completing the corresponding computing tasks in the specific state and outputting corresponding computing data; At least one second electrical chip (4) is correspondingly provided in the data storage area, the second electrical chip (4) being configured to receive and store the computing data; wherein, the electrical connection path from the signal processing layer to the signal transmission layer includes a first bonding structure (5), a first redistribution layer (6), a through-silicon via (7), and a second redistribution layer (8) that are successively passed through; At least one task allocation unit, and at least one of the task allocation units is connected to a corresponding functional partition, and a plurality of the second electrical chips are arranged in the functional partition; the functional partition includes: a data storage area and / or a data conversion area; the task allocation unit is configured to perform the following steps: When at least one of the second electrical chips receives the corresponding computing data, monitoring the power consumption data of the second electrical chip in a first time period; When the power consumption data is greater than a first set threshold and less than or equal to a second set threshold, then a first allocation rule is used to perform allocation processing on the current computing data; wherein, the first allocation rule requires suspending the transmission of new computing data to the current second electrical chip in a second time period, and selecting a second electrical chip whose distance from the current second electrical chip is greater than a first distance to receive the subsequent new computing data to be processed; When the power consumption data is greater than the second set threshold and less than or equal to a third set threshold, then a second allocation rule is used to allocate the computing data; wherein, the second allocation rule requires suspending the transmission of the new computing data to the current second electrical chip in the second time period, and selecting a second electrical chip whose distance from the current second electrical chip is greater than a second distance to receive the subsequent new computing data to be processed, and the second distance is greater than the first distance; When the power consumption data is greater than the third set threshold, the third allocation rule is adopted to allocate the computing data; wherein, the third allocation rule requires suspending the processing of the current computing data by the current second electronic chip, and reallocating the current computing data to at least one of the second electronic chips whose distance from the current second electronic chip is greater than the second distance.

2. The optoelectronic chip packaging structure according to claim 1, wherein, A heat sink (12) is provided on the signal processing layer, and the lower surface of the heat sink (12) covers at least one of the optical chips (3) and the at least one second electronic chip (4).

3. The optoelectronic chip packaging structure according to claim 2, characterized in that, At least two high-bandwidth memory chips are provided on the second surface of the first electronic chip (2), and the at least two high-bandwidth memory chips are respectively arranged on both sides of the optical chip; The first electronic chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit for communicating with the high-bandwidth memory chip; wherein, The XDAC control circuit is used to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is used to receive the output signal of the photodetector in the photon computing unit, and the WDAC control circuit is used to provide a computing input signal to the modulated photon computing unit, and the photon computing unit completes the computation in response to the computing input signal and outputs the computing data.

4. The optoelectronic chip packaging structure according to claim 2, wherein, The signal processing layer further includes: a data conversion area communicatively connected to the data storage area, and at least one second electronic chip is correspondingly provided in the data conversion area, and the corresponding second electronic chip receives the corresponding computing data through the first electronic chip, and converts the computing data into a specific format according to a set data conversion rule, and inputs the computing data converted into the specific format into the second electronic chip located in the data storage area.

5. The optoelectronic chip packaging structure according to claim 2, characterized in that, At least one of the second electronic chips (4) is a field programmable gate array chip.

6. The optoelectronic chip packaging structure according to claim 2, wherein, The first electronic chip (2) is an application specific integrated circuit chip.

7. The optoelectronic chip packaging structure according to claim 2, wherein, The first bonding structure is a conductive bump.

8. The optoelectronic chip packaging structure according to claim 2, characterized in that, A second bonding structure (9) is provided on the second redistribution layer (8) to connect the first surface to the substrate (1), and the second bonding structure is a conductive bump.

9. The optoelectronic chip packaging structure according to claim 8, characterized in that, The second bonding structure is a solder ball.

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