Scan chain reordering method, computer equipment and storage medium

Abstract

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a scan chain and a plurality of elements contained in the scan chain according to the chip design layout; grouping according to the number of the plurality of elements to generate at least one group of element sets; reordering the at least one group of element sets, and generating at least one sub-chain corresponding to the at least one group of element sets; and splicing the at least one sub-chain so as to complete the reordering of the scanning chain.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip layout planning, and particularly to a scan chain reordering method, a computer device, and a storage medium. Background Art

[0002] A scan chain is a commonly used digital integrated circuit (IC) testing technology and belongs to the category of design for testability (DFT). Scan reorder refers to the process of reorganizing the scan chain during the chip design process.

[0003] With the development of chip technology, some scan chains are designed to be very long. If these scan chains are reordered according to the methods of related technologies, the overall time consumption will be very long, seriously affecting the overall efficiency.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure proposes a scan chain reordering method, a computer device, and a storage medium to solve or partially solve the above problems.

[0006] Based on the above purpose, in a first aspect, the present disclosure provides a scan chain reordering method, including: Obtain a chip design layout; Determine a scan chain and a plurality of components included in the scan chain according to the chip design layout; Group according to the number of the plurality of components to generate at least one set of component sets; Reorder the at least one set of component sets to generate at least one sub-chain corresponding to the at least one set of component sets; Splice the at least one sub-chain to complete the reordering of the scan chain.

[0007] In a second aspect, the present disclosure provides a computer device, including one or more processors and a memory; and one or more programs, where the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0008] In a third aspect, the present disclosure provides a non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to execute the method according to the first aspect.

[0009] As can be seen from the above, the present disclosure provides a scan chain reordering method, a computer device, and a storage medium. First, the present disclosure determines any scan chain through the chip design layout, then determines the number of components included in the scan chain, groups the components included in the scan chain according to the number of components, then reorders each group of components according to relevant reordering rules to generate multiple sub-chains corresponding to each group of components, and finally splices these sub-chains to complete the reordering of the scan chain. This is equivalent to splitting the scan chain. After reordering each split sub-chain, the re-ordered sub-chains are spliced to form a re-ordered scan chain. In this way, an overly long scan chain can be re-ordered in segments, and parallel re-ordering of each segmented group can be performed using multi-threading or other methods, thereby greatly optimizing the running time of scan chain reordering and improving the overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 Shows a schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present disclosure.

[0012] Figure 2 Shows a schematic diagram of the basic structure of an EDA tool provided by an embodiment of the present disclosure.

[0013] Figure 3 Shows a schematic diagram of the basic execution flow of a calculation command of an EDA tool provided by an embodiment of the present disclosure.

[0014] Figure 4 Shows a schematic diagram of the flow of an exemplary method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To make the objectives, technical solutions, and advantages of this specification clearer, the following further details this specification in conjunction with specific embodiments and with reference to the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements, objects or method steps appearing before the word cover the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships, and when the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0017] Figure 1 FIG. shows a schematic structural diagram of a computer device 100 provided by an embodiment of the present disclosure. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the device through the bus 110.

[0018] The processor 102 may be a central processing unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to execute functions related to the technologies described in the present disclosure. In some embodiments, the processor 102 may further include multiple processors integrated as a single logic component. As Figure 1 shown, the processor 102 may include multiple processors 102a, 102b, and 102c.

[0019] The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of the present disclosure) and data to be processed. The processor 102 can also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0020] The network interface 106 can be configured to provide communication with other external devices to the computer device 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0021] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, various sensors, etc. and output devices such as a display, a speaker, a vibrator, an indicator light, etc.

[0022] The bus 110 can be configured to transmit information between the various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), etc.

[0023] It should be noted that although the above devices only show the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above devices may also only include the components necessary for implementing the solution of the embodiments of the present disclosure and do not necessarily include all the components shown in the figure.

[0024] Figure 2 Shows a schematic diagram of the basic structure of an EDA tool 200 according to an embodiment of the present disclosure.

[0025] As Figure 2As shown, the part above the dashed line is the user part; the part below the dashed line is the EDA tool 200, which can be implemented by the device 100 shown in Figure 1 In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The EDA tool 200 can include a Tcl command (or graphical / window interface) module 204, various computing modules (such as a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by inputting relevant commands in the Tcl command (or graphical / window interface) module 204.

[0026] The Tcl command module 204 mainly functions as message passing or command passing. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can, according to the specific content of the instructions, allocate and transfer them to the corresponding computing modules to perform specific tasks.

[0027] According to different computing tasks, the various computing modules can be divided into, for example, a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection method between the components, and the Optimization computing module 210 can be used to optimize the placement positions and wire connection methods between the components. The computing processes of these computing modules can be performed, for example, in Figure 1 the processor 102.

[0028] The database system 212 can be used to comprehensively record and store all information of the chip being simulated or designed (such as position, orientation, size, structure, wire connection method, etc.). This information can be stored, for example, in Figure 1 the memory 104.

[0029] Figure 3 shows a basic execution flow 300 of a computing command of the EDA tool 200 according to an embodiment of the present disclosure. As Figure 3As shown, in step 302, user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses this command and distributes it to the corresponding computing module (e.g., Place computing module 206). In step 306, each computing module performs the specific calculations required by itself. During this period, as shown in step 308, each computing module needs to (frequently and repeatedly) retrieve data from the database system 212 for calculations. After the calculations are completed, as shown in step 310, each computing module can write the calculation results into the database system 212 and return the calculation results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation results to the user 202 through the command interface or graphical user interface (GUI), and the processing process of the EDA tool 200 for a calculation command ends. In step 314, the user can evaluate according to the calculation results and then determine the next plan.

[0030] In some embodiments, a scan chain is a design-for-testability technique that allows testers to externally control and observe the signal values of internal flip-flops in a circuit by implanting shift registers. Its basic principle is to connect all the flip-flops in the design into a chain, driven by a unified scan clk, and shift each bit into the chip one by one through a pre-designed scan pattern. Then, the capture enable is turned on, and the output of the Q terminal (output terminal) of each flip-flop will be fed into the combinational circuit it drives. The D terminal (input terminal) of the next-level flip-flop will capture the output of this combinational circuit. Finally, a set of result vectors will be obtained at the output of the scan chain and compared with the expected values pre-calculated by the tool to determine whether there are manufacturing errors in the chip. Scan Reorder refers to the process of reordering the scan chain during the chip design process. A scan chain is a design method in design for testability (DFT). By replacing ordinary registers with registers with scan functions and connecting them into a chain through specific input and output ports, it is possible to perform shift operations through external control during testing, thereby enabling the testing of the internal logic of the chip. The main role of scan chain reordering is to optimize the connection method of the scan chain to ensure that data can flow quickly and safely.

[0031] With the increasing complexity of chip design, very long scan chains may appear in some scenarios. These scan chains may contain tens of thousands or even hundreds of thousands of components (inst). If such scan chains need to be reordered, directly reordering the entire scan chain using the reordering means of related technologies will result in a very long overall reordering time, which may reach dozens of minutes or even several hours. Such long time consumption and low efficiency can no longer meet the current high-efficiency requirements of the EDA industry.

[0032] In view of this, the present disclosure proposes a scan chain reordering method. First, the present disclosure determines any scan chain through the chip design layout, then determines the number of components included in the scan chain, groups the components included in the scan chain according to the number of components, and then reorders each group of components according to relevant reordering rules to generate multiple sub-chains corresponding to each group of components. Finally, these sub-chains are spliced to complete the reordering of the scan chain. This is equivalent to splitting the scan chain, reordering each split sub-chain, and then splicing the reordered sub-chains to form the reordered scan chain. In this way, the overly long scan chain can be reordered in segments, and multi-threading and other methods can be used to parallelly reorder each segmented group, thereby greatly optimizing the running time of scan chain reordering and improving the overall efficiency.

[0033] Figure 4 FIG. shows a schematic flowchart of an exemplary method 400 provided by an embodiment of the present disclosure. The method 400 can be implemented by Figure 1 a computer device 100 and can be implemented as Figure 2 a part of the function of an EDA tool 200. As Figure 4 shown, the method 400 may further include the following steps.

[0034] Step 402, obtaining a chip design layout.

[0035] Generally, a chip design layout includes each layer structure for chip processing, specifically the layout of transistors, wiring, routing, the connection positions of via holes between channels, and so on. According to this chip design layout, a chip processing service provider can directly operate and carry out batch processing production of the chip. Further, the chip design layout itself is drawn step by step, accompanied by various optimizations, and finally the entire chip design layout is completed. In the initial stage of the chip design layout, it may only indicate the functional information of the layers, such as a certain layer is a routing layer, a certain layer is an insulating layer, etc.; or only set various functional components and mark the positions, sizes, and other information of each functional component. Then, step-by-step design and optimization are carried out using EDA tools and the like, and finally a complete version of the chip design layout is formed. Here, the so-called components (inst) can be standard processing units, modules or hard cores, input / output terminals, registers, etc. in the chip.

[0036] In this step, since this embodiment is related to operations on the scan chain, generally, a chip design layout with the relevant scan chain drawn thereon needs to be obtained. Through this chip design layout, the specific form and relevant attribute data of the current scan chain can be determined, such as the starting position of the scan chain (which can be represented by coordinates, etc.), the ending position, the connection relationship between each component in the scan chain, the setting positions of these components (which can be represented by coordinates, etc.), and so on. In a specific application scenario, initial data information such as scan chain data and component positions can be obtained through the DEF (Design Exchange File, physical information of the design library) file and / or LEF (Library Exchange File, physical information of the process library) file of the chip design layout.

[0037] In addition, in this step, the chip design layout can be partial (for example, dividing the entire design layout into a large number of sub-regions) or it can be the whole.

[0038] Step 404, determine the scan chain and the multiple components included in the scan chain according to the chip design layout.

[0039] In this step, after obtaining the chip design layout, at least one scan chain can be determined according to the records therein. These scan chains generally have a starting position, and then starting from the starting position, they pass through multiple components in series and / or in parallel and reach the ending position. It should be noted that in this embodiment, generally at least two components are included in one scan chain. If a scan chain only includes one component, then there is no need to reorder the scan chain itself.

[0040] After determining a scan chain, according to the chip design layout, the multiple components included in the scan chain can be further determined, and the relevant attributes of these components can be determined through the chip design layout, such as the connection relationship and setting position of each component and other attribute information.

[0041] Step 406: Group the multiple components according to the number of the components to generate at least one set of component sets.

[0042] In this step, after determining the multiple components included in the scan chain, the number of components included in the scan chain can be determined by reading the chip design layout data or by statistical means. Further, these components can be grouped according to this number to generate at least one component set.

[0043] In some embodiments, the number of groups to be divided can be preset, and these components can be grouped accordingly. For example, if it is necessary to divide into 5 groups, after determining the number of components, these components can be divided into 5 groups by means of random, equal division, nearest clustering (taking distance as a reference, clustering components with close distance), etc., to generate 5 component sets.

[0044] In other embodiments, the maximum number of components included in each group can also be set, and these components can be grouped accordingly. For example, if the number of components is 200 and the maximum number of components included in a group is 20, then the components need to be divided into 10 groups to generate 10 component sets.

[0045] Further, in order to improve the processing efficiency, the processing capacity of the relevant processor can be determined in advance, and a set threshold can be set according to the processing capacity. If the number of components does not exceed the set threshold, there is no need to group, and the entire scan chain can be directly re-ordered; if the number of components exceeds the set threshold, grouping is required. Specifically, the ceiling value can be taken according to the ratio of the number of components to the set threshold. For example, for 100 components and a set threshold of 20, it is divided into 5 component sets; if the set threshold is 30, it is divided into 4 component sets. In this way, the processing capacity of the processor can be fully utilized, and the scan chain can be grouped and re-ordered to improve the overall re-ordering efficiency. That is, in some embodiments, the grouping according to the number of the multiple components includes: determining a set threshold; determining the number of groups according to the ratio between the number and the set threshold.

[0046] Furthermore, in some specific application scenarios, due to different grouping strategies or grouping methods, for example, when grouping components using some algorithms, the number of components in each component set may be different. As a result, according to the method of the foregoing embodiments, the number of components in a certain component set may exceed the set threshold. In this case, reordering the component set will also affect the overall efficiency. Therefore, to prevent the above situation and provide more fault tolerance space for reordering, a set number of groups can be added based on the foregoing grouping number to determine the final grouping number. For example, if the grouping number determined according to the ratio between the number of components and the set threshold is 5, at this time, 1 (set number) grouping can be added on the basis of 5, and the final grouping number is changed to 6. That is, in some embodiments, after determining the grouping number according to the ratio between the number and the set threshold, the method further includes: adding a set number on the basis of the determined grouping number to update the grouping number.

[0047] In some embodiments, when arranging and connecting components in chip design, there is an important parameter that needs to be considered, namely the wirelength gain. When adjusting components and / or adjusting connections each time, it is desired to minimize the loss of wirelength gain. For the scenario of this embodiment, if considering minimizing the loss of wirelength gain, during the reordering process, components with close distances should be rearranged together or grouped into one group as much as possible. In a specific application scenario, first, according to the chip design layout, etc., the distances between various components in the scan chain can be determined, and then these components can be clustered using a clustering algorithm based on these distances to complete the grouping of these components. Finally, the components in each group of component sets can be made as close as possible to reduce the optimization loss of the global wirelength gain. For example, assume that 100 components need to be divided into 5 groups of component sets. The clustering algorithm can be used to randomly select 5 origin points first, and then, according to the distances between the components, clustering is performed with these 5 origin points as the centers. After the initial clustering, the center origin of each clustering set is re-determined and clustering is performed again. By iterating in this way, after reaching the set termination condition, the grouping of 5 groups of component sets is completed. That is, in some embodiments, the grouping according to the number of the multiple components includes: determining the distances between the multiple components; clustering the multiple components using a clustering algorithm according to the distances; and performing the grouping according to the clustering results.

[0048] Further, in some more specific application scenarios, for a large number of clustering algorithms, considering the application scenarios of this embodiment and the requirements for aspects such as convergence speed and scalability, the K-means clustering algorithm can be selected to perform clustering. That is, in some embodiments, the clustering algorithm includes the K-means clustering algorithm.

[0049] Still further, in a specific application scenario, when using the clustering algorithm to cluster the components in the scan chain, due to reasons such as too many clustering objects (components), the particularity of the clustering objects (components), or the particularity of the connection relationships of the clustering objects (components), the clustering convergence process sometimes takes a long time, which may also affect the overall efficiency. Therefore, it is possible to consider accelerating the clustering algorithm. For example, it can be accelerated by reducing dimensions (such as principal component analysis PCA, etc.), using an efficient database (such as using the NumPy library, etc.), local sensitive hashing (LSH), etc. And due to its outstanding performance in optimizing data structures, automatic vectorization, etc., the Eigen template library can be selected to accelerate the clustering algorithm, and in the specific application scenario of this embodiment, the Eigen template library also shows relatively prominent advantages, greatly reducing the clustering process for components. Among them, the Eigen template library is a C++ template library for linear algebra: used for matrices, vectors, numerical solvers, and related algorithms. That is, in some embodiments, clustering the multiple components according to the distance using the clustering algorithm includes: accelerating the clustering algorithm using the Eigen template library.

[0050] Step 408, reorder the at least one set of component sets to generate at least one sub-chain corresponding to the at least one set of component sets.

[0051] In this step, after determining the component sets, since these component sets are essentially part of the scan chain, the reordering rules originally for the scan chain can be used to reorder these component sets. Here, it can be understood that the scan chain is divided into multiple sub-chains and these sub-chains are reordered. The specific reordering rules can be specifically set according to the specific application scenario, and its main purpose is to optimize the component connection relationships. By reordering the at least one set of component sets, adjusting the connection relationships of the components in each set of component sets, after optimizing the connection relationships, at least one re-ordered sub-chain can be generated, where one sub-chain corresponds to one set of component sets.

[0052] In some embodiments, to facilitate subsequent splicing processes, the sub-chain can be adjusted to a circular sub-chain. In this way, no matter which element in the sub-chain is used as the starting point for splicing, the entire sub-chain can be spliced according to the circular sub-chain, and a unique element located at the end can be determined to facilitate the splicing of the next sub-chain. That is, in some embodiments, the at least one sub-chain includes a circular chain.

[0053] Step 410, splice the at least one sub-chain to complete the reordering of the scan chain.

[0054] In this step, after the reordering of each sub-chain is completed, these sub-chains need to be spliced together to restore a complete scan chain. For splicing, it can be performed according to a preset setting. For example, before the reordering, the order of the sub-chains corresponding to each element set during splicing has been determined. This order can be set manually or determined according to other requirements.

[0055] After that, in some embodiments, the splicing order and / or splicing method, etc. can be determined according to certain attributes of the sub-chains. In the specific application process, for a scan chain, it can be a long single chain or a multi-chain form including multiple sub-chains; after that, for a scan chain, it generally has a starting position and an ending position, that is, the starting point and the ending point of a scan chain, and the starting point and the ending point will have corresponding specific position information in the chip design layout (such as starting point coordinates and ending point coordinates, etc.), and at the same time each component will also correspond to a specific setting position in the chip design layout (such as the position coordinates of each component, etc.). Thus, the splicing method and / or order can be determined according to the relative position relationship between the position coordinates of the components included in each sub-chain and the starting point coordinates and the ending point coordinates. For example, assume there are 3 sub-chains: sub-chain A, sub-chain B, and sub-chain C. In the first scenario, the distance between the component closest to the starting position in sub-chain A and the starting position is 3 units, the distance between the component closest to the starting position in sub-chain B and the starting position is 8 units, and the distance between the component closest to the starting position in sub-chain C and the starting position is 13 units. Then it can be determined that the connection order is that sub-chain A is first connected to the starting position, then sub-chain B is connected to sub-chain A, and finally sub-chain C is connected to sub-chain B; in the second scenario, after determining a similar distance to the first scenario, first connect sub-chain A to the starting position, and then, taking the component at the end of sub-chain A as the target component, determine the distance between the components in sub-chain B and sub-chain C and the target component. Assume that in this case, a certain component in sub-chain C is the closest to the target component, then connect sub-chain C after sub-chain A, and so on; in the third scenario, assume that it is determined that there are components in both sub-chain A and sub-chain B with a distance of 3 units from the starting position, then it can be considered that sub-chain A and sub-chain B are connected side by side to the starting position, and the sub-chain splicing is carried out accordingly. That is, in some embodiments, the splicing of the at least one sub-chain includes: determining the starting position of the scan chain and the setting positions of the multiple components according to the chip design layout; taking the starting position as the origin, sorting the at least one sub-chain according to the setting positions of the components included in the at least one sub-chain; and completing the splicing of the at least one sub-chain in order according to the sorting result, taking the starting position as the origin.

[0056] Further, considering the continuity of splicing, the loss of wire length gain during the splicing of sub-chains, etc., when connecting sub-chains, try to find the sub-chain where the component closest to the component at the end of the sub-chain is located after the sorted or connected sub-chain as the next sub-chain. Of course, if there is not yet a sub-chain that has been sorted or connected, the sub-chain where the component closest to the starting position is located can be determined as the sub-chain connected to the starting position. For example, assume there are three sub-chains: Sub-chain A, Sub-chain B, and Sub-chain C. When starting the sorting (usually when all sub-chains have not been sorted), the relative position relationship between the components included in each of the three sub-chains and the starting position can be determined first. Assume that it is determined that Sub-chain A contains the component closest to the starting position. Then Sub-chain A is the first sub-chain to be sorted, and when connecting, the component closest to the starting position can be connected to the starting position. After expanding according to the connection order of Sub-chain A, the first component at the end of Sub-chain A can be determined. Then, based on the position of the first component, the second component closest to the target component is determined in Sub-chain B and Sub-chain C. Assume that the second component exists in Sub-chain B. Then Sub-chain B connects the second component to the first component. After expanding according to the connection order of Sub-chain B, the third component at the end of Sub-chain B can be determined. Then, in a similar manner to Sub-chain B, the connection of Sub-chain C is completed. That is, in some embodiments, the sorting of the at least one sub-chain includes: in response to the existence of unsorted sub-chains, determining, according to the set position, the sub-chain where the component closest to the starting position is located as the first sub-chain to be sorted; in response to the existence of sorted sub-chains, determining the component at the end of the sub-chain that is currently the last in the sorting as the end component (which can correspond to the aforementioned first component), and according to the set position, determining the sub-chain where the component closest to the end component (which can correspond to the aforementioned second component) is located as the next sub-chain in the current sorting.

[0057] As can be seen from the above, the embodiments of the present disclosure provide a scan chain reordering method. The present disclosure first determines any scan chain through the chip design layout, then determines the number of components included in the scan chain, groups the components included in the scan chain according to the number of components, then reorders each group of components according to relevant reordering rules to generate multiple sub-chains corresponding to each group of components, and finally splices these sub-chains to complete the reordering of the scan chain. This is equivalent to splitting the scan chain, reordering each split sub-chain, and then splicing the reordered sub-chains to form a reordered scan chain. In this way, an overly long scan chain can be reordered in segments, and parallel reordering of each segmented group can be performed using multi-threading or other methods, which can greatly optimize the running time of scan chain reordering and improve the overall efficiency.

[0058] As can be seen above, the present disclosure forms sub-chains by using the K-means clustering algorithm accelerated by the Eigen template library for scan chains with the number of components greater than a set threshold, then uses the divide-and-conquer strategy to reorder the scan chains for these sub-chains, and then splices these reordered sub-chains, thereby efficiently and maximally reducing the loss of wire length gain, and thus solving the high computational complexity problem in the reordering of ultra-long scan chains (including tens of thousands to hundreds of thousands of instances).

[0059] It should be noted that the method of the embodiments of the present disclosure can be executed by a single device, such as a computer or a server. The method of the embodiments of the present disclosure can also be applied to a distributed scenario and completed by the cooperation of multiple devices. In such a distributed scenario, one of the multiple devices can only execute one or more steps of the method of the embodiments of the present disclosure, and these multiple devices will interact with each other to complete the described method.

[0060] It should be noted that the above describes specific embodiments of the present disclosure. In some cases, the actions or steps recorded in the above embodiments of the present disclosure can be executed in a different order from that in the above embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0061] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program. The non-volatile computer-readable storage medium containing the computer program stores computer instructions, and the computer instructions are used to cause the computer to execute the method 400 described in any of the above embodiments.

[0062] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0063] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the method 400 described in any of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0064] Based on the same inventive concept, corresponding to the method 400 in any of the above embodiments, the present application further provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to execute the method 400. Corresponding to the execution subjects of the respective steps in the embodiments of the method 400, the processors executing the corresponding steps may belong to the corresponding execution subjects.

[0065] The computer program product of the above embodiments is used to cause a processor to execute the method 400 described in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0066] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application is limited to these examples; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0067] In addition, for the sake of simplicity of description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. In addition, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0068] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0069] Embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the above embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A scan chain reordering method, characterized in that: include: Obtain chip design layout; Determine a scan chain and a plurality of components included in the scan chain according to the chip design layout; Grouping the plurality of components according to the number of components to generate at least one set of components; Reordering the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets; The at least one sub-chain is spliced ​​to complete the reordering of the scan chain.

2. The method according to claim 1, characterized in that The grouping according to the number of the plurality of elements comprises: Determine the set threshold; The number of groups is determined according to a ratio between the number and the set threshold.

3. The method according to claim 2, characterized in that After determining the number of groups according to the ratio between the number and the set threshold, the method further includes: The set number is increased based on the determined number of groups, thereby updating the number of groups.

4. The method according to claim 1, characterized in that: The grouping according to the number of the plurality of elements comprises: determining distances between the plurality of elements; Clustering the plurality of elements using a clustering algorithm according to the distance; The grouping is performed according to the clustering result.

5. The method according to claim 4, characterized in that The clustering of the plurality of elements by using a clustering algorithm according to the distance comprises: The clustering algorithm is accelerated using the Eigen template library.

6. The method according to claim 4, characterized in that The clustering algorithm includes a K-means clustering algorithm.

7. The method according to claim 1, characterized in that The at least one sub-chain comprises an endless chain.

8. The method according to claim 1, characterized in that The step of splicing the at least one subchain comprises: Determining the starting position of the scan chain and the setting positions of the multiple components according to the chip design layout; Taking the starting position as the origin, sorting the at least one sub-chain according to the setting positions of the elements included in the at least one sub-chain; According to the sorting result, the splicing of the at least one subchain is completed in order with the starting position as the origin.

9. The method according to claim 8, characterized in that The sorting of the at least one subchain comprises: In response to the sub-chains that have not completed sorting, determining, according to the setting position, the sub-chain where the element closest to the starting position is located as the first sub-chain to be sorted; In response to the existence of a subchain that has been sorted, the element at the end of the last subchain currently sorted is determined as the last element, and according to the set position, the subchain where the element closest to the last element is located is determined as the next subchain currently sorted.

10. A computer device, characterized in that: The method comprises one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 9.

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