A General Double-End Current Output Memristor Simulator

Abstract

The present invention provides a general double - terminal current output memristor emulator, which includes a double - terminal current output module, an operation module, and an integration module. The operation module contains two four - quadrant multipliers based on the 444 circuit: Through the feedback control of the operation module, the present invention realizes double - terminal current output in cooperation with the double - terminal current output module, and realizes the accurate operation of the internal variables of the memristor in cooperation with the integration module. The double - terminal memristor emulator designed by the present invention has a compact structure and rich functions, and has the characteristics of strong generality and wide application range, and can be widely applied to fields such as nonlinear systems, neural network computing, and encrypted communication.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronic circuits and non - linear systems, and particularly to a general dual - terminal current - output memristor emulator. Background Art

[0002] As a non - linear electronic device with memory characteristics, the memristor emulator has shown great application potential in the fields of non - volatile storage, neural network computing, chaotic systems, etc. since its proposal. However, limited by the current manufacturing process, the commercial application of actual memristor emulators still faces many challenges. Therefore, in the prior art, a design scheme of an equivalent memristor emulator is widely adopted, that is, the current - voltage characteristics of the memristor emulator are realized through analog circuits. In recent years, with the rapid development of applications such as chaotic signal generation, encrypted communication, and neural network computing, higher requirements have been put forward for the functionality and integration of equivalent memristor emulators. However, the existing equivalent memristor emulator technology still has many limitations, which are specifically manifested as follows:

[0003] Single function and limited application: Patent CN115499116B (A method for realizing a simple memristive hyper - chaotic circuit with a large - scale parameter range) adopts a discretized single - chip microcomputer implementation method. Although it can generate chaotic signals with a large - scale parameter range, its digital - circuit - based design cannot fully utilize the analog characteristics of the memristor emulator, and the circuit is complex, making it difficult to meet the requirements of high - efficiency and compact applications.

[0004] Limitations of single - terminal memristors: The power supply part in CN113445076B (A method for reducing metal dendrites in manganese electrodeposition) adopts a single - terminal equivalent memristor chaotic oscillator. In this design, one end of the memristor emulator is connected to the high - input - impedance terminal of AD633, and it is assumed that the current at this port is zero in the calculation. Therefore, it is not a true dual - terminal memristor emulator. This design limits the bidirectional current control ability of the memristor emulator and makes it difficult to perform complex non - linear operations.

[0005] Complex structure and cost problems of dual - terminal memristors: Although patent CN119358572A (A switchable floating - ground memristor emulator based on bidirectional symmetry characteristics) realizes the dual - terminal equivalent memristor function, there is a problem that the pins of AD844 are left floating in its design, resulting in low utilization rate. In addition, this design requires multiple commercial multipliers AD633, which not only increases the circuit complexity but also significantly increases the cost, making it difficult to meet the requirements of large - scale integration and low - cost applications. Summary of the Invention

[0006] Object of the Invention: Aiming at the deficiencies of the prior art, the present invention provides a general dual - terminal current - output memristor emulator to solve the problems of the existing equivalent memristor emulator technology in terms of complex structure, single function, low integration, and high cost.

[0007] The general dual - terminal current - output memristor emulator includes a dual - terminal current - output module, an operation module, and an integration module;

[0008] The operation module contains two four - quadrant multipliers (444FQ) based on the 444 circuit;

[0009] The integration module is used for controlling the internal variables of the memristor;

[0010] The four - quadrant multiplier (444FQ) based on the 444 circuit includes four improved TGA - SN modules (SNx), a 444 - circuit core (444Core), and a gate circuit.

[0011] The dual - terminal current - output module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 、an eleventh resistor R 11 、a twelfth resistor R 12 、a thirteenth resistor R 13 、a fourteenth resistor R 14 、a fifteenth resistor R 15 、a sixteenth resistor R 16 、a seventeenth resistor R 17 、a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8.

[0012] One end of the first resistor R1 is the equivalent output port VM+ of the general dual - terminal current - output memristor emulator, and the other end is connected to the output terminal VR1 of the third operational amplifier U3;

[0013] Both ends of the second resistor R2 are respectively connected to the output terminal V+ of the first operational amplifier U1 and the inverting input terminal of the second operational amplifier U2;

[0014] Both ends of the third resistor R3 are respectively connected to the output terminal - V+ of the second operational amplifier U2 and the inverting input terminal of the second operational amplifier U2;

[0015] Both ends of the fourth resistor R4 are respectively connected to the output terminal VI of the thirteenth element U 13 of the operation module including two four - quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the third operational amplifier U3;

[0016] Both ends of the fifth resistor R5 are respectively connected to the output terminal - V+ of the second operational amplifier U2 and the inverting input terminal of the third operational amplifier U3;

[0017] Both ends of the sixth resistor R6 are respectively connected to the output terminal VR1 of the third operational amplifier U3 and the inverting input terminal of the third operational amplifier U3;

[0018] One end of the seventh resistor R7 is the equivalent output port VM- of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR2 of the operational amplifier U6;

[0019] Both ends of the eighth resistor R8 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the fifth operational amplifier U5;

[0020] Both ends of the ninth resistor R9 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the fifth operational amplifier U5;

[0021] Both ends of the tenth resistor R 10 are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the sixth operational amplifier U6;

[0022] Both ends of the eleventh resistor R 11 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the sixth operational amplifier U6;

[0023] Both ends of the twelfth resistor R 12 are respectively connected to the output terminal VR2 of the sixth operational amplifier U6 and the inverting input terminal of the sixth operational amplifier U6;

[0024] Both ends of the thirteenth resistor R 13 are respectively connected to the output terminal VI of the thirteenth element U of the operation module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the seventh operational amplifier U7; 13 and the inverting input terminal of the seventh operational amplifier U7;

[0025] Both ends of the fourteenth resistor R 14 are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the seventh operational amplifier U7;

[0026] Both ends of the fifteenth resistor R 15 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the eighth operational amplifier U8;

[0027] Both ends of the sixteenth resistor R 16 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the eighth operational amplifier U8;

[0028] Both ends of the seventeenth resistor R 17 are respectively connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the eighth operational amplifier U8;

[0029] The output terminal of the first operational amplifier U1 is connected to the inverting input terminal;

[0030] The output terminal of the fourth operational amplifier U4 is connected to the inverting input terminal.

[0031] The non-inverting input terminals of operational amplifiers U2, U3, U5, U6, U7, and U8 are grounded.

[0032] The operation module includes the eighteenth resistor R 18 , the nineteenth resistor R 19 , the ninth operational amplifier U9, the twelfth component U 12 , the thirteenth component U 13 , where the twelfth component U 12 , the thirteenth component U 13 is a four-quadrant multiplier (444FQ) based on a 444 circuit.

[0033] The two ends of the eighteenth resistor R 18 are respectively connected to the output terminal VM of the eighth operational amplifier U8 of the differential current output module and the inverting input terminal of the ninth operational amplifier U9.

[0034] The two ends of the nineteenth resistor R 19 are respectively connected to the output terminal of the ninth operational amplifier U9 and the inverting input terminal of the ninth operational amplifier U9.

[0035] The input terminal X of the twelfth component U 12 is connected to the output terminal VM of the eighth operational amplifier U8 of the differential current output module, the input terminal Y is connected to the output terminal z of the tenth operational amplifier U 10 of the integration module for controlling the internal variable of the memristor, and the input terminal Z is connected to the output terminal of the ninth operational amplifier U9.

[0036] The input terminal X of the thirteenth component U 13 is connected to the output terminal VM of the eighth operational amplifier U8 of the differential current output module, the input terminal Y is supplied with a +1V voltage by an independent power supply, and the input terminal Z is connected to the cathode of the first diode D1 of the integration module for controlling the internal variable of the memristor.

[0037] The non-inverting input terminal of the operational amplifier U9 is grounded.

[0038] The integration module includes the twentieth resistor R 20 , the twenty-first resistor R 21 , the twenty-second resistor R 22 , the twenty-third resistor R 23 , the first capacitor C1, the first diode D1, the tenth operational amplifier U 10 , the eleventh operational amplifier U 11 .

[0039] The two ends of the twentieth resistor R 20is connected to the output terminal of the twelfth element U of the operation module including two four-quadrant multipliers (444FQ) based on 444 circuits at both ends 12 and the inverting input terminal of the tenth operational amplifier U 10 respectively;

[0040] Both ends of the twenty-first resistor R 21 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 respectively;

[0041] Both ends of the twenty-second resistor R 22 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the eleventh operational amplifier U 11 respectively;

[0042] Both ends of the twenty-third resistor R 23 are respectively connected to the cathode of the first diode D1 and the inverting input terminal of the eleventh operational amplifier U 11 respectively;

[0043] Both ends of the first capacitor C1 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 respectively;

[0044] The anode of the first diode D1 is connected to the output terminal of the eleventh operational amplifier U 11 , and the cathode is connected to the input terminal Z of the thirteenth element U of the operation module including two four-quadrant multipliers (444FQ) based on 444 circuits 13 respectively;

[0045] The non-inverting input terminals of the operational amplifiers U 10 , U 11 are grounded.

[0046] The general dual-terminal current output memristor emulator is a combination of two single-terminal floating-ground memristor emulators.

[0047] When constructing the general dual-terminal current output memristor emulator with an equivalent circuit, the following formula is obtained:

[0048] (1),

[0049] where V represents the voltage across the memristor emulator, I represents the current flowing through the memristor emulator internally, VM+ and VM- represent the voltage values of both ends of the memristor emulator with respect to ground, VR1 and VR2 represent the voltage values of the outputs of two controlled voltage sources with respect to ground, and R1 and R7 represent the resistance values of the resistors.

[0050] By transforming formula (1), the relationship between the calculated VR1 and VR2 and the voltages VM+ and VM- to the ground at both ends of the memristor emulator, as well as the current memductance W of the memristor emulator, is obtained:

[0051] (2),

[0052] where W (S, V) represents the memductance function of the memristor emulator, and S is the state variable.

[0053] The present invention has the following beneficial effects: Compact structure: A four-quadrant multiplier based on the 444 circuit module is adopted, and its three input ports and internal parts are highly integrated, avoiding the use of multiple discrete components in traditional designs, and significantly reducing the circuit complexity and power consumption.

[0054] Rich functions: Through the collaborative design of the dual-terminal equivalent memristor structure and the four-quadrant multiplier, complex non-linear operations and bidirectional current control are realized, providing an efficient solution for applications such as non-linear systems and neural network computing.

[0055] Low cost: By optimizing the circuit design and improving the component utilization rate, the use of high-cost commercial multipliers in traditional designs is avoided, and the manufacturing cost is significantly reduced.

[0056] The present invention designs a general dual-terminal current output memristor emulator, which solves the deficiencies of the existing equivalent memristor emulator technology in terms of structure, function, and cost, and provides an efficient, compact, and low-cost solution for fields such as non-linear systems, neural network computing, and encrypted communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is the internal structure diagram of a general dual-terminal current output memristor emulator provided by an embodiment of the present invention.

[0058] Figure 2 is the diagram of a four-quadrant multiplier (444FQ) based on the 444 circuit and its package.

[0059] Figure 3 is the improved TGA-SN (SNx) and its package diagram.

[0060] Figure 4 is the frequency response diagram of a general dual-terminal current output memristor emulator provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0061] The following further detailed description of the present invention is made in conjunction with the drawings and specific embodiments, and the above and / or other advantages of the present invention will become clearer.

[0062] As Figure 1As shown in the figure, an embodiment of the present invention provides a general dual - terminal current output memristor emulator, which includes a dual - terminal current output module, an operation module, and an integration module;

[0063] The operation module includes two four - quadrant multipliers (444FQ) based on the 444 circuit;

[0064] The integration module is used for internal variable control of the memristor;

[0065] The four - quadrant multiplier (444FQ) based on the 444 circuit includes four improved TGA - SN modules (SNx), a 444 circuit core (444Core), and a gate circuit.

[0066] As Figure 1 shown, the dual - terminal current output module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 、eleventh resistor R 11 、twelfth resistor R 12 、thirteenth resistor R 13 、fourteenth resistor R 14 、fifteenth resistor R 15 、sixteenth resistor R 16 、seventeenth resistor R 17 、a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8;

[0067] One end of the first resistor R1 is the equivalent output port VM+ of the general dual - terminal current output memristor emulator, and the other end is connected to the output terminal VR1 of the third operational amplifier U3; both ends of the second resistor R2 are respectively connected to the output terminal V+ of the first operational amplifier U1 and the inverting input terminal of the second operational amplifier U2; both ends of the third resistor R3 are respectively connected to the output terminal - V+ of the second operational amplifier U2 and the inverting input terminal of the second operational amplifier U2; both ends of the fourth resistor R4 are respectively connected to the thirteenth element U of the operation module including two four - quadrant multipliers (444FQ) based on the 444 circuit 13The output terminal VI is connected to the inverting input terminal of the third operational amplifier U3; both ends of the fifth resistor R5 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the third operational amplifier U3; both ends of the sixth resistor R6 are respectively connected to the output terminal VR1 of the third operational amplifier U3 and the inverting input terminal of the third operational amplifier U3; one end of the seventh resistor R7 is the equivalent output port VM- of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR2 of the operational amplifier U6; both ends of the eighth resistor R8 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the fifth operational amplifier U5; both ends of the ninth resistor R9 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the fifth operational amplifier U5; both ends of the tenth resistor R 10 are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the sixth operational amplifier U6; the eleventh resistor R 11 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the sixth operational amplifier U6; the twelfth resistor R 12 are respectively connected to the output terminal VR2 of the sixth operational amplifier U6 and the inverting input terminal of the sixth operational amplifier U6; the thirteenth resistor R 13 are respectively connected to the output terminal VI of the thirteenth element U 13 of the operational module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the seventh operational amplifier U7; the fourteenth resistor R 14 are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the seventh operational amplifier U7; the fifteenth resistor R 15 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the eighth operational amplifier U8; the sixteenth resistor R 16 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the eighth operational amplifier U8; the seventeenth resistor R 17 are respectively connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the eighth operational amplifier U8; the output terminal of the first operational amplifier U1 is connected to the inverting input terminal; the output terminal of the fourth operational amplifier U4 is connected to the inverting input terminal; the non-inverting input terminals of the operational amplifiers U2, U3, U5, U6, U7, U8 are grounded.

[0068] As Figure 1 shown, the operational module includes the eighteenth resistor R 18 , the nineteenth resistor R 19 , the ninth operational amplifier U9, the twelfth element U 12 , the thirteenth element U 13 , where the twelfth element U 12 , the thirteenth element U 13 are four-quadrant multipliers (444FQ) based on the 444 circuit;

[0069] The eighteenth resistor R18 are respectively connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the ninth operational amplifier U9 of the dual-terminal current output module at both ends; the nineteenth resistor R 19 are respectively connected to the output terminal of the ninth operational amplifier U9 and the inverting input terminal of the ninth operational amplifier U9 at both ends; the twelfth component U 12 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U8 of the dual-terminal current output module, its input terminal Y connected to the output terminal z of the tenth operational amplifier U 10 of the integration module for memristor internal variable control, and its input terminal Z connected to the output terminal of the ninth operational amplifier U9; the thirteenth component U 13 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U8 of the dual-terminal current output module, its input terminal Y supplied with a +1V voltage by an independent power supply, and its input terminal Z connected to the cathode of the first diode D1 of the integration module for memristor internal variable control; the non-inverting input terminal of the operational amplifier U9 is grounded.

[0070] As Figure 1 shown, the integration module includes the twentieth resistor R 20 , the twenty-first resistor R 21 , the twenty-second resistor R 22 , the twenty-third resistor R 23 , the first capacitor C1, the first diode D1, the tenth operational amplifier U 10 , the eleventh operational amplifier U 11 ;

[0071] The two ends of the twentieth resistor R 20 are respectively connected to the output terminal of the twelfth component U 12 of the operational module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the tenth operational amplifier U 10 ; the two ends of the twenty-first resistor R 21 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; the two ends of the twenty-second resistor R 22 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the eleventh operational amplifier U 11 ; the two ends of the twenty-third resistor R 23 are respectively connected to the cathode of the first diode D1 and the inverting input terminal of the eleventh operational amplifier U 11 ; the two ends of the first capacitor C1 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; the anode of the first diode D1 is connected to the eleventh operational amplifier U 11is connected to the output terminal, and the cathode is connected to the thirteenth element U of the operation module including two four-quadrant multipliers (444FQ) based on the 444 circuit 13 is connected to the input terminal Z; the operational amplifier U 10 , U 11 's non-inverting input terminal is grounded.

[0072] As Figure 2 shown, Figure 1 the four-quadrant multiplier based on the 444 circuit in 24 includes the twenty-fourth resistor R 25 , the twenty-fifth resistor R 26 , the twenty-sixth resistor R 27 , the twenty-seventh resistor R 28 , the twenty-eighth resistor R 29 , the thirtieth resistor R 30 , the thirty-first resistor R 31 , the thirty-second resistor R 32 , the thirty-third resistor R 33 , the thirty-fourth resistor R 34 , the thirty-fifth resistor R 35 , the thirty-sixth resistor R 36 , the thirty-seventh resistor R 37 , the fourteenth element U 14 , the fifteenth element U 15 , the sixteenth element U 16 , the seventeenth element U 17 , the eighteenth element U 18 , the nineteenth operational amplifier U 19 , the twentieth operational amplifier U 20 , the twenty-first operational amplifier U 21 , the twenty-second NOT gate U 22 , the twenty-third NOT gate U 23 , the twenty-fourth NOT gate U 24 , the twenty-fifth XOR gate U 25 , the twenty-sixth XOR gate U 26 , the twenty-seventh operational amplifier U 27 , where the fourteenth element U 14 , the fifteenth element U 15 , the sixteenth element U 16 , the eighteenth element U 18 is an improved TGA-SN module (SNx), and the seventeenth element is the core of the 444 circuit; the two ends of the twenty-fourth resistor R 24 are respectively connected to the negative power supply VEE for powering the analog circuit and the inverting input terminal of the nineteenth operational amplifier U 19 ; the two ends of the twenty-fifth resistor R 25 are respectively connected to the fourteenth element U 14The output terminal O2(A) and the nineteenth operational amplifier U 19 The inverting input terminal are connected; the twenty-sixth resistor R 26 Both ends are respectively connected to the output terminal of the nineteenth operational amplifier U 19 And the inverting input terminal of the nineteenth operational amplifier U 19 The inverting input terminal are connected; the twenty-seventh resistor R 27 Both ends are respectively connected to the output terminal of the nineteenth operational amplifier U 19 And the input terminal of the twenty-second NOT gate U 22 The inverting input terminal are connected; the twenty-eighth resistor R 28 Both ends are respectively connected to the negative power supply VEE for supplying power to the analog circuit and the inverting input terminal of the twentieth operational amplifier U 20 The inverting input terminal are connected; the twenty-ninth resistor R 29 Both ends are respectively connected to the output terminal O2(B) of the fifteenth component U 15 And the inverting input terminal of the twentieth operational amplifier U 20 The inverting input terminal are connected; the thirtieth resistor R 30 Both ends are respectively connected to the output terminal of the twentieth operational amplifier U 20 And the inverting input terminal of the twentieth operational amplifier U 20 The inverting input terminal are connected; the thirty-first resistor R 31 Both ends are respectively connected to the output terminal of the twentieth operational amplifier U 20 And the input terminal of the twenty-third NOT gate U 23 The inverting input terminal are connected; the thirty-second resistor R 32 Both ends are respectively connected to the negative power supply VEE for supplying power to the analog circuit and the inverting input terminal of the twenty-first operational amplifier U 21 The inverting input terminal are connected; the thirty-third resistor R 33 Both ends are respectively connected to the output terminal O2(C) of the sixteenth component U 16 And the inverting input terminal of the twenty-first operational amplifier U 21 The inverting input terminal are connected; the thirty-fourth resistor R 34 Both ends are respectively connected to the output terminal of the sixth operational amplifier U6 and the inverting input terminal of the twenty-first operational amplifier U 21 The inverting input terminal are connected; the thirty-fifth resistor R 35 Both ends are respectively connected to the output terminal of the twenty-first operational amplifier U 21 And the input terminal of the twenty-fourth NOT gate U 24 The inverting input terminal are connected; the thirty-sixth resistor R 36 Both ends are respectively connected to the power supply VCC for supplying power to the digital gate circuit and the input terminal Y of the eighteenth component U 18 The inverting input terminal are connected; the thirty-seventh resistor R 37 Both ends are respectively connected to the input terminal Y of the eighteenth component U 18 And the ground. The output of the twenty-second NOT gate U 22 The output of the twenty-third NOT gate U 23 Are respectively connected to the two input terminals of the twenty-five XOR gate U 25 The twenty-five XOR gate U25 and the output of the 24th NOT gate U 24 are respectively connected to the two input terminals of the 26th XOR gate U 26 ; the output terminal of the 26th XOR gate U 26 is connected to the non-inverting input terminal of the 27th operational amplifier U 27 ; the inverting input terminal and the output terminal of the 27th operational amplifier U 27 are connected and then connected to the input terminal Z of the 18th component U 18 ; the input terminals X and Y of the 14th component U 14 are connected and used as the equivalent input terminal X of the four-quadrant multiplier based on the 444 circuit; the input terminal Z of the 14th component U 14 is grounded, and the output terminal O1 is connected to the input terminal X of the 17th component U 17 ; the input terminals X and Y of the 15th component U 15 are connected and used as the equivalent input terminal Y of the four-quadrant multiplier based on the 444 circuit; the input terminal Z of the 15th component U 15 is grounded, and the output terminal O1 is connected to the input terminal Y of the 17th component U 17 ; the input terminals X and Y of the 16th component U 16 are connected and used as the equivalent input terminal Z of the four-quadrant multiplier based on the 444 circuit; the input terminal Z of the 16th component U 16 is grounded, and the output terminal O1 is connected to the input terminal Z of the 17th component U 17 ; the output terminal O1 of the 17th component U 17 is connected to the input terminal W, and the output terminal O2 is connected to the input terminal X of the 18th component U 18 ; the output terminal O1 of the 18th component U 18 is used as the equivalent output terminal O of the four-quadrant multiplier based on the 444 circuit; the output terminal O2 is left floating and not connected; the non-inverting input terminals of the operational amplifiers U 19 , U 20 , U 21 are grounded.

[0073] As Figure 3 shown, Figure 2 the improved TGA-SN module (SNx) in 38 includes the 38th resistor R 39 , the 39th resistor R 40 , the 40th resistor R 41 , the 41st resistor R 42 , the 42nd resistor R 28 , the first transistor Q1, the 28th operational amplifier U 29 , the 29th operational amplifier U 38 , the second diode D2; both ends of the 38th resistor R 28The output terminal is connected to the base of the first transistor Q1; the thirty-ninth resistor R 39 One end is the equivalent input port X of the improved TGA-SN module, and the other end is connected to the inverting input terminal of the twenty-ninth operational amplifier U 29 The fortieth resistor R 40 Both ends are respectively connected to the output terminal of the twenty-ninth operational amplifier U 29 And the inverting input terminal of the twenty-ninth operational amplifier U 29 The forty-first resistor R 41 One end is the equivalent input port X of the improved TGA-SN module, and the other end is connected to the non-inverting input terminal of the twenty-ninth operational amplifier U 29 The forty-second resistor R 42 One end is the equivalent output port O1 of the improved TGA-SN module, and the other end is connected to the output terminal of the twenty-ninth operational amplifier U 29 The collector of the first transistor Q1 is connected to the non-inverting input terminal of the twenty-ninth operational amplifier U 29 And the emitter is grounded; the inverting input terminal of the twenty-eighth operational amplifier U 28 Is the equivalent input port Y of the improved TGA-SN module, the non-inverting input terminal is the equivalent input port Z of the improved TGA-SN module, and the output terminal is the equivalent output port O2 of the improved TGA-SN module.

[0074] As Figure 4 Shown (the input voltage is a sinusoidal signal with a peak-to-peak value of 10V. The abscissa represents the voltage difference across the memristor emulator; the ordinate represents the current flowing through the memristor emulator), when the input voltage is a sinusoidal signal with a peak-to-peak value of 10V, a general double-terminal current output memristor emulator of the present invention exhibits a good hysteresis loop, and the memristive characteristics of the circuit can be intuitively understood. Combining Figure 1 The internal structure, its ability to output double-terminal current can be clarified. Therefore, a general double-terminal current output memristor emulator of the present invention can be directly connected to the circuit like a resistor without single-ended grounding, expanding the application range of the memristor.

[0075] Common single-terminal memristor emulators usually adopt a structure with one end grounded and the other end output, and its equivalent model can be simplified to a combination of a resistor and a controlled voltage source. Specifically, the output current of the single-terminal memristor emulator is controlled by the single-terminal external voltage value, and the output of the controlled voltage source is dynamically adjusted through internal state variables, so as to realize the memory effect and non-linear characteristics of the memristor emulator. Although this design is simple and easy to implement, due to the limitation of its unidirectional current control, it is difficult to meet the requirements of complex circuit design.

[0076] The equivalent model of a two-terminal memristor emulator can be regarded as a combination of two single-terminal memristor emulators, but additional circuit elements are needed to support bidirectional current control and the calculation of internal state variables. Its core consists of two controlled voltage sources, two resistors, and a module for calculating internal state variables.

[0077] As Figure 1 shown, the two ends of the memristor emulator are represented by VM+ and VM-, and VR1 and VR2 represent the voltages of the outputs of the two controlled voltage sources with respect to ground. By controlling the outputs of the controlled voltage sources, equivalent currents are generated across resistors R1 and R7.

[0078] For a charge-controlled (current-controlled) memristor emulator, its general expression is:

[0079] (1),

[0080] Here, V represents the voltage across the memristor emulator, I represents the current flowing through the memristor emulator, S is an internal variable of the memristor emulator, and M(S, I) is a function that represents the variation law of the resistance value of the memristor emulator with the state variable S and the current I. This function describes the impedance characteristics of the memristor emulator. Specifically, M represents the resistance of the memristor emulator, and its variation reflects the historical behavior of the memristor emulator, which is the cumulative effect of current here. is the derivative of the state variable S with respect to time, representing the rate of change of the internal state of the memristor emulator, and g is a function describing the dynamic change of the internal state variable.

[0081] As Figure 1 shown, when constructing with an equivalent circuit, from the consistency and directionality of the current, there is:

[0082] (2),

[0083] In Figure 1 , VM+, VM-, VR1, VR2 represent circuit ports, and here they represent the voltage values of the corresponding ports. Specifically, here VM+ and VM- represent the voltages of the two ends of the memristor emulator with respect to ground, and VR1 and VR2 represent the voltages of the outputs of the two controlled voltage sources with respect to ground. In Figure 1 , R1, R7 represent the resistances of circuit elements, and here they represent the specific resistance values of the corresponding resistors.

[0084] Therefore:

[0085] (3),

[0086] By transforming Equation (2), the relationship between the voltages of the outputs of the two controlled voltage sources VR1 and VR2 with respect to ground, the voltages VM+ and VM- across the memristor emulator, and the current resistance M of the memristor emulator is calculated.

[0087] Obviously is a duplicate item and can be implemented using a four-quadrant multiplier based on 444.

[0088] Similarly, for a magnetically controlled (voltage-controlled) memristor emulator, its general expression is:

[0089] (4),

[0090] where h is a function describing the dynamic change of the internal state variable. W(S, I) is a function representing the variation law of the resistance value of the memristor emulator with the state variable S and the current I. This function describes the impedance characteristics of the memristor emulator. Specifically, W represents the conductance of the memristor emulator, and its change reflects the historical behavior of the memristor emulator, which is the accumulation effect of magnetic flux here.

[0091] As Figure 1 shown, when constructed with an equivalent circuit, from the consistency and directionality of the current, there is:

[0092] (5),

[0093] In Figure 1 , VM+, VM-, VR1, VR2 represent circuit ports, representing the voltage values of the corresponding ports here. Specifically, VM+ and VM- here represent the voltages of both ends of the memristor emulator with respect to ground, and VR1 and VR2 represent the voltages of the outputs of two controlled voltage sources with respect to ground. In Figure 1 , R1, R7 represent circuit element resistors, representing the specific resistance values of the corresponding resistors here.

[0094] Therefore:

[0095] (6),

[0096] By transforming Equation (5), the relationship between the voltages of the outputs of the two controlled voltage sources VR1 and VR2 with respect to ground and the voltages VM+ and VM- at both ends of the memristor emulator and the current memductance W of the memristor emulator is calculated.

[0097] Obviously is a duplicate item and can be implemented using a four-quadrant multiplier (444FQ) based on 444.

[0098] As Figure 1 shown, operational amplifiers U1, U2, U3, U4, U5, U6, U7 complete the calculation of the controlled voltage sources VR1 and VR2, and operational amplifier U8 converts the differential voltage into a single-ended voltage for use by other modules. Component U 13The four-quadrant multiplier based on 444 realizes the operation of repeated items in the derivation process. For the charge-controlled (current-controlled) memristor emulator, the input terminal X of the four-quadrant multiplier based on 444 is connected to VM + −VM - , the input terminal Y is connected to the memristor function M(S,I), and the input terminal Z is connected to the unit voltage 1V; for the magnetically controlled (voltage-controlled) memristor emulator, the input terminal X of the four-quadrant multiplier based on 444 is connected to VM+−VM- (the + in VM+ is not an operator, but part of the name), the input terminal Y is connected to the memristor function W(S,I), and the input terminal Z is connected to the unit voltage 1V.

[0099] The operation of the memristor function M (S, I) or memristor function W (S, V) of the memristor simulator can be freely designed. Here, the following specific two-terminal memristor simulator is established:

[0100] (7),

[0101] This model describes a two-terminal memristor emulator, where the current is related to the voltage through the memristor function W(S,V)=10|S|, which is determined by the absolute value of the state variable S. The state variable S is updated over time according to the change rules of the voltage V and S itself, reflecting the memory effect of the memristor emulator. The behavior of the system is manifested as a nonlinear coupling between current, voltage and state.

[0102] like Figure 1 As shown, component U 12 The four-quadrant multiplier based on 444 realizes the multiplication and division operations in the internal variable derivative of the memristor simulator. 10 The integral operation of the internal variables of the memristor simulator is realized, and the operational amplifier U 11 The calculation of memristor function of memristor simulator is realized.

[0103] The present invention provides a universal two-terminal current output memristor emulator. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A general double - ended current output memristor emulator, characterized in that, It includes a dual-terminal current output module, an operation module, and an integration module; The operation module contains two four-quadrant multipliers based on the 444 circuit; The integration module is used for memristor internal variable control; The four-quadrant multiplier based on the 444 circuit includes four improved TGA-SN modules, a 444 circuit core, and a gate circuit; The dual - end current output module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 , an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , a fourteenth resistor R 14 , a fifteenth resistor R 15 , a sixteenth resistor R 16 , a seventeenth resistor R 17 , a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8; One end of the first resistor R1 is the equivalent output port VM+ of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR1 of the third operational amplifier U3; Both ends of the second resistor R2 are respectively connected to the output terminal V+ of the first operational amplifier U1 and the inverting input terminal of the second operational amplifier U2; Both ends of the third resistor R3 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the second operational amplifier U2; Both ends of the fourth resistor R4 are respectively connected to the output terminal VI of the thirteenth component U of the operation module including two four-quadrant multipliers based on the 444 circuit and the inverting input terminal of the third operational amplifier U3; 13 and the non-inverting input terminal of the third operational amplifier U3 is connected to the output terminal of the first resistor R1; Both ends of the fifth resistor R5 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the third operational amplifier U3; Both ends of the sixth resistor R6 are respectively connected to the output terminal VR1 of the third operational amplifier U3 and the inverting input terminal of the third operational amplifier U3; One end of the seventh resistor R7 is the equivalent output port VM- of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR2 of the operational amplifier U6; Both ends of the eighth resistor R8 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the fifth operational amplifier U5; Both ends of the ninth resistor R9 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the fifth operational amplifier U5; The tenth resistor R 10 is connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the sixth operational amplifier U6 at both ends respectively; The eleventh resistor R 11 is connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the sixth operational amplifier U6 at both ends respectively; The twelfth resistor R 12 is respectively connected to the output terminal VR2 of the sixth operational amplifier U6 and the inverting input terminal of the sixth operational amplifier U6 at both ends; The thirteenth resistor R 13 is respectively connected at both ends to the output terminal VI of the thirteenth element U 13 of an operation module including two four-quadrant multipliers based on 444 circuits and the inverting input terminal of the seventh operational amplifier U7; The fourteenth resistor R 14 is respectively connected between the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the seventh operational amplifier U7; The fifteenth resistor R 15 is respectively connected at both ends to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the eighth operational amplifier U8; The sixteenth resistor R 16 is connected at both ends to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the eighth operational amplifier U8 respectively; The seventeenth resistor R 17 is respectively connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the eighth operational amplifier U8 at both ends; The output terminal of the first operational amplifier U1 is connected to the inverting input terminal; The output terminal of the fourth operational amplifier U4 is connected to the inverting input terminal; The non-inverting input terminals of the operational amplifiers U2, U3, U5, U6, U7, and U8 are grounded.

2. The general dual-terminal current output memristor emulator according to claim 1, wherein The operation module includes the eighteenth resistor R 18 , the nineteenth resistor R 19 , the ninth operational amplifier U9, the twelfth component U 12 , the thirteenth component U 13 , where the twelfth component U 12 , the thirteenth component U 13 is a four-quadrant multiplier based on a 444 circuit.

3. The general dual-terminal current output memristor emulator according to claim 2, characterized in that, The eighteenth resistor R 18 is connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the ninth operational amplifier U9 of the dual-terminal current output module at both ends respectively; The nineteenth resistor R 19 is connected to the output terminal and the inverting input terminal of the ninth operational amplifier U9 at both ends respectively; The twelfth element U 12 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U8 of the dual-terminal current output module, its input terminal Y connected to the output terminal z of the tenth operational amplifier U 10 of the integration module for memristor internal variable control, and its input terminal Z connected to the output terminal of the ninth operational amplifier U9; The thirteenth element U 13 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U8 of the dual-terminal current output module, its input terminal Y supplied with a +1V voltage by an independent power supply, and its input terminal Z connected to the cathode of the first diode D1 of the integration module for controlling the internal variables of the memristor; The non-inverting input terminal of the operational amplifier U9 is grounded.

4. A general double-ended current output memristor emulator according to claim 3, characterized in that, The integration module includes the twentieth resistor R 20 , the twenty-first resistor R 21 , the twenty-second resistor R 22 , the twenty-third resistor R 23 , the first capacitor C1, the first diode D1, the tenth operational amplifier U 10 , the eleventh operational amplifier U 11 .

5. A general double-terminal current output memristor emulator according to claim 4, characterized in that, The twentieth resistor R 20 is respectively connected at both ends to the output terminal of the twelfth component U 12 of an operation module including two four-quadrant multipliers based on 444 circuits 10 and the inverting input terminal of the tenth operational amplifier U The twenty-first resistor R 21 is respectively connected at both ends to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; The twenty-second resistor R 22 is respectively connected at both ends to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the eleventh operational amplifier U 11 ; The twenty-third resistor R 23 is connected to the cathode of the first diode D1 and the inverting input terminal of the eleventh operational amplifier U 11 at both ends respectively; Both ends of the first capacitor C1 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; The anode of the first diode D1 is connected to the output terminal of the eleventh operational amplifier U 11 and the cathode is connected to the input terminal Z of the thirteenth component U 13 of the operational module including two four-quadrant multipliers based on the 444 circuit; Operational amplifier U 10 , U 11 's non-inverting input terminal is grounded.

6. A general double-ended current output memristor emulator according to claim 5, characterized in that, The general dual-terminal current output memristor emulator is a combination of two single-terminal floating-ground memristor emulators.

7. A general dual-terminal current output memristor emulator according to claim 6, characterized in that, When constructing the general dual-terminal current output memristor emulator with an equivalent circuit, the following formula is obtained: （1）， Where, V represents the voltage across the memristor emulator, I represents the current flowing through the memristor emulator, VM+ and VM- represent the voltage values of both ends of the memristor emulator with respect to ground, VR1 and VR2 represent the voltage values of the outputs of two controlled voltage sources with respect to ground, and R1 and R7 represent the resistance values of the resistors.

8. A general double - ended current output memristor emulator according to claim 7, characterized in that, By transforming formula (1), the relationship between calculating VR1 and VR2 and the voltage values of both ends of the memristor emulator VM+ and VM- with respect to ground and the current memductance of the memristor emulator is obtained: （2）， Where W (S, V) represents the memductance function of the memristor emulator, and S is the state variable.

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