Source driver, display driving device, and display device including the same

Abstract

The invention provides a source driver, a display driving device, and a display device including the display driving device. A display driving apparatus according to one or more example embodiments includes a source driver configured to output a data signal obtained by amplifying an input signal to a source line in a first period, and receive a detection signal from the source line in a second period different from the first period, and outputs a comparison result signal based on a comparison between the detection signal and the input signal; and a driving controller configured to determine a characteristic of the source line based on a timing at which a level of the comparison result signal transitions in the second period.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0167884, filed with the Korean Intellectual Property Office on November 28, 2023, and Korean Patent Application No. 10 - 2024 - 0060020, filed with the Korean Intellectual Property Office on May 7, 2024, the entire disclosures of which are incorporated herein by reference. Technical field

[0003] One or more example embodiments of the present disclosure relate to a source driver, a display driving device, and a display device including the display driving device. Background art

[0004] Generally, a display panel displays an image and provides various visual information to a user. The display panel includes a plurality of pixels, and each of the plurality of pixels emits light of a predetermined brightness to display an image. A display driver integrated circuit (DDI) may be used to drive the plurality of pixels.

[0005] Since the characteristics of the display panel vary depending on the process distribution, the DDI that supplies a plurality of signals to the display panel is driven with high power to overcome the characteristic differences between the display panels. Summary of the invention

[0006] One or more example embodiments of the present disclosure provide a source driver, a display driving device, and a display device including the display driving device, in which the characteristics of a pixel and / or a display panel can be determined without using a separate amplifier.

[0007] One or more example embodiments of the present disclosure provide a source driver, a display driving device, and a display device including the display driving device, in which defects in a display panel can be detected.

[0008] According to an aspect of an example embodiment of the present disclosure, there is provided a display driving device. The display driving device includes: a source driver configured to output a data signal obtained by amplifying an input signal to a source line during a first period, and during a second period different from the first period, receive a detection signal from the source line and output a comparison result signal based on a comparison between the detection signal and the input signal; and a driving controller configured to determine the characteristics of the source line based on the timing at which the level of the comparison result signal changes during the second period.

[0009] According to an aspect of an exemplary embodiment of the present disclosure, a display device is provided. The display device includes: a panel including a plurality of pixels and a plurality of source lines connected to the plurality of pixels; and a display driving circuit including an amplifier region and a driving controller, the amplifier region including an amplifier and configured to transmit a plurality of data signals to the plurality of source lines during a first period, and receive a plurality of detection signals from the plurality of source lines during a second period different from the first period, and output a plurality of comparison result signals by comparing the plurality of detection signals with an input signal, and the driving controller is configured to determine characteristics of the plurality of source lines based on the plurality of comparison result signals, respectively.

[0010] According to an aspect of an exemplary embodiment of the present disclosure, a source driver is provided. The source driver includes: a digital-to-analog converter configured to output an input signal based on input data; an amplifier region including an amplifier, the amplifier region being configured to amplify the input signal to output a data signal during a first period, and compare the input signal with a detection signal received from a source line to output a comparison result signal during a second period after the first period; and a switching circuit configured to selectively connect an output terminal of the amplifier region to the source line during the first period and selectively disconnect the output terminal of the amplifier region from the source line during the second period based on a level of a first selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of certain exemplary embodiments of the present disclosure may become more apparent from the following description when considered in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is an exemplary block diagram of a display device according to one or more exemplary embodiments.

[0013] Figure 2 is a block diagram showing a part of a panel and a source driver according to one or more exemplary embodiments.

[0014] Figure 3 and Figure 4 is a view illustratively showing a part of a panel and a source driver according to one or more exemplary embodiments.

[0015] Figure 5 is a timing diagram of an operation of detecting characteristics of a source line by a driving controller according to one or more exemplary embodiments.

[0016] Figure 6 and Figure 7 is a timing diagram of an operation of detecting a defect in a source line by a driving controller according to one or more exemplary embodiments.

[0017] Figure 8 It is a timing diagram of the operation of detecting a defect in a source line by a driving controller according to one or more exemplary embodiments.

[0018] Figure 9 It is a block diagram showing a part of a panel and a source driver according to one or more exemplary embodiments.

[0019] Figure 10 and Figure 11 It is a view illustratively showing a part of a panel and a source driver according to one or more exemplary embodiments.

[0020] Figure 12 It is a timing diagram of the operation of determining the characteristics of a source line by a driving controller according to one or more exemplary embodiments.

[0021] Figure 13 It is a block diagram showing the connection relationship between multiple source lines of a panel and a source driver according to one or more exemplary embodiments.

[0022] Figure 14 It is a view explaining a display system according to one or more exemplary embodiments.

[0023] Figure 15 It is a view explaining a display system according to one or more exemplary embodiments. Detailed Description

[0024] The following description with reference to the accompanying drawings helps to comprehensively understand the exemplary embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be merely exemplary. Thus, those of ordinary skill in the art can recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Additionally, descriptions of well-known functions and structures are omitted for clarity and conciseness. Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. It should be understood that unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an item may include one or more things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include the possible combinations of the items listed together in the corresponding one of the phrases. As used herein, terms such as "first (1st)" and "second (2nd)" or "first (first)" and "second (second)" may be used simply to distinguish the corresponding components from another component and do not otherwise limit the components (e.g., in terms of importance or order). It should be understood that if an element (e.g., a first element) is referred to as "coupled to", "coupled with", "connected to", or "connected with" another element (e.g., a second element), with or without the terms "operably" or "communicatively", it means that the element can be coupled to the other element directly (e.g., wired), wirelessly, or via a third element. References throughout this disclosure to "one embodiment", "an embodiment", "an exemplary embodiment", or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Thus, the phrases "in one embodiment", "in an embodiment", "in an exemplary embodiment", and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. As shown in the drawings, the embodiments herein can be described and illustrated in terms of blocks that perform one or more of the described functions. These blocks (which may be referred to herein as units or modules, etc., or by names such as devices, logics, circuits, counters, comparators, generators, converters, etc.) can be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and can also be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein). Hereinafter, various embodiments of the present disclosure are described with reference to the drawings.

[0025] Figure 1is an example block diagram of a display device according to one or more example embodiments.

[0026] Referring Figure 1 , a display device 100 according to one or more example embodiments may include a driving circuit 110 and a panel 120. In some embodiments, the display device 100 may further include a power supply circuit, such as a DC-to-DC converter, that supplies driving voltages to the driving circuit 110 and the panel 120. A display driving device according to one or more example embodiments may correspond to the driving circuit 110.

[0027] The panel 120 may include a display area 121 that displays an image and a gate driver 122 that outputs driving signals to the display area 121. In some embodiments, the gate driver 122 may be included in the driving circuit 110. In an embodiment, source lines SL, gate lines GL, and pixels PX may be positioned in the display area 121.

[0028] In the display area 121, a plurality of pixels PX may be positioned to display an image. The pixel PX may be connected to a corresponding one of the plurality of source lines SL and a corresponding one of the plurality of gate lines GL. When a gate signal is supplied to the gate line GL, the pixel PX may receive a data signal input through the source line SL. The pixel PX may emit light of a predetermined luminance corresponding to the input data signal. The plurality of pixels PX may display an image as one frame unit.

[0029] When the display device 100 is an organic light emitting display device, each pixel PX may include a plurality of transistors including a driving transistor and an organic light emitting diode. The driving transistor included in the pixel PX may supply a current corresponding to the data signal to the organic light emitting diode, and based on this, the organic light emitting diode may emit light of a predetermined luminance. When the display device 100 is a liquid crystal display device, each pixel PX may also include a switching transistor and a liquid crystal capacitor. The pixel PX may control the light supplied to the outside by controlling the transmittance of the liquid crystal in response to the data signal.

[0030] In Figure 1 , the pixel PX is shown connected to one source line SL and one gate line GL, but the connection structure of the signal lines of the pixel PX of a display device according to one or more example embodiments is not limited thereto. For example, various signal lines may be additionally connected according to the circuit structure of the pixel PX. In an embodiment, the pixel PX may be implemented in various currently known forms.

[0031] The gate driver 122 can provide a plurality of gate signals G1, G2, …, Gh. The plurality of gate signals G1, G2, …, Gh can be pulse signals having an enable level and a disable level. The plurality of gate signals G1, G2, …, Gh can be respectively applied to a plurality of gate lines GL. When a gate signal of the enable level is applied to the gate line GL connected to the pixel PX, the data signal applied to the source line SL connected to the pixel PX can be sent to the pixel PX. The gate driver 122 can provide the plurality of gate signals G1, G2, …, Gh during a plurality of horizontal periods. One frame can include a plurality of horizontal periods.

[0032] In Figure 1 it, the gate driver 122 is shown to be implemented on the same substrate as the panel 120 and positioned at the periphery of the panel 120, but the gate driver 122 can be implemented as a separate semiconductor die, chip or module and connected to the panel 120. Additionally, a part of the gate driver 122 can be positioned in the panel 120, and the remaining part can be included in the driving circuit 110.

[0033] The driving circuit 110 can include a source driver 111 and a driving controller 113. Some or all of the source driver 111 and the driving controller 113 can be implemented as the same semiconductor die, chip or module, or can be implemented as separate semiconductor dies, chips or modules. In some embodiments, the source driver 111 can be implemented on the same substrate as the panel 120. In this case, the source driver 111 can be placed at the periphery of the panel 120.

[0034] The source driver 111 can receive data DATA in the form of a digital signal from the driving controller 113 and convert the data DATA into data signals S1, S2, ..., Sk in the form of an analog signal. Here, the data DATA can include gray-scale information corresponding to each pixel PX for displaying an image corresponding to the image signal IS on the panel 120. The source driver 111 can send the plurality of data signals S1, S2, …, Sk to the panel 120 according to the source driver control signal CONT2 provided from the driving controller 113. The source driver 111 can also be referred to as a data driver.

[0035] In an embodiment, the source driver 111 can receive detection signals R1, R2, ..., Rk from a plurality of source lines SL. The source driver 111 can sense the potentials of the plurality of source lines SL. The source driver 111 can compare the potentials of the detection signals R1, R2, …, Rk with a reference voltage. The source driver 111 can provide the comparison result of each of the detection signals R1, R2, …, Rk with the reference voltage to the driving controller 113. The source driver 111 can operate as a receiver.

[0036] In an embodiment, the source driver 111 may divide time to output data signals S1, S2, …, Sk or receive detection signals R1, R2, …, Rk. In other words, the source driver 111 may output data signals S1, S2, …, Sk during a first time period and receive detection signals R1, R2, …, Rk during a second time period other than the first time period. For example, the source driver 111 may receive detection signals R1, R2, …, Rk in a first portion of a vertical blanking period VBLANK within one frame and output data signals S1, S2, …, Sk in a second portion other than the first portion within one frame. The source driver 111 may receive detection signals R1, R2, …, Rk in a first portion of a horizontal blanking period HBLANK within one horizontal period and output data signals S1, S2, …, Sk in a second portion other than the first portion within one horizontal period. The source driver 111 may output data signals S1, S2, …, Sk in a first portion of an active period within one horizontal period and receive detection signals R1, R2, …, Rk in a second portion other than the first portion within one horizontal period.

[0037] The source driver 111 may be electrically connected to a plurality of source lines SL.

[0038] The source driver 111 may send a plurality of data signals S1, S2, …, Sk to the plurality of electrically connected source lines SL. The source driver 111 may receive a plurality of detection signals R1, R2, …, Rk from the plurality of electrically connected source lines SL.

[0039] The source driver 111 may include an amplifier region 112. In a first mode (FIRST MODE) in which the source driver 111 outputs a plurality of data signals S1, S2, …, Sk, an output terminal and an input terminal of an amplifier region 112a included in the amplifier region 112 may be electrically connected to a corresponding source line SL. The amplifier region 112 may send a corresponding data signal Si among the plurality of data signals S1, S2, …, Sk to the corresponding source line SL.

[0040] In the FIRST MODE, the amplifier region 112 may operate as a unity-gain amplifier. In the SECOND MODE in which the source driver 111 receives a plurality of detection signals R1, R2, …, Rk, an output terminal of the amplifier region 112b included in the amplifier region 112 may be electrically disconnected from the corresponding source line SL. An input terminal of the amplifier region 112b may receive the corresponding detection signal Ri among the plurality of detection signals R1, R2, …, Rk from the corresponding source line SL. The amplifier region 112 may output a comparison result signal Voi. The amplifier region 112 may output the comparison result signal Voi to the driving controller 113. In the SECOND MODE, the amplifier region 112 may operate as a comparator.

[0041] The driving controller 113 may receive an image signal IS and a driving control signal CTRL from a host device and control the gate driver 122 and the source driver 111 based thereon. Here, the host device may be a computing device or a system that controls the display device 100 externally to display a desired image (e.g., an image desired by a user) on the panel 120. The driving control signal CTRL provided from the host device may include control instructions and predetermined data for controlling the gate driver 122 and the source driver 111. The driving controller 113 may control the gate driver 122 and the source driver 111 based on the driving control signal CTRL. For example, the driving control signal CTRL may include a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a main clock signal MCLK, and a data enable signal DE. The driving controller 113 may generate data DATA by dividing the image data IS into a frame unit based on the vertical synchronization signal VSYNC and dividing the image data IS for each gate line GL based on the horizontal synchronization signal HSYNC. For example, the driving controller 113 may send a gate driver control signal CONT1 and a source driver control signal CONT2 to the gate driver 122 and the source driver 111, respectively, to perform control for synchronizing the operations of the source driver 111 and the gate driver 122. When the source driver 111 receives a plurality of detection signals R1, R2, …, Rk, the driving controller 113 may control the source driver 111 such that the source driver 111 outputs a comparison result signal VOUT to the driving controller 113. The driving controller 113 may control the gate driver 122 and the source driver 111 based on self-generated control instructions separate from or in addition to the driving control signal CTRL received from the host device.

[0042] In an embodiment, the driving controller 113 may determine the characteristics of the source line SL based on the comparison result signal VOUT. That is, the driving controller 113 may detect the occurrence of a load on the source line SL and / or a short circuit on the source line SL by using the comparison result signal VOUT. Specifically, the driving controller 113 may determine the load of the source line SL based on the level of the comparison result signal VOUT. For example, the driving controller 113 may determine the magnitude of the load on the source line SL based on the timing of the level transition of the comparison result signal VOUT. In some embodiments, the driving controller 113 may determine the load on the source line SL and / or the occurrence of a short circuit based on the value of the data DATA provided by the driving controller 113 to the source driver at the timing of the level transition of the comparison result signal VOUT. In some embodiments, the driving controller 113 may count the timing of the level transition of the comparison result signal VOUT and determine the load on the source line SL and / or the occurrence of a short circuit in the source line SL based on the counting result.

[0043] The source driver 111 of one or more exemplary embodiments may detect the occurrence of a load on the source line SL and / or a short circuit in the source line SL. The source driver 111 of one or more exemplary embodiments may transmit a data signal to the source line SL or receive a detection signal from the source line SL by using one amplifier region 112. Accordingly, in the driving circuit 110 according to one or more exemplary embodiments, the area occupied by the source driver 111 may be reduced, and the size of the driving circuit 110 may be reduced. In addition, in the driving circuit 110 according to one or more exemplary embodiments, since the load of the source line may be determined, the operating electric power of the source driver 111 may be reduced based on the load of the source line.

[0044] Figure 2 is a block diagram showing a part of a panel and a source driver according to one or more exemplary embodiments.

[0045] Reference Figure 2 , the source driver (SOURCE DRIVER) includes an amplifier region 201, a switch circuit 202, and a digital-to-analog converter (DAC) 203. The source driver (SOURCE DRIVER) may be electrically connected and / or directly connected to the source line SLi of the panel (PANEL). The source driver (SOURCE DRIVER) may be Figure 1 the driving circuit 110 or the source driver 111 of Figure 2 . In Figure 1 , the source driver (SOURCE DRIVER) is described as including a switch circuit 202, but the switch circuit 202 may be implemented on the same substrate as the panel (e.g.,

[0046] The amplifier region 201 can be connected to the switch circuit 202 and the DAC 203. The amplifier region 201 can receive the input signal PSi from the DAC 203 and output the data signal Si. The amplifier region 201 can amplify the input signal PSi received from the DAC 203 to generate the data signal Si, and send the generated data signal Si to the panel PANEL through the source line Si. In some embodiments, the amplifier region 201 can operate as a comparator. When the amplifier region 201 operates as a comparator, the amplifier region 201 can receive the detection signal Ri from the source line SLi and the input signal PSi from the DAC 203. The amplifier region 201 can compare the detection signal Ri and the input signal PSi and output the output signal VOi to the output line OLi connected to the drive controller (e.g., Figure 1 the 113 in

[0047] The switch circuit 202 can be connected to the output terminal of the amplifier region 201. The switch circuit 202 can electrically connect the source line SLi to the output terminal of the amplifier region 201 or electrically disconnect it from the output terminal of the amplifier region 201 based on the level of the selection signal SEL. For example, when the selection signal SEL is at the logic level “H”, the switch circuit 202 can electrically connect the output terminal of the amplifier region 201 to the source line SLi, and when the selection signal SEL is at the logic level “L”, the switch circuit 202 can disconnect the electrical connection between the output terminal of the amplifier region 201 and the source line SLi.

[0048] The DAC 203 can receive the data DATA and convert the data DATA from a digital signal to an analog signal. For example, the DAC 203 can convert the data DATA in the form of a digital signal to an analog signal by matching the plurality of gamma voltages VG1 to VGp received from a gamma voltage generator (not shown) with the data DATA. The converted analog signal can be sent to the amplifier region 201 and provided as the input signal PSi to the amplifier provided in the amplifier region 201.

[0049] The source line SLi can have a load 210. For example, the source line SLi can have a capacitive load CP. Additionally, the source line SLi can have a resistive load and / or an inductive load. The magnitude of the load of the source line SLi can be different from the magnitude of the loads of other source lines. The amplifier region 201 can output a signal corresponding to the magnitude of the load of the source line SLi by comparing the detection signal Ri and the input signal PSi.

[0050] The source line SLi can be short-circuited with the wirings that supply the power supply voltages ELVSS and ELVDD 220. Additionally, the source line SLi can be short-circuited with another adjacent source line SL(i + 1) 230. Additionally, the source line SLi can be short-circuited with at least one of the wirings that apply various voltages to signals. The amplifier region 201 can output a signal based on the short circuit of the source line SLi by comparing the detection signal Ri and the input signal PSi.

[0051] Hereinafter, reference will be made to Figures 3 to 8 describe a method for detecting the occurrence of a short circuit in the load of the source line and / or the source line SLi.

[0052] Figure 3 and Figure 4 are views illustratively showing a part of a panel and a source driver according to one or more example embodiments.

[0053] Reference Figure 3 , the source driver (SOURCE DRIVER) can output the data signal Si to the panel PANEL. The source driver (SOURCE DRIVER) can include an amplifier 301 and a switch circuit 302.

[0054] The output terminal of the amplifier 301 can be connected to the output line OLi. The output terminal of the amplifier 301 can be connected to the source line SLi through the switch circuit 302. The input terminal IN1 of the amplifier 301 can be connected to the source line SLi, and the input terminal IN2 of the amplifier 301 can receive the input signal PSi from the DAC. The amplifier 301 can amplify the input signal PSi and output the data signal Si to the output terminal of the amplifier 301.

[0055] When the selection signal SEL is at the logic level “H”, the switch circuit 302 can electrically connect the output terminal of the amplifier 301 to the source line SLi. The data signal Si from the output terminal of the amplifier 301 can be sent to the source line SLi through the switch circuit 302.

[0056] Reference Figure 4 , the source driver (SOURCE DRIVER) can output the comparison result signal VOi to the driving controller (DRIVING CONTROLLER).

[0057] The output terminal of the amplifier 401 may be connected to the output line OLi. The output terminal of the amplifier 401 may not be connected to the source line SLi. The input terminal IN1 of the amplifier 401 may be connected to the source line SLi, and the input terminal IN2 of the amplifier 401 may receive the input signal PSi from the DAC. The amplifier 401 may compare the detection signal Ri from the source line SLi with the input signal PSi and output the comparison result signal Voi to the output terminal of the amplifier 401.

[0058] Figure 5 is a timing diagram of the operation of a drive controller for determining the characteristics of a source line according to one or more example embodiments.

[0059] Specifically, Figure 5 shows a timing diagram of the operation of determining the magnitude of the load of the source line SLi according to one or more example embodiments. Refer to Figures 3 to 5 , at time t0, the input signal PSi may be input to the input terminal IN2 of the amplifier 301. In Figure 5 , V_IN2 indicates the voltage level of the input terminal IN2. The period from t0 to t1 may be a pre-charge period P_PRE1. During the pre-charge period P_PRE1, the select signal SEL may have a logic level "H". The amplifier 301 may amplify the input signal PSi on the source line SLi and output the amplified input signal PSi as the data signal Si. That is, during the pre-charge period P_PRE1, the amplifier 301 may output the data signal Si that charges the source line SLi.

[0060] In some embodiments, the pre-charge period P_PRE1 may be a period of 1H (one horizontal cycle) or less. The voltage of the source line SLi may be changed by the data signal Si output from the amplifier 301. Depending on the magnitude of the load of the source line SLi, the voltage of the source line SLi may change rapidly (e.g., L1) or slowly (e.g., L2 or L3). For example, when the load on the source line SLi is relatively large, the voltage of the source line SLi may change slowly (e.g., L2 or L3). When the load on the source line SLi is relatively small, the voltage on the source line SLi may change rapidly (e.g., L1). The pre-charge period P_PRE1 may be determined based on at least one of the size of the panel PANEL, the length of the source line SLi, or the number of pixels connected to the source line SLi.

[0061] At timing t1, the selection signal SEL can change from the logic level "H" to the logic level "L". The amplifier 401 can output the signal VOi to the output line OLi based on the comparison between the input signal PSi and the detection signal Ri of the source line SLi. The period from t1 to t5 can be the sensing period P_SEN1. During the sensing period P_SEN1, the level of the input signal PSi can change within the range of a plurality of gamma voltages VG1 to VGp. The sensing period P_SEN1 can include a plurality of unit sensing periods P_SU. The input signal PSi can change for each of the plurality of unit sensing periods P_SU. For example, the input signal PSi applied to the input terminal IN2 of the amplifier 401 in the first unit sensing period within the sensing period P_SEN1 and the input signal PSi applied to the input terminal IN2 of the amplifier 401 in the second unit sensing period within the sensing period P_SEN1 can be different. The input signal PSi can change as the data DATA applied to the DAC (e.g., Figure 2 203 in Figure 1 113) changes. The drive controller (e.g., Figure 1 113) can change the data DATA, and the DAC 203 can output the input signal PSi corresponding to the changed data DATA. The drive controller 113 can change the data DATA by using various sorting methods such as binary search. Then, the voltage level of the input signal PSi can also be changed by using various sorting methods such as binary search. For example, when the voltage level of the input signal PSi within the first unit sensing period is a level representing 128 gray levels, the voltage level of the input signal PSi within the second unit sensing period after the first unit sensing period can be a level representing 64 gray levels. Another example, as Figure 5 shows, when the voltage level of the input signal PSi within the first unit sensing period is a level representing 0 gray levels, the voltage level of the input signal PSi within the second unit sensing period after the first unit sensing period can be a level representing 1 gray level.

[0062] Within the unit sensing period P_SU, the amplifier 401 can compare the signals applied to the input terminals IN1 and IN2 and output the comparison result as the comparison result signal VOi. The drive controller 113 can determine the magnitude of the load of the source line SLi based on the data DATA applied to the DAC 203 when the level of the comparison result signal VOi changes.

[0063] During the period from t1 to t2, when the load of the source line SLi ranges from the first amplitude L1 to the third amplitude L3, the level of the input signal PSi is less than the level of the detection signal Ri output from the source line SLi, and the level of the comparison result signal Voi can be at the logic "L" level. At timing t2, the level of the input signal PSi is greater than the level of the detection signal Ri output from the source line SLi with a load of the third amplitude L3, and the level of the comparison result signal Voi of the source line SLi with a load of the third amplitude L3 can change from the logic "L" level to the logic "H" level. Based on the data DATA applied by the drive controller 113 to the DAC 203 when the level of the comparison result signal Voi of the source line SLi changes from the logic "L" level to the logic "H" level, the drive controller 113 can determine the amplitude of the load of the source line SLi. At this time, the amplitude of the load of the source line SLi can be related to the data DATA and can correspond to the third amplitude L3.

[0064] During the period from t2 to t3, when the load of the source line SLi ranges from the first amplitude L1 to the second amplitude L2, the level of the input signal PSi is less than the level of the detection signal Ri output from the source line SLi, and the level of the comparison result signal Voi can be at the logic "L" level. At timing t3, the level of the input signal PSi is greater than the level of the detection signal Ri output from the source line SLi with a load of the second amplitude L2, and the level of the comparison result signal Voi of the source line SLi with a load of the second amplitude L2 can change from the logic "L" level to the logic "H" level. Based on the data DATA applied by the drive controller 113 to the DAC 203 when the level of the comparison result signal Voi of the source line SLi changes from the logic "L" level to the logic "H" level, the drive controller 113 can determine the amplitude of the load of the source line SLi. At this time, the amplitude of the load of the source line SLi is related to the data DATA and can correspond to the second amplitude L2.

[0065] During the period from t3 to t4, when the load of the source line SLi is at the first amplitude L1, the level of the input signal PSi is less than the level of the detection signal Ri output from the source line SLi, and the level of the comparison result signal Voi can be at the logic "L" level. At timing t4, the level of the input signal PSi is greater than the level of the detection signal Ri output from the source line SLi with a load of the first amplitude L1, and the level of the comparison result signal Voi of the source line SLi with a load of the first amplitude L1 can change from the logic "L" level to the logic "H" level. Based on the data DATA applied to the DAC 203 by the drive controller 113 when the level of the comparison result signal Voi of the source line SLi changes from the logic "L" level to the logic "H" level, the drive controller 113 can determine the amplitude of the load of the source line SLi. At this time, the amplitude of the load of the source line SLi can be related to the data DATA and can correspond to the first amplitude L1.

[0066] Figure 6 and Figure 7 is a timing diagram of an operation for a drive controller to determine a defect in a source line according to one or more exemplary embodiments.

[0067] Specifically, Figure 6 shows a timing diagram of an operation for determining a short circuit between the source line SLi and a wiring that provides a first power supply voltage ELVSS. Figure 7 shows a timing diagram of an operation for determining a short circuit between the source line SLi and a wiring that provides a second power supply voltage ELVDD.

[0068] Refer to Figure 3 、 Figure 4 and Figure 6 , at timing t00, the input signal PSi can be input to the input terminal IN2 of the amplifier 301. In Figure 6 , V_IN2 indicates the voltage level of the input terminal IN2. The period from t00 to t01 can be a pre-charge period P_PRE2. During the pre-charge period P_PRE2, the select signal SEL can have a logic level "H". The amplifier 301 can amplify the input signal PSi to output it as a data signal Si on the source line SLi. That is, during the pre-charge period P_PRE2, the amplifier 301 can output the data signal Si that charges the source line SLi. In some embodiments, the data signal Si can be the highest voltage V_TOP among a plurality of gamma voltages VG1, VG2,..., VGp.

[0069] In some embodiments, the pre-charge period P_PRE2 may be 2 H periods (two horizontal periods) or longer. The pre-charge period P_PRE2 may be long enough for the voltage of the source line SLi to reach the voltage V_TOP of the data signal Si. During the pre-charge period P_PRE2, the voltage of the source line SLi corresponding to the amplitude L1 of the load may reach the voltage V_TOP.

[0070] At timing t01, the select signal SEL may change from the logic level “H” to the logic level “L”. The amplifier 401 may output the signal VOi to the output line OLi based on the comparison between the input signal PSi and the detection signal Ri of the source line SLi. The period from t01 to t03 may be the sensing period P_SEN2. During the sensing period P_SEN2, the level of the input signal PSi may change within the range of a plurality of gamma voltages VG1 to VGp. In some embodiments, the level of the input signal PSi during the sensing period P_SEN2 may decrease from the voltage V_TOP to the voltage V_BOT, where the voltage V_BOT is the lowest voltage among the plurality of gamma voltages VG1, VG2, …, VGp. Similar to Figure 5 the sensing period P_SEN1 in Figure 5 , the sensing period P_SEN2 may include a plurality of unit sensing periods P_SU. The description of the sensing period P_SEN2 may be the same as or similar to the description of the sensing period P_SEN1 in

[0071] During the period from t01 to t02, since the level of the input signal PSi is less than the level of the detection signal Ri output from the source line SLi, the level of the comparison result signal VOi may be the logic “L” level. At timing t02, since the level of the input signal PSi becomes greater than the level of the detection signal Ri output from the source line SLi, the level of the comparison result signal VOi of the source line SLi may change from the logic “L” level to the logic “H” level. Based on the data DATA applied to the DAC 203 by the drive controller 113 when the level of the comparison result signal VOi of the source line SLi changes from the logic “L” level to the logic “H” level, the drive controller 113 may determine that the source line SLi is short-circuited to the wiring providing the first power supply voltage ELVSS. For example, when the voltage level of the input signal PSi at timing t02 has a relatively small difference from the level of the first power supply voltage ELVSS, the drive controller 113 may determine that a short circuit has occurred in the wiring of the source line SLi and the wiring providing the first power supply voltage ELVSS. If the source line SLi is not short-circuited to the wiring providing the first power supply voltage ELVSS, the voltage level of the input signal PSi will have a relatively small difference from the level of the voltage V_TOP.

[0072] Refer toFigure 3 , Figure 4 and Figure 7 , at timing t10, the input signal PSi can be input to the input terminal IN2 of the amplifier 301. In Figure 7 , V_IN2 indicates the voltage level of the input terminal IN2. The period from t10 to t11 can be a pre-charge period P_PRE3. During the pre-charge period P_PRE3, the selection signal SEL can have a logic level "H". The amplifier 301 can amplify the input signal PSi on the source line SLi to output it as a data signal Si. That is, during the pre-charge period P_PRE3, the amplifier 301 can output the data signal Si for charging the source line SLi. In some embodiments, the data signal Si can be the lowest voltage V_BOT among a plurality of gamma voltages VG1, VG2, …, VGp.

[0073] In some embodiments, the pre-charge period P_PRE3 can be a period of 2 H cycles or longer. The pre-charge period P_PRE3 can be long enough for the voltage of the source line SLi to reach the voltage V_BOT of the data signal Si. During the pre-charge period P_PRE3, the voltage of the source line SLi corresponding to the amplitude L1 of the load can reach the voltage V_BOT.

[0074] At timing t11, the selection signal SEL can change from the logic level "H" to the logic level "L". The amplifier 401 can output the signal VOi to the output line OLi based on the comparison between the input signal PSi and the detection signal Ri of the source line SLi. The period from t11 to t13 can be a sensing period P_SEN3. During the sensing period P_SEN3, the level of the input signal PSi can change within the range of a plurality of gamma voltages VG1 to VGp. In some embodiments, the level of the input signal PSi during the sensing period P_SEN3 can decrease from the voltage V_TOP to the voltage V_BOT. Similar to Figure 5 the sensing period P_SEN1 in Figure 5 , the sensing period P_SEN3 can include a plurality of unit sensing periods P_SU. The description of the sensing period P_SEN3 can be the same as or similar to the description of the sensing period P_SEN1 in

[0075] During the period from t11 to t12, since the input signal PSi is greater than the detection signal Ri output from the source line SLi, the level of the comparison result signal Voi can have a logic "H" level. At timing t12, since the level of the input signal PSi becomes less than the level of the detection signal Ri output from the source line SLi, the level of the comparison result signal Voi of the source line SLi can change from a logic "H" level to a logic "L" level. Based on the data DATA applied to the DAC 203 by the drive controller 113 when the level of the comparison result signal Voi of the source line SLi changes from a logic "H" level to a logic "L" level, the drive controller 113 can determine that the source line SLi is short-circuited with the wiring that provides the second power supply voltage ELVDD. For example, if the voltage level of the input signal PSi at timing t12 has a relatively small difference from the level of the second power supply voltage ELVDD, the drive controller 113 can determine that the source line SLi is short-circuited with the wiring that provides the second power supply voltage ELVDD. If the source line SLi is not short-circuited with the wiring that provides the second power supply voltage ELVDD, the voltage level of the input signal PSi can have a relatively small difference from the level of the voltage V_BOT.

[0076] Figure 8 is a timing diagram of the operation of a drive controller that determines a defect in a source line according to one or more example embodiments.

[0077] Specifically, Figure 8 shows a timing diagram of the operation of determining a short circuit between the source line SL2 and the adjacent source line SL3.

[0078] Refer to Figure 3 、 Figure 4 and Figure 8 , at timing t20, the input signal PSi can be input to the input terminal IN2 of each amplifier 301 of the source line SL2 and the source line SL3. At Figure 8Among them, V_IN2 indicates the voltage level of the input terminal IN2. The period from t20 to t21 may be a pre-charge period P_PRE4. During the pre-charge period P_PRE4, the select signal SEL may have a logic level "H". The amplifier 301 may amplify the input signals PS2 and PS3 on the corresponding source lines SL2 and SL3, and output the amplified input signals as data signals. That is, during the pre-charge period P_PRE4, the amplifier 301 may output data signals for charging the corresponding source lines SL2 and SL3. In some embodiments, the data signals S2 and S3 applied to two adjacent source lines SL2 and SL3 may be different from each other. For example, the data signal S2 applied to the source line SL2 may be the highest voltage V_TOP among a plurality of gamma voltages VG1, VG2, …, VGp, and the data signal S3 applied to the source line SL3 may be the lowest voltage V_BOT among a plurality of gamma voltages VG1, VG2, …, VGp.

[0079] In some embodiments, the pre-charge period P_PRE4 may be a period of 2 H cycles or longer. The pre-charge period P_PRE4 may be long enough for the voltages of the source lines SL2 and SL3 to reach the voltages V_TOP and V_BOT of the data signals S2 and S3 respectively. During the pre-charge period P_PRE4, the voltage V_SL2 of the source line SL2 may reach the voltage V_TOP, and the voltage V_SL3 of the source line SL3 may reach the voltage V_BOT. When the pre-charge period P_PRE4 ends, the voltages of the source lines SL2 and SL3 may become the same due to a short circuit between the source lines SL2 and SL3. That is, the voltages of the source lines SL2 and SL3 may have a voltage level between the voltage V_TOP and the voltage V_BOT.

[0080] At timing t21, the select signal SEL may change from the logic level "H" to the logic level "L". The amplifier 401 connected to the source line SL2 may output the signal VO2 to the output line OL2 by comparing the input signal PS2 and the detection signal R2 of the source line SL2. The amplifier 401 connected to the source line SL3 may output the signal VO3 to the output line OL3 by comparing the input signal PS3 and the detection signal R3 of the source line SL3. The period from t21 to t24 may be a sensing period P_SEN4. During the sensing period P_SEN4, the levels of the input signals PS2 and PS3 may change within the range of a plurality of gamma voltages VG1 to VGp. In some embodiments, the levels of the input signals PS2 and PS3 may decrease from the voltage V_TOP to the voltage V_BOT during the sensing period P_SEN4. Similar to Figure 5In the sensing period P_SEN1, the sensing period P_SEN4 may include a plurality of unit sensing periods P_SU. The description of the sensing period P_SEN4 may be the same as or similar to the description of the sensing period P_SEN1 in Figure 5 and thus the description thereof is omitted.

[0081] During the period from t21 to t22, since the level of the input signal PS2 is less than the level of the detection signal R2 output from the source line SL2, the level of the comparison result signal VO2 may have a logic "L" level. Since the level of the input signal PS3 is greater than the level of the detection signal R3 output from the source line SL3, the level of the comparison result signal VO3 may have a logic "H" level. At timing t22, since the level of the input signal PS3 is less than the level of the detection signal R3 output from the source line SL3, the level of the comparison result signal VO3 of the source line SL3 may change from the logic "H" level to the logic "L" level. At timing t23, since the level of the input signal PS2 is greater than the level of the detection signal R2 output from the source line SL2, the level of the comparison result signal VO2 of the source line SL2 may change from the logic "L" level to the logic "H" level. Similarly, since the level of the input signal PS3 is greater than the level of the detection signal R3 output from the source line SL3, the level of the comparison result signal VO3 of the source line SL3 may change from the logic "L" level to the logic "H" level.

[0082] That is, at timing t23, since the levels of the comparison result signals VO2 and VO3 of the two source lines SL2 and SL3 have changed, the drive controller 113 may determine that the two source lines SL2 and SL3 charged with different voltages V_TOP and V_BOT are short-circuited and have the same voltage level.

[0083] As Figures 5 to 8 explained in, the drive controller according to one or more example embodiments may measure the magnitude of the load of the source line and detect a short-circuit defect between the source line and other wirings (s).

[0084] As Figure 5 shown, the drive controller according to one or more example embodiments may determine the magnitude of the load of the four adjacent source lines SLi,..., SL(i + 3) by precharging the four adjacent source lines SLi,..., SL(i + 3) with an arbitrary data voltage. As Figure 6 shown, the drive controller according to one or more example embodiments may detect a short circuit with other voltage wirings by precharging the four adjacent source lines SLi,..., SL(i + 3) with a relatively high voltage V_TOP.

[0085] As Figure 7The driving controller according to one or more example embodiments as shown can detect a short circuit with other voltage wirings of four adjacent source lines SLi, ..., SL(i+3) by precharging the four adjacent source lines SLi, ..., SL(i+3) with a relatively low voltage V_BOT. As Figure 8 shown, the driving controller according to one or more example embodiments can detect a short circuit between four adjacent source lines SLi, ..., SL(i+3) by precharging the four adjacent source lines SLi, ..., SL(i+3) with different voltages.

[0086] Figure 9 is a block diagram showing a part of a panel and a source driver according to one or more example embodiments.

[0087] Referring to Figure 9 , the source driver can include an amplifier area 901, a first switch circuit 902, a digital-to-analog converter (DAC) 903, a ramp signal generator 904, and a multiplexer circuit 905. The source driver can be electrically connected and / or directly connected to the source line SLi of the panel PANEL. The source driver can be Figure 1 the driving circuit 110 or the source driver 111 of Figure 9 . In Figure 1 , the source driver is described as including a switch circuit 902, but the switch circuit 902 can be formed on the same substrate as the panel (e.g., Figure 9 120 of Figure 2 ). In the components of

[0088] The amplifier area 901 can be connected to the switch circuit 902 and the multiplexer circuit 905. The amplifier area 901 can receive an input signal PSi from the DAC 903 through the multiplexer circuit 905 and output a data signal Si. The amplifier area 901 can amplify the input signal PSi received from the DAC 903 to generate a data signal Si, and can send the generated data signal Si to the panel PANEL through the source line SLi. In some embodiments, the amplifier area 901 can operate as a comparator. When the amplifier area 901 operates as a comparator, the amplifier area 901 can receive a detection signal Ri from the source line SLi and receive a ramp signal VRMP from the ramp signal generator 904 through the multiplexer circuit 905. The amplifier area 901 can compare the detection signal Ri and the ramp signal VRMP, and output an output signal VOi to a connection to the driving controller (e.g., Figure 1The output line OLi of (113) therein.

[0089] The switch circuit 902 can be connected to the output terminal of the amplifier region 901. The switch circuit 902 can electrically connect the source line SLi to the output terminal of the amplifier region 901 or electrically disconnect the source line SLi from the output terminal of the amplifier region 901 depending on the level of the first selection signal SEL.

[0090] The DAC 903 can receive the data DATA and convert the data DATA from a digital signal to an analog signal.

[0091] The ramp signal generator 904 can generate a ramp signal VRMP. For example, the ramp signal generator 904 can generate a ramp signal VRMP that increases at a constant slope or a ramp signal VRMP that decreases at a constant slope. The ramp signal generator 904 can operate based on the ramp control signal EN provided from the drive controller 113. When the ramp control signal EN is activated, the ramp signal generator 904 can generate the ramp signal VRMP.

[0092] The multiplexer circuit 905 can be connected to the input terminal of the amplifier region 901. The multiplexer circuit 905 can electrically connect the DAC 903 to the input terminal of the amplifier region 901 or electrically connect the ramp signal generator 904 to the input terminal of the amplifier region 901 depending on the level of the second selection signal SEL.

[0093] The source line SLi can have a load 910. For example, the source line SLi can have a capacitive load CP. The source line SLi can be short-circuited with the wirings supplying the power supply voltages ELVSS, ELVDD 920. Additionally, the source line SLi can be short-circuited with another adjacent source line SL(i + 1) 930.

[0094] Next, reference will be made to Figures 10 to 12 Describe a method for detecting the occurrence of a short circuit in the load of the source line SLi and / or the source line SLi.

[0095] Figure 10 and Figure 11 is a view illustratively showing a part of a panel and a source driver according to one or more example embodiments.

[0096] Reference Figure 10 , the source driver (SOURCE DRIVER) can output a data signal Si to the panel PANEL. The source driver (SOURCE DRIVER) can include an amplifier 1001 and a switch circuit 1002.

[0097] The output terminal of amplifier 1001 can be connected to output line OLi. The output terminal of amplifier 1001 can be connected to source line SLi through switch circuit 1002. The input terminal IN1 of amplifier 1001 can be connected to source line SLi, and the input terminal IN2 of amplifier 1001 can be connected to the output terminal of multiplexer circuit 1003. Amplifier 1001 can amplify input signal PSi and output data signal Si to the output terminal of amplifier 1001.

[0098] In switch circuit 1002, when the first selection signal SEL is at the logic level “H”, the output terminal of amplifier 1001 can be electrically connected to source line SLi. Switch circuit 1002 can receive data signal Si from the output terminal of amplifier 1001 and send data signal Si to source line SLi.

[0099] In multiplexer circuit 1003, when the second selection signal SEL is at the logic level “H”, the input terminal IN2 of amplifier 1001 can be electrically connected to the output terminal of the DAC. Multiplexer circuit 1003 can receive input signal PSi from the DAC and send input signal PSi to the input terminal IN2 of amplifier 1001.

[0100] Reference Figure 11 , the source driver can output comparison result signal VOi to the driving controller.

[0101] The output terminal of amplifier 1101 can be connected to output line OLi. The output terminal of amplifier 1101 may not be connected to source line SLi. The input terminal IN1 of amplifier 1101 can be connected to source line SLi, and the input terminal IN2 of amplifier 1101 can be connected to the output terminal of multiplexer circuit 1103. Amplifier 1101 can compare detection signal Ri from source line SLi with ramp signal VRMP and output comparison result signal VOi to the output terminal of amplifier 1101.

[0102] When the second selection signal SEL is at the logic level “L”, multiplexer circuit 1103 can electrically connect the input terminal IN2 of amplifier 1101 to the output terminal of the ramp signal generator. Multiplexer circuit 1103 can receive ramp signal VRMP from the ramp signal generator and send ramp signal VRMP to the input terminal IN2 of amplifier 1101.

[0103] Figure 12 is a timing diagram of an operation for a driving controller to determine the characteristics of a source line according to one or more example embodiments.

[0104] Specifically, Figure 12 a timing diagram showing an operation of determining an amplitude of a load of the source line SLi is shown. Refer to Figures 10 to 12 , at timing t30, the input signal PSi can be input to the input terminal IN2 of the amplifier 1001. In Figure 12 , V_IN2 indicates the voltage level of the input terminal IN2. The period from t30 to t31 can be a pre-charge period P_PRE5. During the pre-charge period P_PRE5, the first selection signal SEL can have a logic level “H”. The amplifier 1001 can amplify the input signal PSi on the source line SLi and output it as the data signal Si. That is, during the pre-charge period P_PRE5, the amplifier 1001 can output the data signal Si for charging the source line SLi.

[0105] In some embodiments, the pre-charge period P_PRE5 can be a period of 1 H cycle or shorter. The voltage of the source line SLi can be changed by the data signal Si output by the amplifier 1001. Depending on the amplitude of the load of the source line SLi, the voltage of the source line SLi can change rapidly (e.g., L1) or slowly (e.g., L2 or L3). For example, when the load on the source line SLi is relatively large, the voltage on the source line SLi can change slowly (e.g., L2 or L3). When the load on the source line SLi is relatively small, the voltage on the source line SLi can change rapidly (e.g., L1). The pre-charge period P_PRE5 can be determined based on at least one of the size of the panel PANEL, the length of the source line SLi, or the number of pixels connected to the source line SLi.

[0106] At timing t31, the first selection signal SEL can change from the logic level “H” to the logic level “L”. The amplifier 1101 can output the signal VOi to the output line OLi based on a comparison between the ramp signal VRMP and the detection signal Ri of the source line SLi. The period from t31 to t36 can be a sensing period P_SEN5. During the period from t32 to t36, the level of the ramp signal VRMP can increase at a constant slope.

[0107] The amplifier 1101 can output the result of comparing the signals applied to the input terminals IN1 and IN2 as the comparison result signal VOi. The drive controller 113 can count the comparison result signal VOi based on the clock signal and determine the amplitude of the load of the source line SLi based on the counting result.

[0108] During the period from t31 to t33, when the load of the source line SLi ranges from the first amplitude L1 to the third amplitude L3, since the level of the ramp signal VRMP is less than the level of the detection signal Ri output from the source line SLi, the level of the comparison result signal Voi can have a logic "L" level. At timing t33, since the level of the ramp signal VRMP becomes greater than the level of the detection signal Ri output from the source line SLi with the third amplitude L3 as the load, the level of the comparison result signal Voi of the source line SLi with the third amplitude L3 as the load can change from the logic "L" level to the logic "H" level. The drive controller 113 can count the timing at which the level of the comparison result signal Voi changes from the logic "L" level to the logic "H" level, and determine the amplitude of the load of the source line SLi based on the counting result. At this time, the amplitude of the load of the source line SLi can be related to the period between t32 and t33.

[0109] During the period from t33 to t34, when the load of the source line SLi ranges from the first amplitude L1 to the second amplitude L2, since the level of the ramp signal VRMP is less than the level of the detection signal Ri output from the source line SLi, the level of the comparison result signal Voi can be at the logic "L" level. At timing t34, since the level of the ramp signal VRMP becomes greater than the level of the detection signal Ri output from the source line SLi with the second amplitude L2 as the load, the level of the comparison result signal Voi of the source line SLi with the second amplitude L2 as the load can change from the logic "L" level to the logic "H" level. The drive controller 113 can count the timing at which the level of the comparison result signal Voi changes from the logic "L" level to the logic "H" level, and determine the amplitude of the load of the source line SLi based on the counting result. At this time, the amplitude of the load of the source line SLi can be related to the period between t33 and t34.

[0110] During the period from t34 to t35, when the load of the source line SLi is at the first amplitude L1, the level of the ramp signal VRMP is less than the level of the detection signal Ri output from the source line SLi, and the level of the comparison result signal VOi can have a logic "L" level. At timing t35, since the level of the ramp signal VRMP is greater than the level of the detection signal Ri output from the source line SLi with a load of the first amplitude L1, the level of the comparison result signal VOi of the source line SLi with a load of the first amplitude L1 can change from the logic "L" level to the logic "H" level. The drive controller 113 can count the timing at which the level of the comparison result signal VOi changes from the logic "L" level to the logic "H" level, and determine the amplitude of the load of the source line SLi based on the counting result. At this time, the amplitude of the load of the source line SLi can be related to the period between t34 and t35. At timing t36, the first selection signal SEL can change from the logic level "L" to the logic level "H".

[0111] The source driver according to one or more example embodiments may include a ramp signal generator 904 that generates a ramp signal VRMP, and may use the ramp signal VRMP to determine the amplitude of the load of the source line SLi. In addition, the source driver may detect a defect in the source line SLi by using the ramp signal VRMP in the same or similar manner as Figures 6 to 8 the input signal PSi. Therefore, Figures 6 to 8 and Figure 12 the same or similar descriptions in

[0112] Figure 13 are applicable, and repeated descriptions are omitted.

[0113] As Figure 13 shown, each of the plurality of amplifiers 1301a, 1301b, 1301c, and 1301d may include a first input terminal connected to the corresponding source line of the plurality of source lines SLa, SLb, SLc, and SLd extending from the panel, a second input terminal connected to the output terminal of the corresponding multiplexer circuit of the plurality of multiplexer circuits 1302a, 1302b, 1302c, and 1302d, and an output terminal connected to the corresponding output line of the plurality of output lines OLa, OLb, OLc, and OLd.

[0114] The input terminals of the plurality of multiplexer circuits 1302a, 1302b, 1302c, and 1302d can be connected to the output terminal of the ramp signal generator 1310. The ramp signal generator 1310 can generate a ramp signal VRMP and output the ramp signal VRMP to the plurality of multiplexer circuits 1302a, 1302b, 1302c, and 1302d.

[0115] The logic circuit 1320 can include a plurality of counter circuits 1321a, 1321b, 1321c, and 1321d and a plurality of flip - flops 1322a, 1322b, 1322c, and 1322d. The plurality of counter circuits 1321a, 1321b, 1321c, and 1321d can be respectively connected to a plurality of output lines OLa, OLb, OLc, and OLd, receive a plurality of comparison result signals, and output the result of counting the timing of the level transitions of the plurality of comparison result signals. The plurality of flip - flops 1322a, 1322b, 1322c, and 1322d can store the counting results output from the plurality of counter circuits 1321a, 1321b, 1321c, and 1321d.

[0116] Figure 14 is a view for explaining a display system according to one or more example embodiments.

[0117] Reference Figure 14 , a display system 1400 according to one or more example embodiments can include a processor 1410, a memory 1420, a display device 1430, and a peripheral device 1440 that are electrically connected to a system bus 1450.

[0118] The processor 1410 can control the input / output of data of the memory 1420, the display device 1430, and the peripheral device 1440, and perform image processing of the image data transmitted between the corresponding devices.

[0119] The memory 1420 can include a volatile memory (such as, for example, a dynamic random access memory (DRAM)) and / or a non - volatile memory (such as, for example, a flash memory). The memory 1420 can include, for example but not limited to, DRAM, phase - change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), NOR flash memory, NAND flash memory, and hybrid flash memory (for example, a memory that combines a static random access memory (SRAM) buffer, NAND flash memory, and NOR interface logic). The memory 1420 can store the image data obtained from the peripheral device 1440 or the video signal processed by the processor 1410.

[0120] The display device 1430 may include a display driver integrated circuit (DDI) 1431 and a display panel 1432, and store the image data applied through the system bus 1450 in a frame memory included in the DDI 1431 to be displayed on the display panel 1432. The DDI 1431 may include a source driver according to one or more example embodiments. The DDI 1431 may detect a load and / or a defect in a source line of the display panel 1432. By using an amplifier that applies a data signal to the source line as a comparator, the DDI 1431 may detect a load and / or a defect in the source line based on a change in the voltage charged to the source line. The display driving device according to one or more example embodiments may correspond to the DDI 1431.

[0121] The peripheral device 1440 may be a device that converts a moving picture or a still image into an electrical signal, such as a camera, a scanner, or a webcam. The image data acquired through the peripheral device 1440 may be stored in the memory 1420 or displayed on the display panel 1432 in real time.

[0122] The display system 1400 may be provided in a mobile electronic product such as a smart phone, but is not limited thereto, and may be provided in various types of electronic products that display images.

[0123] Figure 15 is a view for explaining a display system according to one or more example embodiments.

[0124] Reference Figure 15 , the display system 1500 according to one or more example embodiments may include a host 1510, a DDI 1520, and a display panel 1530.

[0125] The host 1510 may receive data or instructions from a user and control the DDI 1520 based on the received data or instructions. The DDI 1520 may drive the display panel 1530 under the control of the host 1510. The DDI 1520 may include a semiconductor device according to one or more example embodiments. The DDI 1520 may include an amplifier region that selectively operates as a source driver that sends a data signal to the display panel 1530 to display image data, or selectively operates as a comparator that receives a detection signal from the display panel 1530 according to a load and / or a defect in the source line.

[0126] In some embodiments, each component or a combination of two or more components described with reference Figures 1 to 15 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), etc.

[0127] Although the present disclosure has been described in connection with example embodiments, it should be understood that the present disclosure is not limited to the described example embodiments, but on the contrary, covers various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A display driving device, comprising: a source driver configured to output a data signal obtained by amplifying an input signal to a source line in a first period, and to receive a detection signal from the source line in a second period different from the first period, and to output a comparison result signal based on a comparison between the detection signal and the input signal; as well as A drive controller is configured to determine the characteristic of the source line based on the timing at which the level of the comparison result signal transitions in the second period.

2. The display driving device according to claim 1, wherein: The source driver comprises: a digital-to-analog converter configured to output the input signal based on data received from the drive controller, and An amplifier region including an amplifier configured to amplify the input signal in the first period to output the data signal, and to compare the input signal and the detection signal in the second period to output the comparison result signal.

3. The display driving device according to claim 2, wherein: The first period is one horizontal period or smaller.

4. The display driving device according to claim 3, wherein: The drive controller is further configured to change the data a plurality of times in the second period, and determine the magnitude of the load of the source line based on data related to timing at which the level of the comparison result signal transitions in the second period among the plurality of changed data.

5. The display driving device according to claim 2, wherein: The first period is a period of two horizontal periods or more.

6. The display driving device according to claim 5, wherein: The drive controller is further configured to change the data a plurality of times in the second period, and detect a defect in the source line based on data related to a timing at which the level of the comparison result signal transitions in the second period among the plurality of changed data.

7. The display driving device according to claim 5, wherein: The source driver is further configured to output a first data signal obtained by amplifying a first input signal to a first source line adjacent to the source line in the first period, the first input signal being different from the input signal, and to receive a first detection signal from the first source line in the second period, and output a first comparison result signal by comparing the first detection signal with the first input signal, and The driving controller is further configured to detect a short circuit between the source line and the first source line based on the comparison result signal and the first comparison result signal.

8. The display driving device according to claim 2, wherein: The source driver further includes a ramp signal generator configured to provide a ramp signal increasing or decreasing with a constant slope as the input signal in the second period.

9. The display driving device according to claim 8, wherein: The driving controller is further configured to count the timing of the level transition of the comparison result signal based on a clock signal, and determine the characteristic of the source line based on the counting result.

10. The display driving device according to claim 8, wherein: The source driver also includes a multiplexer circuit configured to selectively connect the input terminal of the amplifier region to the digital-to-analog converter in the first period and selectively connect the input terminal of the amplifier region to the ramp signal generator in the second period based on the level of a selection signal.

11. The display driving device according to claim 2, wherein: The source driver also includes a switch circuit configured to selectively connect the output terminal of the amplifier region to the source line in the first period and disconnect the output terminal of the amplifier region from the source line in the second period based on a level of a selection signal.

12. A display device, comprising: A panel including a plurality of pixels and a plurality of source lines connected to the plurality of pixels; as well as A display driving circuit includes an amplifier area and a driving controller, wherein the amplifier area includes an amplifier and is configured to send a plurality of data signals to the plurality of source lines in a first time period, and receive a plurality of detection signals from the plurality of source lines in a second time period different from the first time period, and output a plurality of comparison result signals by comparing the plurality of detection signals with an input signal, and the driving controller is configured to determine the characteristics of the plurality of source lines based on the plurality of comparison result signals respectively.

13. The display device according to claim 12, wherein: The display driving circuit further includes a gamma voltage generator configured to output the input signal in the second period.

14. The display device according to claim 13, wherein: The gamma voltage generator is further configured to change a level of the input signal in the second period.

15. The display device according to claim 12, wherein: The display driving circuit further includes a ramp signal generator configured to provide a ramp signal increasing or decreasing with a constant slope as the input signal in the second period.

16. The display device according to claim 12, wherein: The amplifier region is further configured to transmit a data signal of a first level to a first data line among the plurality of data lines in the first period, and transmit a data signal of a second level different from the first level to a second data line adjacent to the first data line among the plurality of data lines.

17. The display device according to claim 12, wherein: The first period is a period of one horizontal period or less, and the driving controller is further configured to determine a magnitude of a load of a corresponding source line.

18. The display device according to claim 12, wherein: The first period is a period of two horizontal periods or more, and the driving controller is further configured to determine a short defect of the corresponding source line.

19. A source driver, comprising: a digital-to-analog converter configured to output an input signal based on the input data; an amplifier region including an amplifier configured to amplify the input signal in a first period to output a data signal, and to compare the input signal with a detection signal received from a source line in a second period after the first period to output a comparison result signal; as well as A switch circuit is configured to selectively connect the output terminal of the amplifier region to the source line in the first period and selectively disconnect the output terminal of the amplifier region from the source line in the second period based on a level of a first selection signal.

20. The source driver according to claim 19, further comprising: a ramp signal generator configured to provide a ramp signal increasing or decreasing with a constant slope as the input signal during the second period, and A multiplexer circuit is configured to selectively connect the input terminal of the amplifier region to the digital-to-analog converter in the first period and selectively connect the input terminal of the amplifier region to the ramp signal generator in the second period based on a level of a second selection signal.

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