Chip three-dimensional packaging method

Abstract

The application belongs to the technical field of semiconductor packaging, and particularly relates to a chip three-dimensional packaging method. The method comprises the following steps: S1, preparing a 12-inch silicon wafer; S2, preparing a first N-layer metal interconnection line; S3, performing wafer-level temporary bonding on the first N-layer metal interconnection line; S4, thinning the silicon back of the silicon wafer by using a wafer-level thinning device; S5, performing a 5-micron-thickness aluminum bonding finger process development; S6, forming a wafer-level multi-layer redistribution silicon substrate; S7, performing dicing on the wafer-level multi-layer redistribution silicon substrate to form a customized-size chiplet integrated substrate; S8, preparing a chiplet integrated micro-module; S9, reconfiguring a 12-inch wafer; and S10, thinning a resin surface by using a wafer-level resin thinning device. The application improves the density of chiplet integration, greatly shortens the metal interconnection between each functional chiplet, and reduces heat generation, power consumption and delay.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a three-dimensional chip packaging method. Background Technology

[0002] Three-dimensional interconnects, building upon planar circuits, utilize a third dimension to integrate multiple layers of devices within a single chip. This involves dividing a large planar circuit into several logically related functional modules distributed across multiple adjacent chip layers, and then integrating these multiple chips through three-dimensional vertical interconnects that penetrate the substrate. Three-dimensional interconnects enable the vertical integration of multiple chips with different functions and processes, significantly reducing the length of the global interconnects, thereby substantially reducing interconnect latency, increasing integrated circuit speed, and decreasing chip power consumption.

[0003] Currently, wafer-level 3D integration mainly involves vertical interconnection between silicon wafer metal pillars and chips. The through-holes (THs) on the silicon wafer are fabricated through a series of processes, including deep silicon etching of THs, growth of an insulating layer on the TH wall, growth of a seed layer on the TH wall, and metal electroplating filling within the THs. While the fabrication process for silicon wafer THs is relatively mature, the bonding process between these THs and multi-chip wafers is challenging, with high material and processing costs. This requires advanced equipment such as high-precision wafer-level assemblers and wafer-level underfilling equipment. Furthermore, the TH silicon wafers are only 200µm in size, resulting in significant wafer warpage, which complicates wafer assembly and increases the risk of wafer cracking during multi-chip integration. This significantly reduces the yield of 3D integration and increases the cost of raw materials and chips. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide a chip three-dimensional packaging method to solve the problems of the high difficulty of silicon wafer through-hole and multi-core port assembly process and the high risk of 200um silicon wafer cracking in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a three-dimensional chip packaging method, comprising the following steps:

[0006] Step S1: Multiple blind holes are etched on a 12-inch silicon substrate using a deep silicon etching device to form a 12-inch silicon wafer, and then metallized and filled in the blind holes using a metal electroplating process.

[0007] Step S2: Fabricate the first N-layer metal interconnect on the 12-inch silicon wafer after metallization filling;

[0008] Step S3: Apply temporary bonding adhesive to the first N-layer metal interconnect using a fully automated spin coating device, and perform wafer-level temporary bonding to the silicon carrier bonding substrate on the temporary bonding adhesive;

[0009] Step S4: After thinning the silicon back of the 12-inch silicon wafer to 20μm to 30μm from the blind via using a wafer-level thinning device, dry etching is performed using a deep silicon etching device until the metal inside the blind via is exposed.

[0010] Step S5: Develop a 5μm thick aluminum bonding finger process for the exposed metal within the blind hole;

[0011] Step S6: Peel off the temporary bonding adhesive and the silicon bonding substrate to form a wafer-level multilayer redistribution silicon substrate;

[0012] Step S7: The wafer-level multilayer redistribution silicon substrate is diced using a wafer-level dicing device to form a chip-integrated substrate of customized size.

[0013] Step S8: Solder the chip with tin-containing leads and the resin through-hole chip to the chip integration substrate to prepare a chip integration micro module.

[0014] Step S9: The multiple chip-integrated micro-modules are laid flat in a 12-inch wafer molding die, and resin is injected into the molding die using wafer-level molding equipment to reconstruct and prepare a 12-inch wafer;

[0015] Step S10: Thin the resin surface using a wafer-level resin thinning device until the tin-containing lead chip and the resin through-hole chip are exposed.

[0016] Step S11: Fabricate a second N-layer metal interconnect on the 12-inch wafer to finally form a 12-inch wafer-level resin-embedded core double-sided multilayer integrated micro-module.

[0017] Step S12: Multiple 12-inch wafer-level resin embedded chip double-sided multilayer integrated micro-modules are flip-mounted onto the pads on the 12-inch chip integrated resin wafer using a high-precision alignment device, and then soldered using a wafer-level reflow device to finally produce a chip-oriented three-dimensional integrated packaging structure.

[0018] Preferably, in step S1, the aspect ratio of the blind hole etching is 200μm:20μm.

[0019] Preferably, in step S1, the metallization filler material is copper.

[0020] Preferably, in step S2, on the 12-inch silicon wafer after metallization filling, a polyimide passivation layer with a thickness of 3μm to 7μm is first coated using a photoresist spin coating device, and then a metal rewiring layer with a thickness of 2μm to 5μm is electroplated using a metal electroplating device to prepare the first N-layer metal interconnect.

[0021] Preferably, in step S6, the temporary bonding adhesive and the silicon bonding carrier on the first N-layer metal interconnect are peeled off using a fully automated laser debonding device to form the wafer-level multilayer redistribution silicon substrate.

[0022] Preferably, step S8, after soldering, further includes filling the gap between the chip with tin-containing leads and the resin through-hole chip and the chip integrated substrate.

[0023] Preferably, in step S11, a polyimide passivation layer with a thickness of 3μm to 7μm is first coated on the 12-inch wafer using a photoresist spin coating device, and then a metal rewiring layer with a thickness of 2μm to 5μm is electroplated using a metal electroplating device to prepare the second N-layer metal interconnect.

[0024] Preferably, in steps S2 and S11, the first N-layer metal interconnect and the second N-layer metal interconnect are made of metal or a mixture of metal and metal nitride.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The three-dimensional packaging method of the present invention reduces wafer warpage by embedding multiple chip-integrated micro-modules into resin reconstruction process, thereby increasing the number of interconnect layers of integrated metal interconnects and expanding the compatibility of such process with chip processing. In addition, compared with the process of forming micro-modules by welding silicon wafers with chips through holes, this process can overcome the problems of micro-module fragility and cracking by resin embedding, greatly improve the support strength and reliability, thereby improving the yield of packaging structure.

[0027] 2. This invention can integrate chips containing different substrates and functions on a wafer-level heterogeneous three-dimensional structure. While keeping the two-dimensional area of ​​the integrated body unchanged and only increasing the three-dimensional height, it greatly improves the chip integration density, significantly shortens the metal interconnection between each functional chip, and reduces heat generation, power consumption and delay. Attached Figure Description

[0028] Figure 1 This is a flowchart of a chip three-dimensional packaging method according to the present invention.

[0029] Figure 2 This is a schematic diagram of the structure in this invention, in which multiple blind holes are etched on a 12-inch silicon substrate using a deep silicon etching device to form a 12-inch silicon wafer, and then metallized and filled into the blind holes using a metal electroplating process.

[0030] Figure 3 This is a schematic diagram of the structure for fabricating the first N-layer metal interconnect on a silicon wafer after metallization filling in this invention.

[0031] Figure 4 This is a schematic diagram of the structure in this invention where temporary bonding adhesive is applied to the first N-layer metal interconnect using a fully automated spin coating device, and wafer-level temporary bonding is performed between the temporary bonding adhesive and the silicon carrier substrate.

[0032] Figure 5 This is a schematic diagram of the structure in this invention, which uses a wafer-level thinning device to thin the silicon back of a silicon wafer until the metal inside the blind via is exposed.

[0033] Figure 6 This is a schematic diagram of the structure developed in this invention for the 5μm thick aluminum bonding finger process at the exposed blind hole metal.

[0034] Figure 7 This is a schematic diagram of the structure of the wafer-level multilayer redistribution silicon substrate formed by peeling off the temporary bonding adhesive and silicon carrier bonding substrate in this invention.

[0035] Figure 8 This is a schematic diagram of the structure of the chip-integrated substrate with customized size formed by dicing a wafer-level multilayer redistribution silicon substrate using a wafer-level dicing device.

[0036] Figure 9 This is a schematic diagram of the structure of the present invention, which involves welding a chip with tin-containing leads and a resin through-hole chip to a chip integrated substrate to form a chip integrated micromodule.

[0037] Figure 10 This is a schematic diagram of the structure of a 12-inch wafer fabrication process in which multiple core particles are integrated into a micro-module and laid flat in a wafer molding die. Resin is injected into the molding die using wafer-level molding equipment to reconstruct and prepare the wafer.

[0038] Figure 11 This is a schematic diagram of the structure of the present invention, which uses a wafer-level resin thinning device to thin the resin surface until the tin-containing lead-out chip and the resin through-hole chip are exposed.

[0039] Figure 12 This is a schematic diagram of the structure of a 12-inch wafer-level resin-embedded core double-sided multilayer integrated micro-module, which is fabricated on a wafer using a second N-layer metal interconnect.

[0040] Figure 13 This is a schematic diagram of the structure in this invention, in which multiple wafer-level resin embedded core particles are flip-mounted onto pads on a 12-inch core particle integrated resin wafer using a high-precision alignment device.

[0041] Figure 14 This is a schematic diagram of a packaging structure for three-dimensional integration of chips, produced by welding using wafer-level reflow equipment in this invention.

[0042] In the diagram: 1-12-inch silicon substrate, 2-blind via, 3-first N-layer metal interconnect, 4-temporary bonding adhesive, 5-silicon bonding carrier, 6-wafer-level multilayer redistribution silicon substrate, 7-chip integrated substrate, 8-chip with tin-containing leads, 9-resin through-hole chip, 10-chip integrated micro-module, 11-second N-layer metal interconnect, 12-12-inch wafer-level resin-embedded chip double-sided multilayer integrated micro-module, 13-pad. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0044] like Figure 1 As shown, this embodiment of the invention provides a three-dimensional chip packaging method, including:

[0045] Step S1: Multiple blind holes 2 are etched on a 12-inch silicon substrate 1 using a deep silicon etching device to fabricate a 12-inch silicon wafer. Metallization is then performed within the blind holes 2 using a metal plating process. Figure 2 As shown.

[0046] In this embodiment of the invention, the blind via 2 on the silicon substrate 1 has an etching aspect ratio of 200μm:20μm, which has excellent electrical performance, with a typical impedance matching value of 50 ohms, an insertion loss of -17dB to 20dB@8GHz, and a support rate of 24GT / s; the metal material for the metallization filling is copper.

[0047] Step S2: Fabricate the first N-layer metal interconnect 3 on the metallized silicon wafer, such as... Figure 3 As shown.

[0048] In this embodiment of the invention, a polyimide passivation layer with a thickness of 3μm to 7μm is coated on the metallized silicon wafer using a photoresist spin coating device. This passivation layer thickness effectively reduces the flatness and warpage of the passivation layer during processing. A metal rewiring layer with a thickness of 2μm to 5μm is then electroplated using a metal electroplating device. This rewiring layer has a good coefficient of thermal expansion matching with the passivation layer, significantly reducing the risk of delamination between the metal rewiring layer and the passivation layer. A first N-layer metal interconnect 3 is fabricated, and the material of the first N-layer metal interconnect 3 is a metal or a mixture of metal and metal nitride.

[0049] Step S3: Temporary bonding adhesive 4 is applied to the first N-layer metal interconnect 3 using a fully automated spin coating device. Wafer-level temporary bonding is then performed on the temporary bonding adhesive 4 to the silicon carrier substrate 5. Figure 4 As shown.

[0050] Step S4: Thin the silicon back of the silicon wafer using a wafer-level thinning device until it is 20μm to 30μm from the blind via. This protects the integrity of the blind via before the copper pillars are exposed and reduces the risk of silicon wafer fragmentation. Dry etching is then performed using a deep silicon etching device until the metal within the blind via is exposed. Figure 5 As shown.

[0051] Step S5: Develop a 5μm thick aluminum bonding finger process at the exposed metal portion within blind via 2, such as... Figure 6 As shown.

[0052] Step S6: Peel off the temporary bonding adhesive 4 and the silicon bonding substrate 5 to form a wafer-level multilayer redistribution silicon substrate 6, as shown. Figure 7 As shown.

[0053] In this embodiment of the invention, the temporary bonding adhesive 4 and the silicon bonding carrier 5 on the first N-layer metal interconnect 3 are peeled off by a fully automated laser debonding device to form a wafer-level multilayer redistribution silicon substrate 6.

[0054] Step S7: The wafer-level multilayer redistribution silicon substrate 6 is diced using a wafer-level dicing device to form a custom-sized chip integration substrate 7, such as... Figure 8 As shown.

[0055] Step S8: The chip 8 with tin-containing leads and the resin through-hole chip 9 are soldered to the chip integration substrate 7, and the gaps between the chip 8 with tin-containing leads, the resin through-hole chip 9 and the chip integration substrate 7 are filled to form a chip integrated micromodule 10, such as... Figure 9 As shown.

[0056] Step S9: Multiple integrated micromodules 10 are laid flat in a 12-inch wafer molding compound. Resin is injected into the molding compound using wafer-level molding equipment to reconstruct and fabricate the 12-inch wafer. Figure 10 As shown.

[0057] Step S10: Thin the resin surface using a wafer-level resin thinning device until the tin-containing lead chip 8 and the resin through-hole chip 9 are exposed, such as... Figure 11 As shown.

[0058] Step S11: Fabricate a second N-layer metal interconnect 11 on the wafer, ultimately forming a 12-inch wafer-level resin-embedded core double-sided multilayer integrated micromodule 12, as shown below. Figure 12 As shown.

[0059] In this embodiment of the invention, a polyimide passivation layer with a thickness of 3μm to 7μm is coated on a wafer using a photoresist spin coating device, and a metal rewiring layer with a thickness of 2μm to 5μm is electroplated using a metal electroplating device to prepare a second N-layer metal interconnect 11. The material of the second N-layer metal interconnect 11 is metal or a mixture of metal and metal nitride.

[0060] Step S12: Multiple wafer-level resin embedded chip double-sided multilayer integrated micro-modules 12 are flip-mounted onto pads 13 on a 12-inch chip integrated resin wafer using a high-precision alignment device, such as... Figure 13 As shown, the wafer-level reflow soldering process ultimately produces a packaging structure oriented towards chip-level three-dimensional integration, such as... Figure 14 As shown.

[0061] In summary, this invention enables the integration of chips with different substrates and functions onto a single wafer-level heterogeneous three-dimensional structure. While maintaining the two-dimensional area of ​​the integrated structure and only increasing the three-dimensional height, it significantly improves the chip integration density, substantially shortens the metal interconnects between each functional chip, and reduces heat generation, power consumption, and latency. Furthermore, the integrated micromodule and resin reconstruction into a 12-inch wafer effectively distribute stress evenly, reducing stress-induced wafer warpage. This also facilitates a better match between the thermal expansion coefficients of the resin wafer, the metal interconnect layers, and the polyimide passivation layer. This improves processing yield, reduces fabrication difficulty, and increases the number of metal interconnect layers. The resin embedding process for micro-modules proposed in this invention provides a resin support for the micro-modules, effectively avoiding the fragility of the 200µm chip integrated substrate and improving the product's environmental adaptability, structural integrity, and reliability. It eliminates the need for complex processes such as wafer-level die bonding and wafer-level underfilling, requiring only a more common single-wafer die bonding and underfilling process to assemble the chip and chip integrated substrate. This reduces production equipment investment costs and shortens the process flow, making it easier to industrialize, and is particularly suitable for the three-dimensional packaging of multi-I / O chips.

[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for three-dimensional chip packaging, characterized in that, Includes the following steps: Step S1: Multiple blind holes (2) are etched on a 12-inch silicon substrate (1) using a deep silicon etching device to form a 12-inch silicon wafer. The blind holes (2) are then metallized and filled by a metal electroplating process. Step S2: Fabricate the first N-layer metal interconnect on the 12-inch silicon wafer after metallization filling (3); Step S3: Apply temporary bonding adhesive (4) to the first N-layer metal interconnect (3) using a fully automatic spin coating equipment, and perform wafer-level temporary bonding to the silicon carrier bonding substrate (5) on the temporary bonding adhesive (4); Step S4: After thinning the silicon back of the 12-inch silicon wafer to 20μm to 30μm from the blind hole (2) using a wafer-level thinning device, dry etching is performed using a deep silicon etching device until the metal inside the blind hole (2) is exposed. Step S5: Develop a 5μm thick aluminum bonding finger process at the exposed metal within the blind hole (2); Step S6: Peel off the temporary bonding adhesive (4) and the silicon bonding substrate (5) to form a wafer-level multilayer redistribution silicon substrate (6); Step S7: The wafer-level multilayer redistribution silicon substrate (6) is diced using a wafer-level dicing device to form a chip-integrated substrate (7) of customized size; Step S8: The chip with tin lead-out end (8) and the resin through-hole chip (9) are soldered to the chip integrated substrate (7) to form a chip integrated micro module (10). Step S9: The multiple chip integrated micro-modules (10) are laid flat in a 12-inch wafer molding die, and the wafer-level molding equipment is used to inject into the molding die to reconstruct and prepare a 12-inch wafer; Step S10: Thin the resin surface using a wafer-level resin thinning device until the tin-containing lead chip (8) and the resin through-hole chip (9) are exposed. Step S11: Fabricate a second N-layer metal interconnect on the 12-inch wafer (11) to finally form a 12-inch wafer-level resin-embedded core double-sided multilayer integrated micro-module (12); Step S12: Multiple 12-inch wafer-level resin embedded chip double-sided multilayer integrated micro-modules (12) are flip-mounted onto the pads (13) on the 12-inch chip integrated resin wafer level using a high-precision alignment device, and then soldered using a wafer-level reflow device to finally form a chip-oriented three-dimensional integrated packaging structure.

2. The chip three-dimensional packaging method as described in claim 1, characterized in that, In step S1, the aspect ratio of the blind hole (2) is 200μm:20μm.

3. The chip three-dimensional packaging method as described in claim 1, characterized in that, In step S1, the metallization filler material is copper.

4. The chip three-dimensional packaging method as described in claim 1, characterized in that, In step S2, on the 12-inch silicon wafer after metallization filling, a polyimide passivation layer with a thickness of 3μm to 7μm is first coated by a photoresist spin coating device, and then a metal rewiring with a thickness of 2μm to 5μm is electroplated by a metal electroplating device to prepare the first N-layer metal interconnect (3).

5. The chip three-dimensional packaging method as described in claim 1, characterized in that, In step S6, the temporary bonding adhesive (4) and the silicon bonding carrier (5) on the first N-layer metal interconnect (3) are peeled off by a fully automated laser debonding device to form the wafer-level multilayer redistribution silicon substrate (6).

6. The chip three-dimensional packaging method as described in claim 1, characterized in that, After soldering, step S8 further includes filling the gap between the chip with tin-containing leads (8) and the resin through-hole chip (9) and the chip integrated substrate (7).

7. The chip three-dimensional packaging method as described in claim 1, characterized in that, In step S11, a polyimide passivation layer with a thickness of 3μm to 7μm is first coated on the 12-inch wafer using a photoresist spin coating device, and then a metal rewiring layer with a thickness of 2μm to 5μm is electroplated using a metal electroplating device to prepare the second N-layer metal interconnect (11).

8. The chip three-dimensional packaging method as described in claim 1, characterized in that, In steps S2 and S11, the first N-layer metal interconnect (3) and the second N-layer metal interconnect (11) are made of metal or a mixture of metal and metal nitride.

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