Switch chip, circuit system and electronic equipment

Abstract

The invention provides a switch chip, a circuit system and electronic equipment, and the chip comprises a grid electrode pin, a source electrode pin and a drain electrode pin, and is also integrated with a boost module, an anti-backflow module, a switch NOMS tube and a pull-down module. According to the invention, the ground end of the boost module is multiplexed as the input control end of the boost module, so that the switch chip can be compatible with the existing PMOS tube high-side switch chip without additionally arranging a ground end pin, thereby reducing the application cost of the switch chip. And the conduction of the boost module on the switch NMOS tube is irrelevant to the parameters of the internal circuit of the boost module, so that the circuit debugging cost in different application scenes is saved, and the application cost of the switch chip is further reduced. Besides, a first pull-down NMOS tube in the pull-down module is connected between a grid electrode and a source electrode of a switch NMOS tube, and on-off of the first pull-down NMOS tube is controlled through a switch control signal, so that the first pull-down NMOS tube is conducted when the switch control signal is at a high level, and the switch NMOS tube is rapidly turned off.

Description

Technical Field

[0001] The present invention relates to the field of circuit switches, and in particular, to a switching chip, a circuit system, and an electronic device. Background Art

[0002] Using MOS transistors as switches has become a common technical means in the industry. Specific application scenarios are roughly divided into: high-side switches and low-side switches. Among them, the high-side switch is coupled between the power supply and the load. The low-side switch is coupled between the load and the ground terminal.

[0003] Although the prior art usually selects PMOS transistors as high-side switches. However, on the premise of the same breakdown voltage and the same impedance, the size of the PMOS transistor is 2 - 3.5 times higher than that of the NMOS transistor. Therefore, compared with using PMOS transistors as high-side switches, using NMOS transistors as high-side switches can greatly save circuit costs.

[0004] However, the existing switching chips that select NMOS transistors as high-side switches have high application costs because they need to perform device debugging on the boost circuit for different application scenarios and have low pin compatibility.

[0005] Therefore, providing a switching chip that can both reduce circuit costs and application costs has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0006] Embodiments of the present invention provide a switching chip, a circuit system, and an electronic device, which can both reduce the circuit costs of the switching chip and reduce the application costs of the switching chip.

[0007] To solve the above technical problems, the technical solution of the present invention provides a switching chip, including:

[0008] A gate pin, a source pin, and a drain pin, the gate pin is connected to a switch control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load;

[0009] A boost module, whose ground terminal is connected to the gate pin, and whose power supply terminal is connected to the source pin. The boost module is used to boost the difference between the power supply voltage and the switch control signal and output a corresponding boosted voltage;

[0010] An anti-backflow module, whose input terminal is connected to the output terminal of the boost module. The anti-backflow module is used to: completely cut off the connection between its input terminal and output terminal when the switch control signal is at a high level; and establish the connection between its input terminal and output terminal when the switch control signal is at a low level;

[0011] A switching NMOS transistor, whose drain is connected to the source pin, whose gate is connected to the output terminal of the anti-backflow module, and whose source is connected to the drain pin;

[0012] A pull-down module, which includes a first pull-down NMOS transistor, a first pull-down resistor, a pull-down diode and a second pull-down NMOS transistor; the drain of the first pull-down NMOS transistor is connected to the output terminal of the anti-backflow module, the source of the first pull-down NMOS transistor is connected to the source of the switching NMOS transistor, the gate of the first pull-down NMOS transistor is connected to the drain of the second pull-down NMOS transistor, and the substrate of the first pull-down NMOS transistor is connected to the pole with the lower voltage among its own source and its own drain; the first end of the first pull-down resistor is connected to the gate of the switching NMOS transistor, and the second end of the first pull-down resistor is connected to the positive pole of the pull-down diode; the negative pole of the pull-down diode is connected to the gate of the first pull-down NMOS transistor; the gate of the second pull-down NMOS transistor is connected to the source pin, the source of the second pull-down NMOS transistor is connected to the gate pin, the drain of the second pull-down NMOS transistor is connected to the gate of the first pull-down NMOS transistor, and the substrate of the second pull-down NMOS transistor is connected to its own source;

[0013] Wherein, the boost module, the anti-backflow module, the switching NMOS transistor and the pull-down module are all integrated on the same chip.

[0014] Optionally, the pull-down module further includes: a second pull-down resistor, a third pull-down NMOS transistor and a third pull-down resistor;

[0015] The first end of the second pull-down resistor is connected to the output terminal of the anti-backflow module, and the second end of the second pull-down resistor is connected to the first end of the first pull-down resistor;

[0016] The gate of the third pull-down NMOS transistor is connected to the second end of the second pull-down resistor, the drain of the third pull-down NMOS transistor is connected to the first end of the second pull-down resistor, the source of the third pull-down NMOS transistor is connected to the source of the first pull-down NMOS transistor, and the substrate of the third pull-down NMOS transistor is connected to its own source;

[0017] The first end of the third pull-down resistor is connected to the gate of the switching NMOS transistor, and the second end of the third pull-down resistor is connected to the source of the switching NMOS transistor.

[0018] Optionally, the first pull-down resistor, the second pull-down resistor and the third pull-down resistor are all greater than or equal to a first threshold value, and the first threshold value is used to represent the minimum resistance value for maintaining the normal driving of the switching NMOS transistor.

[0019] Optionally, the boost module is a charge pump circuit.

[0020] Optionally, the charge pump is specifically a second-order voltage-doubling charge pump.

[0021] Optionally, the anti-backflow module includes a first PMOS transistor, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, and whose drain serves as the output end of the anti-backflow module. The substrate of the first PMOS transistor is connected to its own source.

[0022] Optionally, the anti-backflow module includes a second PMOS transistor, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, and whose drain serves as the output end of the anti-backflow module. Its substrate is connected to the pole with the highest voltage among its own source and its own drain.

[0023] Optionally, the difference between the power supply voltage and the high level of the switch control signal is less than a second threshold value, and the second threshold value is used to represent the minimum operating voltage of the boost module.

[0024] The technical solution of the present invention also provides a circuit system, including the switch chip.

[0025] The technical solution of the present invention also provides an electronic device, including the circuit system.

[0026] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0027] The switch chip provided by the technical solution of the present invention makes the ground terminal of the boost module be multiplexed as the input control terminal of the boost module, so that the switch chip can be compatible with the existing PMOS high-side switch chip without an additional ground terminal pin, thereby improving the compatibility of the switch chip and further reducing the application cost of the switch chip. In addition, the boost module outputs a boosted voltage according to the difference between the external power supply voltage and the external switch control signal. Therefore, the conduction of the switch NMOS transistor by the boost module has nothing to do with the parameters of the internal circuit of the boost module. Compared with the existing high-side switch chips integrating NMOS transistors, the switch chip of the present invention does not need to redesign the boost module in different application scenarios, thereby further reducing the application cost of the switch chip. Finally, by setting the first pull-down NMOS transistor, the first pull-down resistor, the pull-down diode and the second pull-down NMOS transistor, when the switch control signal is at a high level, the first pull-down NMOS transistor is quickly turned on, thereby accelerating the speed of turning off the switch NMOS transistor, so that the switch chip of the present invention can be applied to high-frequency or small-duty-cycle scenarios.

[0028] At the same time, through the anti-backflow module and the pull-down module, it is ensured that the switch NMOS transistor is completely turned off when the switch control signal is at a high level, achieving 0 standby power consumption when the switch NMOS transistor is turned off while ensuring fast turn-off.

[0029] Further, by setting the second pull-down resistor and the third pull-down NMOS transistor, when the switching NMOS transistor is turned on, it is ensured that the first pull-down NMOS transistor is not broken down. Description of the Drawings

[0030] Figure 1 Schematic diagram of the circuit structure of the switching chip provided by the embodiment of the present invention Figure 1 ;

[0031] Figure 2 Schematic diagram of the circuit structure of the switching chip provided by the embodiment of the present invention Figure 2 ;

[0032] Figure 3 Schematic diagram of the circuit structure of the switching chip provided by the embodiment of the present invention Figure 3 . Detailed Embodiments

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. Terms such as "gate", "source", "drain", "fourth", etc. (if any) in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0034] Although a PMOS transistor is set as the high-side switch and there is no need to set an additional boost circuit. However, under the same breakdown voltage and the same impedance, the size of the PMOS transistor is 2-3.5 times higher than that of the NMOS transistor. Therefore, in order to reduce the circuit cost, even in the case where an additional boost circuit needs to be set and the circuit complexity is increased, those skilled in the art still prefer to choose an NMOS transistor as the high-side switch.

[0035] However, there are still the following problems when using an NMOS transistor as the high-side switch:

[0036] 1. When the high-side switch of a PMOS transistor needs to be replaced with that of an NMOS transistor, since the high-side switch of an NMOS transistor requires an additional boost circuit, and this boost circuit needs a ground terminal, when replacing the high-side switch of a PMOS transistor with that of an NMOS transistor, on the basis of the original high-side switch, it is necessary to add a boost circuit and additionally set a ground pin, resulting in the incompatibility of the high-side switches of NMOS transistors and PMOS transistors in the pin architecture, thereby increasing the application cost of replacing the high-side switch of an NMOS transistor.

[0037] 2. In different application scenarios, the existing high-side switches of NMOS transistors all need to debug the parameters of the internal devices of the boost circuit to ensure that the voltage output by the boost circuit can fully turn on the NMOS transistor, thereby further increasing the application cost of the high-side switch of an NMOS transistor in different application scenarios.

[0038] In view of this, the embodiments of the present invention provide a new switching chip to greatly reduce the application cost of the switching chip as a high-side switch in different application scenarios.

[0039] Among them, Figure 1 is the circuit structure schematic diagram of the switching chip provided by the embodiments of the present invention Figure 1 .

[0040] Please refer to Figure 1 , the switching chip provided by the embodiments of the present invention includes:

[0041] A gate pin G, a source pin S, and a drain pin D. The gate pin G is connected to a switch control signal V1, the source pin S is connected to a power supply voltage VDD, and the drain pin D is connected to a load;

[0042] A boost module 10, whose ground terminal AGND is connected to the gate pin G, and whose power supply terminal AVDD is connected to the source pin S. The boost module 10 is used to boost the difference between the power supply voltage VDD and the switch control signal V1 and output a corresponding boost voltage VGC;

[0043] An anti-backflow module 20, whose input terminal is connected to the output terminal of the boost module 10. The anti-backflow module 20 is used for: when the switch control signal V1 is at a high level, completely cutting off the connection between its input terminal and output terminal; and when the switch control signal V1 is at a low level, establishing the connection between its input terminal and output terminal;

[0044] A switching NMOS transistor MN1, whose drain is connected to the source pin S, whose gate is connected to the output terminal of the anti-backflow module 20, and whose source is connected to the drain pin D;

[0045] Pull-down module 30, which includes a first pull-down NMOS transistor MN2, a first pull-down resistor R1, a pull-down diode D1 and a second pull-down NMOS transistor MN3; the drain of the first pull-down NMOS transistor MN2 is connected to the output end of the anti-backflow module 20, the source of the first pull-down NMOS transistor MN2 is connected to the source of the switching NMOS transistor MN1, the gate of the first pull-down NMOS transistor MN2 is connected to the drain of the second pull-down NMOS transistor, and the substrate of the first pull-down NMOS transistor MN2 is connected to the one with the lower voltage among its own source and its own drain; the first end of the first pull-down resistor R1 is connected to the gate of the switching NMOS transistor MN1, and the second end of the first pull-down resistor R1 is connected to the positive electrode of the pull-down diode D1; the negative electrode of the pull-down diode D1 is connected to the gate of the first pull-down NMOS transistor MN2; the gate of the second pull-down NMOS transistor MN3 is connected to the source pin, the source of the second pull-down NMOS transistor MN3 is connected to the gate pin, the drain of the second pull-down NMOS transistor MN3 is connected to the gate of the first pull-down NMOS transistor MN2, and the substrate of the second pull-down NMOS transistor MN3 is connected to its own source;

[0046] Among them, the boost module 10, the anti-backflow module 20, the switching NMOS transistor MN1 and the pull-down module 30 are all integrated in the same chip.

[0047] In order to make the pin architecture of the switching chip in the embodiment of the present invention compatible with the high-side switch of the existing PMOS transistor, the present invention multiplexes the ground terminal AGND of the boost module 10 inside the switching chip as the input control terminal of the boost module 10 and makes the ground terminal AGND connected to the gate pin G of the switching chip, thereby avoiding the need to additionally provide a ground terminal AGND pin for the ground terminal AGND of the boost module 10 on the switching chip. Since the gate pin G accesses the switching control signal V1, the gate pin G of the switching chip of the present invention is equivalent to the gate pin G of the existing PMOS transistor high-side switch. Since the source pin S and the drain pin D of the switching chip of the present invention are respectively connected to the power supply voltage VDD and the load, the source pin S and the drain pin D of the switching chip of the present invention are respectively equivalent to the source pin S and the drain pin D of the existing PMOS transistor high-side switch. As can be seen from the above, on the basis of integrating the NMOS transistor and not additionally providing a ground terminal AGND pin, the pin architecture of the chip of the present invention is compatible with the existing PMOS transistor high-side switch, thereby reducing the application cost of the switching chip.

[0048] In addition, the boost module 10 of the switching chip outputs a boosted voltage VGC based on the difference between the externally input power supply voltage VDD and the externally input switching control signal V1. Therefore, the conduction of the switching NMOS transistor MN1 by the boost module 10 is independent of the device parameters of the internal circuit of the boost module 10. Compared with the existing high-side switch integrated with an NMOS transistor, the switching chip of the present invention does not need to readjust the device parameters of the internal circuit of the boost module 10 in different application scenarios, thereby further reducing the application cost of the switching chip.

[0049] Secondly, when the switching control signal V1 jumps from a low level to a high level, the anti-backflow module 20 completely cuts off the connection between its input end and output end. The gate of the switching NMOS transistor MN1 will still maintain the original boosted voltage VGC and be in a floating state. For example, when the power supply voltage VDD is 5V and the boost module 10 is specifically a second-order voltage doubler charge pump, when the switching control signal V1 is at a low level, the boost module 10 will output a boosted voltage VGC of 8V - 10V. And this 8V - 10V boosted voltage VGC will remain at the gate VG of the switching NMOS transistor MN1 when the anti-backflow module 20 completely cuts off the connection between its input end and output end.

[0050] At this time, the second pull-down NMOS transistor MN3 will be turned off, so that the gate of the first pull-down NMOS transistor MN2 is in a floating state. Therefore, the boosted voltage VG can quickly act on the gate of the first pull-down NMOS transistor MN2 through the path formed by the first pull-down resistor R1 and the pull-down diode D1. And since the source voltage of the first pull-down NMOS transistor MN2 and the source voltage of the switching NMOS transistor MN1 both remain at the power supply voltage VDD at this time. Therefore, the first pull-down NMOS transistor MN2 will be quickly turned on by the boosted voltage VG to quickly pull down the gate of the switching NMOS transistor MN1 to the source of the switching NMOS transistor MN1, thereby realizing the quick turn-off of the switching NMOS transistor MN1.

[0051] For example, when the boosted voltage VG is 9V and the power supply voltage VDD is 5V, after subtracting the conduction voltage of the pull-down diode D1, there will be a voltage of approximately 8.3V acting on the gate of the first pull-down NMOS transistor MN2. And a gate-source voltage of 3.3V is sufficient to turn on the first pull-down NMOS transistor MN2 to quickly pull down the gate of the switching NMOS transistor MN1 to the source of the switching NMOS transistor MN1, thereby realizing the quick turn-off of the switching NMOS transistor MN1.

[0052] When the switch control signal V1 is at a high level, in addition to the first pull-down NMOS transistor MN2 being quickly turned on, the second pull-down NMOS transistor MN3 will also be turned off because its gate-source voltage is approximately 0V. However, the high level of the switch control signal V1 will be transmitted to the gate of the first pull-down NMOS transistor MN2 through the body diode of the second pull-down NMOS transistor MN3. Since the boost voltage VG at the gate of the switch NMOS transistor MN1 acts on the gate of the first pull-down NMOS transistor MN2, the switch NMOS transistor MN1 will be turned off due to the conduction of the first pull-down NMOS transistor MN2, thereby pulling down the gate voltage of the switch NMOS transistor MN1 to the source voltage, turning off the switch NMOS transistor MN2, and finally pulling down both the gate voltage and the source voltage of the switch NMOS transistor MN1 to 0V.

[0053] Originally, the first pull-down NMOS transistor MN2 would also be turned off because its gate-source voltage was 0V. However, at this time, the high level of the switch control signal V1 is transmitted to the gate of the first pull-down NMOS transistor MN2 through the body diode of the second pull-down NMOS transistor MN3, which will maintain the conduction of the first pull-down NMOS transistor MN2, thereby ensuring that the switch NMOS transistor MN1 remains off when the switch control signal V1 is at a high level.

[0054] When the switch control signal V1 is at a low level, the second pull-down NMOS transistor MN3 will be turned on to transmit the low-level switch control signal V1 to the gate of the first pull-down NMOS transistor MN2, so that the first pull-down NMOS transistor MN2 is turned off, thereby ensuring that it does not affect the normal conduction of the switch NMOS transistor MN1.

[0055] It should be noted that although the boost voltage VG at the gate of the switch NMOS transistor MN1 is at a high voltage when the switch control signal V1 is at a low level, the first pull-down resistor limits the path current from the gate of the switch NMOS transistor MN1 to the gate of the first pull-down NMOS transistor MN2. Also, since the switch control signal V1 is transmitted to the gate of the first pull-down NMOS transistor MN2 through the second pull-down NMOS transistor, the gate of the first pull-down NMOS transistor MN2 is at 0V and is turned off.

[0056] Finally, through the anti-backflow module 20 and the first pull-down NMOS transistor MN2, it is ensured that the switch NMOS transistor MN1 is completely turned off when the switch control signal V1 is at a high level, achieving 0 standby power consumption during the turn-off of the switch NMOS transistor while ensuring fast turn-off.

[0057] As a supplementary explanation, the function of the pull-down diode D1 is as follows: when the switching NMOS transistor MN1 is turned off because the switching control signal V1 is at a high level, the switching control signal V1 acting on the gate of the first pull-down NMOS transistor MN2 will not be back-fed to the gate of the switching NMOS transistor MN1 through the path of the first pull-down resistor R1.

[0058] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Wherein, Figure 2 is a schematic circuit structure of the switching chip provided by the embodiment of the present invention Figure 2 .

[0060] Please refer to Figure 2 , as a specific implementation manner, in order to prevent the drain of the first pull-down NMOS transistor MN2 from being broken down by the high voltage of the boost voltage VG, the pull-down module 30 further includes: a second pull-down resistor R2, a third pull-down NMOS transistor MN4, and a third pull-down resistor R3;

[0061] The first end of the second pull-down resistor R2 is connected to the output end of the anti-backflow module 20, and the second end of the second pull-down resistor R2 is connected to the first end of the first pull-down resistor R1;

[0062] The gate of the third pull-down NMOS transistor MN4 is connected to the second end of the second pull-down resistor R2, the drain of the third pull-down NMOS transistor MN4 is connected to the first end of the second pull-down resistor R2, the source of the third pull-down NMOS transistor MN4 is connected to the source of the first pull-down NMOS transistor MN2, and the substrate of the third pull-down NMOS transistor MN4 is connected to its own source;

[0063] The first end of the third pull-down resistor R3 is connected to the gate of the switching NMOS transistor MN1, and the second end of the third pull-down resistor R3 is connected to the source of the switching NMOS transistor MN1.

[0064] The specific working principle of this embodiment is as follows:

[0065] When the switching control signal V1 jumps from a low level to a high level, the first pull-down NMOS transistor MN2 will be turned on, and the principle of its being turned on is the same as the above description, which will not be elaborated here.

[0066] After the first pull-down NMOS transistor MN2 is turned on, the source voltage of the switch NMOS transistor MN1 is transmitted to the source of the third pull-down NMOS transistor MN4 through the first pull-down NMOS transistor MN2. At this time, since the source voltage of the switch NMOS transistor MN1 is equal to the power supply voltage VDD, and the gate voltage of the switch NMOS transistor MN1 remains at the high boost voltage VG, the third pull-down NMOS transistor MN4 is turned on. For example, the power supply voltage VDD is 5V, the high boost voltage VG is 9V, and since the gate of the first pull-down NMOS transistor MN2 is floating, the gate voltage of the third pull-down NMOS transistor MN4 is equal to 9V, and its source voltage is equal to 5V, so the third pull-down NMOS transistor MN4 is turned on.

[0067] After the third pull-down NMOS transistor MN4 is turned on, the source voltage of the switch NMOS transistor MN1 is transmitted to the gate of the switch NMOS transistor MN1 through the third pull-down NMOS transistor MN4 and the first pull-down NMOS transistor MN2. Since the gate of the switch NMOS transistor MN1 is also floating and has no driving ability at this time, the gate voltage of the switch NMOS transistor MN1 is equal to its own source voltage, turning off the switch NMOS transistor MN1.

[0068] After the switch NMOS transistor MN1 is turned off, the source voltage of the switch NMOS transistor MN1 is pulled down to the ground terminal AGND by the load, causing the gate voltage of the switch NMOS transistor MN1 to be pulled down to 0V, thereby turning off the third pull-down NMOS transistor MN4. At this time, the first pull-down NMOS transistor MN2 is turned on, and the conduction principle has been described above and will not be elaborated here. And the substrate of the third pull-down NMOS transistor MN4 is connected to its own source, so the gate and source of the switch NMOS transistor MN1 are connected through the body diodes of the turned-on first pull-down NMOS transistor MN2 and the third pull-down NMOS transistor MN4. At the same time, the third pull-down resistor R3 is further used to ensure the connection between the gate and source of the switch NMOS transistor MN1, thereby ensuring that the switch NMOS transistor MN1 remains off.

[0069] When the switch control signal V1 is at a low level, the voltage at the gate of the first pull-down NMOS transistor MN2 is 0V, and the first pull-down NMOS transistor MN2 is turned off. At this time, the gate voltage of the third pull-down NMOS transistor MN4 is equal to the voltage divided by the first pull-down resistor R1 and the second pull-down resistor R2 for the gate voltage of the switch NMOS transistor MN1. The source of the third pull-down NMOS transistor MN4 is floating, so the third pull-down NMOS transistor MN4 is turned on.

[0070] After the third pull-down NMOS transistor MN4 is turned on, the source voltage of the third pull-down NMOS transistor MN4 will be less than the gate voltage of the third pull-down NMOS transistor MN4. Therefore, it is ensured that the gate-drain voltage, gate-source voltage, and source-drain voltage of the first pull-down NMOS transistor MN2 do not exceed their respective breakdown voltages, so as to ensure that the first pull-down NMOS transistor MN2 will not be broken down without using a high-breakdown-voltage NMOS transistor. At the same time, the gate-drain voltage, gate-source voltage, and source-drain voltage of the third pull-down NMOS transistor MN4 also do not exceed their respective breakdown voltages, so as to ensure that the third pull-down NMOS transistor MN2 will not be broken down without using a high-breakdown-voltage NMOS transistor.

[0071] For example, both the first pull-down NMOS transistor MN2 and the third pull-down NMOS transistor MN4 are standard 5V low-voltage NMOS transistors. When the switch control signal V1 is at a low level, the power supply voltage VDD is 5V, the gate voltage of the switch NMOS transistor MN1 is 9V, and the resistance value of the first pull-down resistor R1 is equal to the resistance value of the second pull-down resistor R2. Therefore, the gate voltage of the third pull-down NMOS transistor MN4 is approximately equal to 4.5V, and the source voltage of the third pull-down NMOS transistor MN4 is clamped at about 3.5V due to the conduction threshold of the NMOS transistor. Therefore, the gate-source voltage, source-drain voltage, and gate-drain voltage of the third pull-down NMOS transistor MN4 do not exceed 5V. At this time, the gate voltage of the first pull-down NMOS transistor MN2 is 0V, its source voltage is equal to the source voltage of the third pull-down NMOS transistor MN4 and is equal to 3.5V, and its drain voltage is equal to the source voltage of the switch NMOS transistor MN1 and is equal to 5V. Therefore, the gate-source voltage, source-drain voltage, and gate-drain voltage of the first pull-down NMOS transistor MN2 also do not exceed 5V.

[0072] It should be noted that in order to ensure that the first pull-down resistor R1, the second pull-down resistor R2, and the third pull-down resistor R3 do not affect the normal on / off of the switch NMOS transistor MN1, the resistance values of the first pull-down resistor R1, the second pull-down resistor R2, and the third pull-down resistor R3 need to be set above a first threshold.

[0073] Among them, the first threshold is used to represent the minimum resistance value for maintaining the normal driving of the switch NMOS transistor. For example, if the boost module can provide a driving current of 1mA, the calculation formula of the first threshold is as follows:

[0074] Rth = VG / Ith; Formula (1) where Rth is used to represent the first threshold; VG is used to represent the gate voltage of the switch NMOS transistor, and Ith is used to represent the maximum value of the shunt current allowed by the resistor branch when driving the switch NMOS transistor.

[0075] When the gate-source voltage of the switching NMOS transistor is equal to 10V and Ith is equal to 10 μA, the first threshold is set to 1 MΩ. Of course, the specific value of the first threshold is related to the driving ability of the boost module and the capacitance of the switching NMOS transistor, which is not limited herein.

[0076] Of course, in addition to setting the second pull-down resistor R2, the third pull-down NMOS transistor MN4 and the third pull-down resistor R3, the same effect can also be achieved by setting the first pull-down NMOS transistor MN2 as a high-voltage withstand MOS transistor, which is not limited herein.

[0077] Among them, Figure 3 is a schematic circuit structure of the switching chip provided by the embodiment of the present invention Figure 3 .

[0078] Please refer to Figure 3 , as a specific implementation manner, the anti-backflow module includes a first PMOS transistor, whose gate is connected to the source pin, whose source is used as the input end of the anti-backflow module, whose drain is used as the output end of the anti-backflow module, and the substrate of the first PMOS transistor is connected to its own source.

[0079] The following takes the power supply voltage VDD as 5V specifically, the boost module as a second-order voltage-doubling charge pump, and the high and low levels of the switching control signal V1 as 5V and 0V respectively as an example to illustrate the working principles of the anti-backflow module 20 and the pull-down module 30:

[0080] When the switching control signal V1 is at a low level, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 5V. The boost module boosts this voltage difference and outputs a boosted voltage VGC of 10V to the source of the first PMOS transistor MP1. The gate of the first PMOS transistor MP1 is connected to the 5V power supply voltage VDD. Therefore, the source-gate voltage difference of the first PMOS transistor MP1 is 5V, which is greater than the threshold voltage of the first PMOS transistor MP1, and the first PMOS transistor MP1 is turned on. Since the drain of the first PMOS transistor MP1 is connected to the gate of the switching NMOS transistor MN1, the boosted voltage VG acts on the gate of the switching NMOS transistor MN1 to turn on the switching NMOS transistor MN1.

[0081] When the switch control signal V1 is at a high level, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 0V. This voltage difference is less than the normal operating voltage of the boost module. Therefore, the boost module outputs a boosted voltage VGC of approximately 5V to the source of the first PMOS transistor MP1. The gate of the first PMOS transistor MP1 is connected to the power supply voltage VDD of 5V. Therefore, the source-gate voltage difference of the first PMOS transistor MP1 is approximately 0V, which is less than the threshold voltage of the first PMOS transistor MP1, and the first PMOS transistor MP1 is turned off. Since the anode of the body diode of the first PMOS transistor MP1 is connected to its own drain, and the cathode of the body diode of the first PMOS transistor MP1 is connected to its own source. Therefore, when the first PMOS transistor MP1 is turned off, the boosted voltage VGC will not be transferred from its own source to its own drain through the body diode of the first PMOS transistor MP1, so as to prevent the boosted voltage VGC from acting on the gate VG of the switching NMOS transistor MN1, thereby completely isolating between the output terminal of the boost module and the gate of the switching NMOS transistor MN1.

[0082] Of course, in addition to the first PMOS transistor M2 described above, other PMOS transistor switch circuits with anti-backflow functions are also within the protection scope of the present invention and are not limited herein.

[0083] As a specific implementation manner, the switch control signal V1 is specifically a periodic PWM pulse signal. And the difference between the high level of the PWM pulse signal and the voltage value of the power supply voltage VDD is less than a second threshold. And the second threshold is used to represent the minimum operating voltage of the boost module.

[0084] As can be seen from the above, when the PWM pulse signal is at a high level, the boost module will output a boosted voltage VGC approximately equal to the power supply voltage VDD, which means that the boost module does not work. Also, since the boost module can only work normally when the voltage difference between its own power supply terminal AVDD and the ground terminal AGND is greater than the second threshold. Therefore, by setting the difference between the high level of the PWM pulse signal and the power supply voltage VDD to be less than the second threshold, it is ensured that the boost module does not work when the PWM pulse signal is at a high level, and further ensured that the anti-backflow module 20 functions, so that the pull-down module 30 turns off the switching NMOS transistor MN1.

[0085] In summary, in the switch chip provided by the embodiment of the present invention, by multiplexing the ground terminal of the boost module as the input control terminal of the boost module, the switch chip can be compatible with the existing PMOS high-side switch chips without an additional ground terminal pin, thereby improving the compatibility of the switch chip and further reducing the application cost of the switch chip. In addition, the boost module outputs a boosted voltage according to the difference between the external power supply voltage and the external switch control signal. Therefore, the conduction of the switching NMOS transistor by the boost module is independent of the parameters of the internal circuit of the boost module. Compared with the existing high-side switch chips integrated with NMOS transistors, the switch chip of the present invention does not need to redesign the boost module in different application scenarios, thereby further reducing the application cost of the switch chip. Finally, by setting the first pull-down NMOS transistor, the first pull-down resistor, the pull-down diode and the second pull-down NMOS transistor, when the switch control signal is at a high level, the first pull-down NMOS transistor is quickly turned on, thereby accelerating the turn-off speed of the switching NMOS transistor, so that the switch chip of the present invention can be applied to high-frequency or small-duty-cycle scenarios.

[0086] Meanwhile, through the anti-backflow module and the pull-down module, it is ensured that the switching NMOS transistor is completely turned off when the switch control signal is at a high level, realizing 0 standby power consumption when the switching NMOS transistor is turned off while ensuring fast turn-off.

[0087] Furthermore, by setting the second pull-down resistor and the third pull-down NMOS transistor, when the switching NMOS transistor is turned on, it is ensured that the first pull-down NMOS transistor is not broken down.

[0088] The embodiment of the present invention also provides a circuit system, including the switch chip provided by the embodiment of the present invention.

[0089] The embodiment of the present invention also provides an electronic device, including the circuit system provided by the embodiment of the present invention.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switch chip, characterized in that: include: A gate pin, a source pin and a drain pin, wherein the gate pin is connected to a switch control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load; A boost module, whose ground terminal is connected to the gate pin, and whose power terminal is connected to the source pin, and the boost module is used to boost the difference between the power supply voltage and the switch control signal, and output a corresponding boost voltage; An anti-backflow module, whose input end is connected to the output end of the boost module, and the anti-backflow module is used to: completely cut off the connection between its own input end and output end when the switch control signal is at a high level; and establish a connection between its own input end and output end when the switch control signal is at a low level; A switch NMOS tube, whose drain is connected to the source pin, whose gate is connected to the output end of the anti-backflow module, and whose source is connected to the drain pin; A pull-down module, comprising a first pull-down NMOS tube, a first pull-down resistor, a pull-down diode and a second pull-down NMOS tube; the drain of the first pull-down NMOS tube is connected to the output end of the anti-backflow module, the source of the first pull-down NMOS tube is connected to the source of the switch NMOS tube, the gate of the first pull-down NMOS tube is connected to the drain of the second pull-down NMOS tube, and the substrate of the first pull-down NMOS tube is connected to the one with a smaller voltage between its own source and its own drain; the first end of the first pull-down resistor is connected to the gate of the switch NMOS tube, and the second end of the first pull-down resistor is connected to the positive electrode of the pull-down diode; the negative electrode of the pull-down diode is connected to the gate of the first pull-down NMOS tube; the gate of the second pull-down NMOS tube is connected to the source pin, the source of the second pull-down NMOS tube is connected to the gate pin, the drain of the second pull-down NMOS tube is connected to the gate of the first pull-down NMOS tube, and the substrate of the second pull-down NMOS tube is connected to its own source; The boost module, the anti-backflow module, the switch NMOS tube and the pull-down module are all integrated in the same chip.

2. The switch chip according to claim 1, characterized in that: The pull-down module further includes: a second pull-down resistor, a third pull-down NMOS tube and a third pull-down resistor; A first end of the second pull-down resistor is connected to the output end of the anti-backflow module, and a second end of the second pull-down resistor is connected to the first end of the first pull-down resistor; The gate of the third pull-down NMOS tube is connected to the second end of the second pull-down resistor, the drain of the third pull-down NMOS tube is connected to the first end of the second pull-down resistor, the source of the third pull-down NMOS tube is connected to the source of the first pull-down NMOS tube, and the substrate of the third pull-down NMOS tube is connected to its own source; A first end of the third pull-down resistor is connected to the gate of the switch NMOS tube, and a second end of the third pull-down resistor is connected to the source of the switch NMOS tube.

3. The switch chip according to claim 2, characterized in that: The first pull-down resistor, the second pull-down resistor and the third pull-down resistor are all greater than or equal to a first threshold, and the first threshold is used to represent a minimum resistance value for maintaining normal driving of the switch NMOS tube.

4. The switch chip according to claim 1, characterized in that: The boost module is a charge pump circuit.

5. The switch chip according to claim 4, characterized in that: The charge pump is specifically a second-order voltage-doubling charge pump.

6. The switch chip according to claim 1, characterized in that: The anti-backflow module comprises a first PMOS tube, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, and whose drain serves as the output end of the anti-backflow module. The substrate of the first PMOS tube is connected to its own source.

7. The switch chip according to claim 1, characterized in that: The anti-backflow module includes a second PMOS tube, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, whose drain serves as the output end of the anti-backflow module, and whose substrate is connected to the one with the largest voltage between its own source and its own drain.

8. The switch chip according to claim 1, characterized in that: The difference between the power supply voltage and the high level of the switch control signal is smaller than a second threshold value, and the second threshold value is used to represent the minimum operating voltage of the boost module.

9. A circuit system, characterized in that: A switch chip comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 9.

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