Bonding wire-free full-die-attach interconnection SiC power module packaging structure and preparation method

Abstract

The application discloses a wire-bonding-free full-pad interconnection SiC power module packaging structure and a preparation method thereof. The packaging structure comprises a lower substrate, an upper substrate, a chip, a power layer terminal, a driving signal terminal, a power pole pad, a signal pole pad and a supporting pad. A plurality of driving signal terminals corresponding to each chip are sintered and fixed on the lower substrate. The upper substrate is sintered and fixed on the power pole pad, the signal pole pad and the supporting pad through secondary reflow soldering. The preparation method comprises welding the chip, positioning each terminal, pad and lower substrate, welding and fixing each terminal, pad and lower substrate, positioning the lower substrate and the upper substrate, and welding the lower substrate and the upper substrate. The above scheme of the application provides a novel packaging technology which is easy to dissipate heat, has low parasitic inductance and meets the requirements of small size and high power density, and has better stability and reliability. The preparation cost of the packaging structure can be reduced, the process design is reasonable, and the yield is high.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor devices and their packaging, and in particular to a bonding wire-free, all-pad interconnect SiC power module packaging structure and its fabrication method. Background Technology

[0002] The statements in this section are merely background information related to this application and do not necessarily constitute prior art.

[0003] Silicon carbide (SiC) power devices offer advantages such as high voltage, high temperature, and high speed, enabling power electronic equipment to develop towards higher power density, higher efficiency, and higher operating temperatures. However, most SiC power devices still use the packaging structure and processes of Si-based devices, making it difficult to fully realize the potential of SiC devices.

[0004] Typically, the interconnect material between the chip source and the substrate of power devices is aluminum or copper wire, while the interconnect material between the chip gate or Kelvin electrode and the substrate is 6-10 miu aluminum wire. This wire bonding process is difficult and prone to breakage. Copper wire bonding requires a layer of copper foil (DTS) to be attached to the chip surface, further complicating manufacturing. Furthermore, this traditional wire bonding method results in dozens or even hundreds of bonding points between the chip and the substrate; the detachment of a single bonding point directly impacts the reliability of the module.

[0005] Chinese invention patent CN 116613129 A (A novel bonding wire-free packaging structure and packaging method for silicon carbide devices) discloses a novel bonding wire-free packaging structure and packaging method for silicon carbide devices, including a chip, a bottom copper bonding sealing layer, high-temperature glass fiber, electrode copper pillars, peripheral copper pillars, top copper foil, and epoxy resin. Although this patent makes beneficial improvements in eliminating the use of bonding wires and achieving low inductance, and has achieved positive results, it still has significant shortcomings in packaging methods and processes. For example, its preparation method is complex, requiring positioning based on a special mold, and the dot matrix must be formed by laser drilling. Its preparation process is complex, and using lasers to drill holes in the module requires related laser equipment, resulting in high preparation costs.

[0006] Chinese invention patent CN 109661723 A (Semiconductor Package with Double-Sided Heat Dissipation Structure) provides a semiconductor package with a double-sided heat dissipation structure. A metal portion is provided to rapidly conduct the high temperature generated from the semiconductor chip to the substrate exposed on the upper and lower surfaces of the package. The metal portion is bonded to the substrate by ultrasonic welding and adhesive. Although this patent makes beneficial improvements in heat dissipation performance and achieves positive results, its gate drive signal still uses an aluminum bonding wire packaging method, which has a larger parasitic inductance compared to wireless bonding packaging.

[0007] In view of this, it is urgent to design a bonding wire-free, all-pad interconnect SiC power module packaging structure that is easy to dissipate heat and has low parasitic inductance, suitable for small size and high power density requirements. Summary of the Invention

[0008] The purpose of this invention is to provide a bonding wire-free, all-pad interconnect SiC power module packaging structure and its fabrication method.

[0009] To achieve the above objectives, the first aspect of the present invention adopts the following technical solution: a bonding wire-free, all-pad interconnect SiC power module packaging structure is proposed, the packaging structure including a lower substrate, an upper substrate, a chip, power stacked terminals, drive signal terminals, power electrode pads, signal electrode pads, and support pads.

[0010] The lower and upper substrates are etched with grooves to form current flow paths.

[0011] The upper surface of the lower substrate has multiple printing areas, and each printing area is printed with a printing layer.

[0012] Multiple chips are sintered and fixed onto each of the printed layers.

[0013] The power stacked terminal includes a first power terminal, a second power terminal, and a third power terminal. The first power terminal and the second power terminal are stacked structures. The first power terminal and the second power terminal are sintered and fixed on the same side of the lower substrate and the upper substrate, respectively. The third power terminal is sintered and fixed on the other side of the lower substrate.

[0014] The multiple drive signal terminals are sintered and fixed on the lower substrate corresponding to each chip.

[0015] The power electrode pad is sintered between the source electrode of the chip and the etched trench on the lower surface of the upper substrate.

[0016] The signal electrode pad is sintered between the driving electrode of the chip and the etched trench on the lower surface of the upper substrate, and the signal electrode pad is electrically connected to the gate and Kelvin electrodes on the chip.

[0017] The support pad is a support structure used to support the lower substrate and the upper substrate. The support pad is located in the area outside the etched trench and the printing area. The support pad is sintered and fixed between the lower substrate and the upper substrate.

[0018] The upper substrate is fixed to the power electrode pad, signal electrode pad, and support pad by secondary reflow soldering.

[0019] To achieve the above objectives, the second aspect of this invention adopts the following technical solution: a method for fabricating a bonding-wire-free, all-pad interconnect SiC power module packaging structure is provided for use in fabricating the all-pad interconnect SiC power module packaging structure of the first aspect of this invention. The fabrication method includes:

[0020] S100, Welding Chips: A printed layer for sintering and welding is printed on the lower substrate. After placing the chip on the printed layer, the chip is sintered and fixed onto the printed layer accordingly.

[0021] S200. Position each terminal, pad, and lower substrate. Place the lower substrate with the chip fixed in it in a reflow soldering fixture. Place the first power terminal, third power terminal, drive signal terminal, power electrode pad, signal electrode pad, and support pad in the corresponding positions on the lower substrate and chip. Each terminal, pad, lower substrate, and chip has reflow solder between them. The first power terminal is placed in the positive position.

[0022] S300: Weld and fix each terminal, gasket, and lower substrate, and perform a first reflow soldering on the reflow soldering fixture that positions each terminal, gasket, and lower substrate.

[0023] S400. Position the lower substrate and the upper substrate. First, place the lower substrate in the secondary reflow soldering fixture. Apply secondary reflow solder to the support pads of the lower substrate. Then, place the upper substrate, which has the second power terminals soldered in opposite directions, onto the secondary reflow soldering fixture.

[0024] S500: Weld the lower substrate and the upper substrate. Perform a second reflow soldering on the secondary reflow soldering fixture that positions the lower substrate and the upper substrate to weld the upper substrate onto the support pad.

[0025] The relevant content of this invention is explained as follows:

[0026] 1. The implementation of the above-mentioned technical solution of the present invention addresses the problems of high parasitic inductance and large loss in traditional silicon carbide (SiC) power devices, as well as the complex process and high cost of conventional bonding wire-free packaging structures. It innovatively designs a bonding wire-free, all-pad interconnect SiC power module packaging structure and its fabrication method. In the packaging structure, power electrode pads and signal electrode pads are used to replace the existing copper or aluminum wire bonding packaging method, which can greatly reduce the parasitic inductance inside the module, giving the SiC power module lower parasitic inductance, allowing it to carry higher current levels, increasing the power rating of the power module, improving the reliability of the power module, and achieving superior electrical characteristics. Simultaneously, the lower and upper substrates are fixed by sintering the pads, giving the packaging structure both double-sided heat dissipation performance, fully utilizing the high-temperature characteristics of SiC power devices. Moreover, this fixing method ensures high bonding strength between the lower substrate and each pad, and between the upper substrate and each pad, preventing device delamination under their respective operating environments, thus providing better stability and reliability. In the fabrication method of this packaging structure, in order to save on manufacturing costs, make the module fabrication process more reasonable, and make the fabricated packaging structure more stable, the following process flow was designed: S100 chip welding, S200 positioning of terminals, pads and lower substrate, S300 welding and fixing of terminals, pads and lower substrate, S400 positioning of lower substrate and upper substrate, and S500 welding of lower substrate and upper substrate. These process flows are scientific and reasonable, and the equipment used is low cost, which can reduce the manufacturing cost of the packaging structure. The process design is reasonable and the yield rate is high. The welding of terminals, pads and lower substrate is positioned and fixed by a single reflow soldering fixture, and the welding of lower substrate and upper substrate is positioned and fixed by a second reflow soldering fixture, which ensures that the position of each component is accurate and without deviation, thereby improving product quality. The welding of terminals, pads and lower substrate is done by a single reflow soldering, and the welding of lower substrate and upper substrate is done by a second reflow soldering, which effectively ensures the stability of terminals and pads and avoids delamination of the packaging structure. The above-described solution of the present invention provides a novel packaging technology that is easy to dissipate heat and has low parasitic inductance, suitable for small-scale high-power-density applications, and has better stability and reliability. It can reduce the manufacturing cost of the packaging structure, has a reasonable process design, and a high yield rate.

[0027] 2. In the technical solution of the first aspect above, both the lower substrate and the upper substrate are double-sided copper-clad ceramic substrates, and the power terminals and signal terminals are sintered onto the copper layer of the lower substrate by solder, thereby providing the SiC power module with high thermal conductivity, good chemical and mechanical properties, as well as low resistivity and excellent current carrying capacity.

[0028] 3. In the technical solution of the first aspect above, the first power terminal and the second power terminal are the same h-shaped structure. The h-shaped structure has one support leg on one side and two support legs on the other side. In the packaged state, the first power terminal is placed facing forward and the second power terminal is placed facing backward, so that the two support legs of the first power terminal and the second power terminal overlap and the support legs of the first power terminal and the second power terminal are misaligned, thereby forming a stacked structure of the first power terminal and the second power terminal. This specially designed stacked structure is beneficial to further reduce parasitic inductance and facilitates positioning and soldering in the manufacturing process, and can also reduce manufacturing costs.

[0029] 4. In the technical solution of the first aspect described above, the two legs on the first power terminal and the second power terminal have soldering areas on the same side. After the first power terminal is sintered and fixed on the lower substrate, the soldering area on the first power terminal faces upward, and after the second power terminal is sintered and fixed on the lower substrate, the soldering area on the second power terminal faces downward. The soldering areas on the first power terminal and the soldering areas on the second power terminal are aligned and soldered. This improves the bonding strength between the first power terminal and the second power terminal of the stacked structure, ensuring that the stacked structure can effectively reduce parasitic inductance.

[0030] 5. In the technical solution of the first aspect above, the first power terminal, the second power terminal, and the third power terminal are respectively a DC+ power terminal, a DC- power terminal, and an AC power terminal, and holes for connecting the power supply and the load are provided at the outward-facing ends of the first power terminal, the second power terminal, and the third power terminal, so as to enable the power module to better realize its function. The power terminal DC+ and the signal terminal are sintered on the lower double-sided copper-clad ceramic substrate (lower substrate), and the power terminal DC- is sintered on the upper double-sided copper-clad ceramic substrate (upper substrate). The power terminal DC+ and the power terminal DC- together form a stacked structure. The method of providing holes for connecting the power supply and the load at the outward-facing ends of the first power terminal, the second power terminal, and the third power terminal makes it more convenient to connect the power module to the external power supply and the load.

[0031] 6. In the technical solution of the first aspect above, the signal electrode pad includes a gate pad and a Kelvin electrode pad. The gate pad is connected to the gate on the chip, and the Kelvin electrode pad is connected to the Kelvin electrode on the chip. This achieves the goal that the connection between the chip and each pin and terminal does not use bonding wires, but only uses pads, further reducing the parasitic inductance inside the module and further improving the power level of the power module.

[0032] 7. In the technical solution of the second aspect above, the chip welding in step S100 includes the following steps:

[0033] S110. Silver paste is printed onto the printing area of ​​the lower substrate using a printing press to form a printing layer;

[0034] S120. Dry the silver paste in a vacuum oven at 120~130℃ for 15~20 minutes.

[0035] S130. The chip is placed onto the silver paste surface of the printed layer using a pick-and-place machine;

[0036] S140, the chip is sintered for 4-6 minutes at 240-260℃ and 15-20 MPa using a pressure silver sintering process.

[0037] The above process allows for better sintering of the chip onto the substrate, resulting in a more robust packaging structure, improved product quality, and prevention of delamination.

[0038] 8. In the technical solution of the second aspect above, in step S200, when positioning the terminals, pads, and lower substrate, the primary reflow solder is Sn5Pb95; in step S400, when positioning the lower and upper substrates, the secondary reflow solder is Sn96.5Ag3.0Cu0.5. The melting point of the primary reflow solder is higher than that of the secondary reflow solder. This ensures that the solder from the primary reflow solder does not melt during the secondary reflow soldering process.

[0039] 9. In the technical solution of the second aspect above, in step S300, when welding and fixing each terminal, gasket and lower substrate, a one-time reflow soldering process is adopted, and the process parameters include: temperature range of 280℃~320℃, time of 20min~25min;

[0040] In step S500, when welding the lower and upper substrates, a secondary reflow soldering process is used. The process parameters include a temperature range of 210℃ to 250℃ and a time of 20 min to 25 min.

[0041] This process ensures higher product quality and reduces voids during the first and second reflow soldering processes, resulting in a more stable and robust package structure after soldering. This further ensures the stability of each terminal and gasket, and further prevents delamination of the package structure.

[0042] 10. In the technical solution of the second aspect above, in step S200, when positioning each terminal pad and the lower substrate, the primary reflow soldering fixture used includes a primary fixture base plate and a primary fixture clamping plate. The primary fixture base plate is provided with a first positioning groove for positioning the lower substrate, the first power terminal, and the third power terminal. After the primary fixture clamping plate is closed, a second positioning groove for positioning the drive signal terminal is formed between the primary fixture base plate and the primary fixture clamping plate.

[0043] In step S400, when positioning the lower substrate and the upper substrate, the secondary reflow soldering fixture used includes a secondary fixture body. The secondary fixture body has a third positioning groove for positioning the lower substrate, the first power terminal, and the third power terminal. Positioning posts for positioning the upper substrate are provided at the four corners of the third positioning groove.

[0044] In this solution, the primary reflow soldering fixture and the secondary reflow soldering fixture were redesigned to enable the packaging structure with the full pad interconnect design to be produced efficiently in a low-cost, high-yield manufacturing process. The fixture has a clever and simple structure, is low in cost, easy to implement, and easy to operate.

[0045] 11. In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0046] 12. In this invention, the terms “center,” “upper,” “lower,” “axial,” “bottom,” “inner,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional assembly relationship shown in the drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0047] 13. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0049] 1. This invention addresses the problems of high parasitic inductance and high loss in traditional silicon carbide (SiC) power devices, as well as the complex processes and high costs associated with conventional wire-free packaging structures. It innovatively designs a wire-free, all-pad interconnect SiC power module packaging structure and its fabrication method. Compared to wire-bonded power modules, the current path in a wire-free power module can be shortened and straightened through optimized design. Since parasitic inductance is proportional to the area of ​​the current loop, the wire-free form significantly reduces the area of ​​the current loop, thereby reducing parasitic inductance. Furthermore, wire-free designs are often accompanied by optimized multilayer packaging (as in this invention, which uses two double-sided copper-clad ceramic substrates), further reducing the distance of the conduction path and lowering parasitic inductance.

[0050] 2. In the technical solution of the packaging structure of this invention, power electrode pads and signal electrode pads are used to replace the existing copper or aluminum wire bonding packaging method, which can greatly reduce the parasitic inductance inside the module, so that the SiC power module has lower parasitic inductance, can carry a larger current level, can increase the power level of the power module, improve the reliability of the power module, and achieve better electrical characteristics. At the same time, the lower substrate and the upper substrate are fixed by sintering the pads, so that the packaging structure has the performance of double-sided heat dissipation, which can give full play to the high temperature characteristics of SiC power devices. Moreover, this fixing method makes the bonding strength between the lower substrate and each pad, and between the upper substrate and each pad, high, and prevents device delamination from occurring in their respective operating environments, thus having better stability and reliability.

[0051] 3. In the preparation method of the packaging structure of the present invention, in order to save preparation costs, make the module preparation process more reasonable, and make the prepared packaging structure more stable, the following process flow is designed: S100 welding chip, S200 positioning terminals, pads and lower substrate, S300 welding and fixing terminals, pads and lower substrate, S400 positioning lower substrate and upper substrate, and S500 welding lower substrate and upper substrate. These process flows are scientific and reasonable, and the equipment used is low cost, which can reduce the preparation cost of the packaging structure. The process design is reasonable and the yield rate is high. The welding of terminals, pads and lower substrate is positioned and fixed by a single reflow soldering fixture, and the welding of lower substrate and upper substrate is positioned and fixed by a second reflow soldering fixture, which ensures that the position of each component is accurate and without deviation, thereby improving product quality. The welding of terminals, pads and lower substrate is done by a single reflow soldering, and the welding of lower substrate and upper substrate is done by a second reflow soldering, which effectively ensures the stability of terminals and pads and avoids delamination of the packaging structure.

[0052] 4. In summary, the above-mentioned solution of the present invention provides a novel packaging technology with easy heat dissipation and low parasitic inductance suitable for small-scale, high-power-density applications. The all-pad interconnect packaging method allows for a shorter and straighter current path through optimized design. Since parasitic inductance is proportional to the area of ​​the current loop, the bond-free form significantly reduces the area of ​​the current loop, thus reducing parasitic inductance to 6.3 nH. In contrast, the parasitic inductance of traditional double-sided water-cooled modules is typically around tens of nH, indicating that this module's packaging method effectively reduces parasitic inductance and provides valuable reference for future packaging. Furthermore, through its double-sided water-cooled heat dissipation structure, when the heat transfer coefficient is 2000 W / (m²·K), the average junction temperature of the chip is 156.5°C, and the maximum junction temperature is 162.9°C. This indicates that the temperature uniformity error is approximately 4%, effectively controlling the chip's temperature uniformity characteristics. In addition, the full-pad interconnect package design is usually accompanied by optimized multi-layer packaging, which further reduces the distance of the conduction path, reduces parasitic inductance, and has better stability and reliability. It can reduce the manufacturing cost of the package structure, and the process design is reasonable with a high yield. Attached Figure Description

[0053] Figure 1 This is an exploded view of the SiC power module package structure with no bond wires and full pad interconnect according to an embodiment of the present invention;

[0054] Figure 2 This is a schematic diagram of the structural layout of the power stack terminals and drive signal terminals in the SiC power module package structure with no bond wire and full pad interconnect according to an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the structural layout of the power electrode pad, signal electrode pad, and support pad in the SiC power module package structure with no bond wire and full pad interconnection according to an embodiment of the present invention.

[0056] Figure 4 This is a circuit topology diagram of the SiC power module package structure with no bond wire and full pad interconnect according to an embodiment of the present invention;

[0057] Figure 5 This is a schematic flowchart illustrating the fabrication method of the bonding wire-free, all-pad interconnect SiC power module packaging structure according to an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram of the single-pass reflow soldering fixture used in the fabrication method of the bonding wire-free all-pad interconnect SiC power module package structure according to an embodiment of the present invention;

[0059] Figure 7 This is a schematic diagram of the use of a reflow soldering fixture in the fabrication method of a bonding wire-free, all-pad interconnect SiC power module package structure according to an embodiment of the present invention.

[0060] Figure 8 This is a schematic diagram of the secondary reflow soldering fixture used in the fabrication method of the bonding wire-free all-pad interconnect SiC power module package structure according to an embodiment of the present invention.

[0061] Figure 9 This is a schematic diagram illustrating the use of a secondary reflow soldering fixture in the fabrication method of a bondless, all-pad interconnect SiC power module package structure according to an embodiment of the present invention.

[0062] In the attached diagrams above:

[0063] 1. Chip;

[0064] 2. Lower substrate; 21. Printed layer;

[0065] 3. Upper substrate;

[0066] 4. Power stacked terminals;

[0067] 41. First power terminal; 42. Second power terminal; 43. Third power terminal;

[0068] 401. Support leg one; 402. Support leg two; 403. Welding area;

[0069] 5. Drive signal terminals;

[0070] 6. Power electrode pads;

[0071] 7. Signal electrode pad; 71. Gate electrode pad; 72. Kelvin electrode pad;

[0072] 8. Support pads;

[0073] 9. Silver paste;

[0074] 10. Tin-lead alloy solder;

[0075] 11. Primary reflow soldering fixture; 111. Primary fixture base plate; 1111. First positioning groove; 112. Primary fixture clamping plate; 1121. Second positioning groove;

[0076] 12. Secondary reflow soldering fixture; 121. Secondary fixture body; 1211. Third positioning groove; 1212. Positioning post. Detailed Implementation

[0077] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0078] This invention aims to address the problems of high parasitic inductance and high loss in traditional silicon carbide (SiC) power devices, as well as the complex processes and high costs associated with conventional wireless packaging structures. It innovatively designs a wireless, all-pad interconnect SiC power module packaging structure and its fabrication method to achieve lower parasitic inductance, higher current carrying capacity, increased power rating, improved reliability, and reduced manufacturing costs of the packaging structure.

[0079] Example 1, as Figures 1 to 4 As shown, Embodiment 1 of the present invention proposes a bonding wire-free, all-pad interconnect SiC power module packaging structure. The packaging structure includes a lower substrate 2, an upper substrate 3, a chip 1, power stack terminals 4, drive signal terminals 5, power electrode pads 6, signal electrode pads 7, and support pads 8.

[0080] The lower substrate 2 and the upper substrate 3 are formed by etching grooves to form current flow paths.

[0081] The upper surface of the lower substrate 2 has multiple printing areas, and each printing area is printed with a printing layer 21.

[0082] Multiple chips 1 are sintered and fixed on each of the printed layers 21.

[0083] like Figure 2 As shown, the power stacked terminal 4 includes a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are stacked structures. The first power terminal 41 and the second power terminal 42 are each sintered and fixed on the same side of the lower substrate 2 and the upper substrate 3, and the third power terminal 43 is sintered and fixed on the other side of the lower substrate 2.

[0084] Multiple drive signal terminals 5 are sintered and fixed on the lower substrate 2 corresponding to each chip 1.

[0085] The power electrode pad 6 is sintered between the source electrode of the chip 1 and the etched trench on the lower surface of the upper substrate 3.

[0086] The signal electrode pad 7 is sintered between the driving electrode of the chip 1 and the etched trench on the lower surface of the upper substrate 3, and the signal electrode pad 7 is electrically connected to the gate and Kelvin electrodes on the chip 1.

[0087] The support pad 8 is a support structure used to support the lower substrate 2 and the upper substrate 3. The support pad 8 is located in the area outside the etched trench and the printing area. The support pad 8 is sintered and fixed between the lower substrate 2 and the upper substrate 3.

[0088] The upper substrate 3 is fixed to the power electrode pad 6, signal electrode pad 7, and support pad 8 by secondary reflow soldering.

[0089] Through the implementation of the embodiments of the present invention, the technical solution of the packaging structure uses power electrode pads 6 and signal electrode pads 7 to replace the existing copper or aluminum wire bonding packaging method, which can greatly reduce the parasitic inductance inside the module, so that the SiC power module has lower parasitic inductance, can carry a larger current level, can increase the power level of the power module, improve the reliability of the power module, and achieve better electrical characteristics. At the same time, the lower substrate 2 and the upper substrate 3 are fixed by sintering the pads, so that the packaging structure has the performance of double-sided heat dissipation, which can give full play to the high temperature characteristics of SiC power devices. Moreover, this fixing method makes the bonding strength between the lower substrate 2 and each pad, and between the upper substrate 3 and each pad high, so that the device delamination will not occur in their respective operating environments, thus having better stability and reliability.

[0090] In one embodiment of the present invention, both the lower substrate 2 and the upper substrate 3 are double-sided copper-clad ceramic substrates. The power terminals and signal terminals are sintered onto the copper layer of the lower substrate 2 with solder, thereby providing the SiC power module with high thermal conductivity, good chemical and mechanical properties, as well as low resistivity and excellent current carrying capacity.

[0091] In another embodiment of the present invention, such as Figure 2 As shown, the first power terminal 41 and the second power terminal 42 are identical h-shaped structures. The h-shaped structure has one support 401 on one side and two supports 402 on the other side. In the packaged state, the first power terminal 41 is placed facing forward and the second power terminal 42 is placed facing backward, so that the two supports 402 of the first power terminal 41 and the second power terminal 42 overlap and the supports 401 of the first power terminal 41 and the second power terminal 42 are misaligned, thereby forming a stacked structure of the first power terminal 41 and the second power terminal 42. This specially designed stacked structure is beneficial to further reduce parasitic inductance, facilitates positioning and soldering in the manufacturing process, and can also reduce manufacturing costs.

[0092] In another embodiment of the present invention, such as Figure 2As shown, the two legs 402 on the first power terminal 41 and the second power terminal 42 have soldering areas 403 on the same side. After the first power terminal 41 is sintered and fixed on the lower substrate 2, the soldering area 403 on the first power terminal 41 faces upward, and after the second power terminal 42 is sintered and fixed on the lower substrate 2, the soldering area 403 on the second power terminal 42 faces downward. The soldering areas 403 on the first power terminal 41 and the soldering areas 403 on the second power terminal 42 are aligned and soldered. This improves the bonding strength between the first power terminal 41 and the second power terminal 42 in the stacked structure, ensuring that the stacked structure can effectively reduce parasitic inductance.

[0093] In one embodiment of the present invention, the first power terminal 41, the second power terminal 42, and the third power terminal 43 are respectively a DC+ power terminal, a DC- power terminal, and an AC power terminal. Holes for connecting the power supply and the load are provided at the outward-facing ends of the first power terminal 41, the second power terminal 42, and the third power terminal 43, so as to enable the power module to better realize its function. The power terminal DC+ and the signal terminal are sintered on the lower double-sided copper-clad ceramic substrate (lower substrate 2), and the power terminal DC- is sintered on the upper double-sided copper-clad ceramic substrate (upper substrate 3). The power terminal DC+ and the power terminal DC- together form a stacked structure. The method of providing holes for connecting the power supply and the load at the outward-facing ends of the first power terminal 41, the second power terminal 42, and the third power terminal 43 makes it more convenient to connect the power module to the external power supply and the load.

[0094] In another embodiment of the present invention, the signal electrode pad 7 includes a gate pad 71 and a Kelvin electrode pad 72. The gate pad 71 is connected to the gate on the chip 1, and the Kelvin electrode pad 72 is connected to the Kelvin electrode on the chip 1. This achieves the goal that the connection between the chip 1 and each pin and terminal does not use bonding wires, but only uses pads, further reducing the parasitic inductance inside the module and further improving the power level of the power module.

[0095] Furthermore, the technical solution of the packaging structure of the present invention will be introduced by taking one detailed packaging structure embodiment as an example.

[0096] In this detailed packaging structure embodiment, a bonding wire-free, all-pad interconnect SiC power module packaging structure is provided. The packaging structure includes a lower substrate 2, an upper substrate 3, a chip 1, a power stack terminal 4, a drive signal terminal 5, a power electrode pad 6, a signal electrode pad 7, and a support pad 8. The number of chips 1 is six. The parallel connection of SiC chips 1 increases the total current, enabling the packaging structure to integrate a larger power.

[0097] In this detailed packaging structure embodiment, etched trenches for forming current flow paths are formed on the lower substrate 2 and the upper substrate 3 by etching. Both the lower substrate 2 and the upper substrate 3 are double-sided copper-clad ceramic substrates. The upper surface of the lower substrate 2 has multiple printing areas, and each printing area has a printed layer 21. Multiple chips 1 are correspondingly sintered and fixed on each of the printed layers 21.

[0098] In this detailed packaging structure embodiment, the power stacked terminal 4 includes a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are stacked structures, and the first power terminal 41 and the second power terminal 42 are each sintered and fixed on the same side of the lower substrate 2 and the upper substrate 3, respectively. The third power terminal 43 is sintered and fixed on the other side of the lower substrate 2. The first power terminal 41 and the second power terminal 42 have the same h-shaped structure. The h-shaped structure has one support 401 on one side and two supports 402 on the other side. In the packaged state, the first power terminal 41 is placed facing forward, and the second power terminal 42 is placed facing backward, so that the two supports 402 of the first power terminal 41 and the second power terminal 42 overlap, and the supports 401 of the first power terminal 41 and the second power terminal 42 are misaligned, thereby forming a stacked structure of the first power terminal 41 and the second power terminal 42. The two legs 402 on the first power terminal 41 and the second power terminal 42 have soldering areas 403 on the same side. After the first power terminal 41 is sintered and fixed on the lower substrate 2, the soldering area 403 on the first power terminal 41 faces upward, and after the second power terminal 42 is sintered and fixed on the lower substrate 2, the soldering area 403 on the second power terminal 42 faces downward. The soldering areas 403 on the first power terminal 41 and the soldering areas 403 on the second power terminal 42 are aligned and soldered. Specifically, the first power terminal 41, the second power terminal 42, and the third power terminal 43 are DC+ power terminals, DC- power terminals, and AC power terminals, respectively. Holes for connecting the power supply and the load are provided at the outward-facing ends of the first power terminal 41, the second power terminal 42, and the third power terminal 43. The first power terminal 41 DC+ represents the current input terminal, the second power terminal 42 DC- represents the current output terminal, and the AC power terminal represents the alternating current terminal. The diameter of the hole on each terminal is 5.2mm, used for connecting the power supply and the load.

[0099] In this detailed packaging structure embodiment, the 12 drive signal terminals 5 are sintered and fixed on the lower substrate 2 corresponding to each chip 1, and are fixed on the lower substrate 2 by a customized fixture (first reflow soldering fixture 11).

[0100] In this detailed packaging structure embodiment, the power electrode pad 6 is sintered between the source electrode of the chip 1 and the etched trench on the lower surface of the upper substrate 3. The signal electrode pad 7 is sintered between the drive electrode of the chip 1 and the etched trench on the lower surface of the upper substrate 3. The signal electrode pad 7 includes a gate pad 71 and a Kelvin electrode pad 72. The gate pad 71 is connected to the gate on the chip 1, and the Kelvin electrode pad 72 is connected to the Kelvin electrode on the chip 1.

[0101] In this detailed packaging structure embodiment, the support pad 8 is a support structure for supporting the lower substrate 2 and the upper substrate 3. The support pad 8 is located in the area outside the etched trench and printed area, and the support pad 8 is sintered and fixed between the lower substrate 2 and the upper substrate 3. The upper substrate 3 is sintered and fixed on the power electrode pad 6, the signal electrode pad 7, and the support pad 8 by secondary reflow soldering.

[0102] In this detailed packaging structure embodiment, the materials of the power electrode pad 6, signal electrode pad 7, and support pad 8 are not limited to copper, silver, molybdenum, or copper-molybdenum alloys. Gold, silver, or other non-oxidizing metal materials may also be plated on the surface of the pads. By forming a plating layer on the outer surface of the power electrode pad 6, signal electrode pad 7, and support pad 8 through a plating process, oxidation can be effectively prevented during the two vacuum reflow soldering processes.

[0103] like Figure 4 As shown in the diagram, the power module circuit topology in this embodiment includes DC+ and DC- representing DC ports, and AC representing AC port output. The circuit has a total of 6 SiC chips. The parallel SiC chips increase the total current, making the package structure capable of integrating greater power.

[0104] Example 2, as Figure 5 As shown, Embodiment 2 of the present invention proposes a method for fabricating a bonding-wire-free, all-pad interconnect SiC power module package structure, used for fabricating the all-pad interconnect SiC power module package structure. The fabrication method includes:

[0105] S100: Weld chip 1. Print a printed layer 21 for sintering and welding on the lower substrate 2. After placing chip 1 on the printed layer 21, sinter and fix chip 1 on the printed layer 21 accordingly.

[0106] S200. Position each terminal, pad, and lower substrate 2. Place the lower substrate 2, on which the chip 1 is fixed, in the reflow soldering fixture 11. Place the first power terminal 41, the third power terminal 43, the drive signal terminal 5, the power electrode pad 6, the signal electrode pad 7, and the support pad 8 in the corresponding positions of the lower substrate 2 and the chip 1. Each terminal, pad, and the lower substrate 2 and the chip 1 are connected by reflow solder. The first power terminal 41 is placed in the positive position.

[0107] S300, Weld and fix each terminal, gasket and lower substrate 2, and perform a first reflow soldering on the first reflow soldering fixture 11 with each terminal, gasket and lower substrate 2 in place.

[0108] S400, Position the lower substrate 2 and the upper substrate 3. First, place the lower substrate 2 in the secondary reflow soldering fixture 12. Apply secondary reflow solder to the support pad 8 of the lower substrate 2. Then, place the upper substrate 3, which has the second power terminal 42 soldered in the opposite direction, onto the secondary reflow soldering fixture 12.

[0109] S500, weld the lower substrate 2 and the upper substrate 3, perform secondary reflow soldering on the secondary reflow soldering fixture 12 that positions the lower substrate 2 and the upper substrate 3, and weld the upper substrate 3 to the support pad 8.

[0110] In the fabrication method of this packaging structure, in order to save on manufacturing costs, make the module fabrication process more rational, and make the fabricated packaging structure more stable, the following process flow was designed: S100 welding chip 1, S200 positioning terminals, pads, and lower substrate 2, S300 welding and fixing terminals, pads, and lower substrate 2, S400 positioning lower substrate 2 and upper substrate 3, and S500 welding lower substrate 2 and upper substrate 3. These process flows are scientific and reasonable, use low-cost equipment, and can reduce the cost of this packaging structure. The manufacturing process is cost-effective, the process design is reasonable, and the yield rate is high. The welding of each terminal, gasket and lower substrate 2 is positioned and fixed by a single reflow soldering fixture 11, and the welding of the lower substrate 2 and upper substrate 3 is positioned and fixed by a second reflow soldering fixture 12. This ensures that the position of each component is accurate and without deviation, thereby improving product quality. The welding of each terminal, gasket and lower substrate 2 is done by a single reflow soldering, and the welding of the lower substrate 2 and upper substrate 3 is done by a second reflow soldering, so as to effectively ensure the stability of each terminal and gasket and avoid delamination of the packaging structure.

[0111] In one embodiment of the second invention, step S100, welding chip 1, includes the following steps:

[0112] S110. Silver paste 9 is printed onto the printing area of ​​the lower substrate 2 using a printing machine to form a printing layer 21.

[0113] S120. Dry the silver paste 9 in a vacuum oven at 120~130℃ for 15~20 minutes.

[0114] S130, The chip 1 is placed on the surface of the silver paste 9 of the printed layer 21 using a pick and place machine;

[0115] S140. The chip 1 is sintered for 4-6 minutes at 240-260℃ and 15-20 MPa using a pressure silver sintering process.

[0116] The above process is used to better sinter the chip 1 onto the lower substrate 2, resulting in high structural stability of the packaging structure, further improving product quality and avoiding delamination.

[0117] In another embodiment of the present invention, in step S200, when positioning the terminals, pads, and lower substrate 2, the primary reflow solder is Sn5Pb95. In step S400, when positioning the lower substrate 2 and upper substrate 3, the secondary reflow solder is Sn96.5Ag3.0Cu0.5. The melting point of the primary reflow solder is higher than that of the secondary reflow solder. This ensures that the primary reflow solder does not melt during the secondary reflow soldering process.

[0118] In another embodiment of the present invention, in step S300, when welding and fixing each terminal, gasket and lower substrate 2, a one-time reflow soldering process is adopted, and the process parameters include: temperature range of 280℃~320℃, time of 20min~25min;

[0119] In step S500, when welding the lower substrate 2 and the upper substrate 3, a secondary reflow soldering process is adopted. The process parameters include: a temperature range of 210℃~250℃ and a time of 20min~25min.

[0120] This process ensures higher product quality and reduces voids during the first and second reflow soldering processes, resulting in a more stable and robust package structure after soldering. This further ensures the stability of each terminal and gasket, and further prevents delamination of the package structure.

[0121] In one embodiment of the second embodiment of the present invention, in step S200, when positioning each terminal pad and the lower substrate 2, as follows: Figure 6 , Figure 7 As shown, the reflow soldering fixture 11 used includes a primary fixture base plate 111 and a primary fixture clamping plate 112. The primary fixture base plate 111 is provided with a first positioning groove 1111 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. After the primary fixture clamping plate 112 is closed, a second positioning groove 1121 for positioning the drive signal terminal 5 is formed between the primary fixture base plate 111 and the primary fixture clamping plate 112.

[0122] In step S400, the lower substrate 2 and the upper substrate 3 are positioned, such as Figure 8 , Figure 9 As shown, the secondary reflow soldering fixture 12 used includes a secondary fixture body 121. The secondary fixture body 121 has a third positioning groove 1211 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. Positioning posts 1212 for positioning the upper substrate 3 are provided at the four corners of the third positioning groove 1211.

[0123] In this plan, such as Figures 6 to 9 As shown, the primary reflow soldering fixture 11 and the secondary reflow soldering fixture 12 were also redesigned to enable the packaging structure with the full pad interconnect design to be efficiently produced in a low-cost, high-yield manufacturing process. The fixture has a clever and simple structure, is low in cost, easy to implement, and easy to operate.

[0124] Furthermore, the technical solution of the process method of the present invention will be further described using more detailed embodiments three, four, and five.

[0125] Example 3: A method for fabricating a bond-free, all-pad interconnect SiC power module package structure is proposed in Example 3. This method is used to fabricate an all-pad interconnect SiC power module package structure, and the fabrication method includes:

[0126] S100: Welding chip 1. A printed layer 21 for sintering and welding is printed on the lower substrate 2. After placing chip 1 on the printed layer 21, chip 1 is sintered and fixed onto the printed layer 21 accordingly. S100 Welding chip 1 includes the following steps:

[0127] S110. Silver paste 9 is printed onto the printing area of ​​the lower substrate 2 using a printing machine to form a printing layer 21.

[0128] S120. Dry the silver paste 9 in a vacuum oven at 130°C for 15 minutes.

[0129] S130, The chip 1 is placed on the surface of the silver paste 9 of the printed layer 21 using a pick and place machine;

[0130] S140. The chip 1 is sintered at 240℃ and 20MPa for 6 minutes using a pressure silver sintering process.

[0131] S200. Position each terminal, pad, and lower substrate 2. Place the lower substrate 2, on which the chip 1 is fixed, in the primary reflow soldering fixture 11. Place the first power terminal 41, the third power terminal 43, the drive signal terminal 5, the power electrode pad 6, the signal electrode pad 7, and the support pad 8 in the corresponding positions of the lower substrate 2 and the chip 1. Each terminal, pad, and the lower substrate 2 and the chip 1 are connected by primary reflow solder. The primary reflow solder is Sn5Pb95. The first power terminal 41 is placed in the positive position. The primary reflow soldering fixture 11 includes a primary fixture base plate 111 and a primary fixture clamping plate 112. The primary fixture base plate 111 has a first positioning groove 1111 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. After the primary fixture clamping plate 112 is closed, a second positioning groove 1121 for positioning the drive signal terminal 5 is formed between the primary fixture base plate 111 and the primary fixture clamping plate 112. The primary reflow soldering fixture 11 used in this step is mainly used to fix the first power terminal 41DC+, the third power terminal 43AC and the drive signal terminal 5. The connecting material between them is a high-melting-point tin-lead alloy solder 10, which effectively ensures the stability of the terminal welding during the secondary vacuum reflow soldering.

[0132] S300. Weld and fix each terminal, gasket and lower substrate 2. Perform a first reflow soldering on the first reflow soldering fixture 11 with each terminal, gasket and lower substrate 2 in place. The first reflow soldering process is adopted. The process parameters include: temperature of 280℃ and time of 25min.

[0133] S400. Position the lower substrate 2 and the upper substrate 3. First, place the lower substrate 2 in the secondary reflow soldering fixture 12. Apply secondary reflow solder to the support pad 8 of the lower substrate 2. The secondary reflow solder is Sn96.5Ag3.0Cu0.5. Then, place the upper substrate 3, which has the second power terminal 42 soldered on in the opposite direction, onto the secondary reflow soldering fixture 12. The secondary reflow soldering fixture 12 includes a secondary fixture body 121. The secondary fixture body 121 has a third positioning groove 1211 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. Positioning posts 1212 for positioning the upper substrate 3 are set at the four corners of the third positioning groove 1211. The secondary reflow soldering fixture 12 used in the secondary reflow soldering process is mainly used to fix the upper substrate 3 (double-sided copper-clad ceramic substrate) and the support pads 8, power electrode pads 6, and signal electrode pads 7. The connecting material between them is tin-lead alloy solder 10 with a low melting point, which can prevent the tin-lead alloy solder 10 from melting during the first vacuum reflow soldering.

[0134] S500, Weld the lower substrate 2 and the upper substrate 3, perform secondary reflow soldering on the secondary reflow soldering fixture 12 with the lower substrate 2 and the upper substrate 3 positioned, and weld the upper substrate 3 to the support pad 8. The secondary reflow soldering process is adopted, and the process parameters include: temperature of 210℃ and time of 25min.

[0135] Example 4: A method for fabricating a bond-free, all-pad interconnect SiC power module package structure, as proposed in Example 4, is used for fabricating an all-pad interconnect SiC power module package structure. The fabrication method includes:

[0136] S100: Welding chip 1. A printed layer 21 for sintering and welding is printed on the lower substrate 2. After placing chip 1 on the printed layer 21, chip 1 is sintered and fixed onto the printed layer 21 accordingly. S100 Welding chip 1 includes the following steps:

[0137] S110. Silver paste 9 is printed onto the printing area of ​​the lower substrate 2 using a printing machine to form a printing layer 21.

[0138] S120. Dry the silver paste 9 in a vacuum oven at 130°C for 15 minutes.

[0139] S130, The chip 1 is placed on the surface of the silver paste 9 of the printed layer 21 using a pick and place machine;

[0140] S140. Chip 1 is sintered for 4 minutes at 260℃ and 15MPa using a pressure silver sintering process.

[0141] S200. Position each terminal, pad, and lower substrate 2. Place the lower substrate 2, on which the chip 1 is fixed, in the primary reflow soldering fixture 11. Place the first power terminal 41, the third power terminal 43, the drive signal terminal 5, the power electrode pad 6, the signal electrode pad 7, and the support pad 8 in the corresponding positions of the lower substrate 2 and the chip 1. Each terminal, pad, and the lower substrate 2 and the chip 1 are connected by primary reflow solder. The primary reflow solder is Sn5Pb95. The first power terminal 41 is placed in the positive position. The primary reflow soldering fixture 11 includes a primary fixture base plate 111 and a primary fixture clamping plate 112. The primary fixture base plate 111 has a first positioning groove 1111 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. After the primary fixture clamping plate 112 is closed, a second positioning groove 1121 for positioning the drive signal terminal 5 is formed between the primary fixture base plate 111 and the primary fixture clamping plate 112. The primary reflow soldering fixture 11 used in this step is mainly used to fix the first power terminal 41DC+, the third power terminal 43AC and the drive signal terminal 5. The connecting material between them is a high-melting-point tin-lead alloy solder 10, which effectively ensures the stability of the terminal welding during the secondary vacuum reflow soldering.

[0142] S300. Weld and fix each terminal, gasket and lower substrate 2. Perform a first reflow soldering on the first reflow soldering fixture 11 with each terminal, gasket and lower substrate 2 in place. The first reflow soldering process is adopted. The process parameters include: temperature of 320℃ and time of 20min.

[0143] S400. Position the lower substrate 2 and the upper substrate 3. First, place the lower substrate 2 in the secondary reflow soldering fixture 12. Apply secondary reflow solder to the support pad 8 of the lower substrate 2. The secondary reflow solder is Sn96.5Ag3.0Cu0.5. Then, place the upper substrate 3, which has the second power terminal 42 soldered on in the opposite direction, onto the secondary reflow soldering fixture 12. The secondary reflow soldering fixture 12 includes a secondary fixture body 121. The secondary fixture body 121 has a third positioning groove 1211 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. Positioning posts 1212 for positioning the upper substrate 3 are set at the four corners of the third positioning groove 1211. The secondary reflow soldering fixture 12 used in the secondary reflow soldering process is mainly used to fix the upper substrate 3 (double-sided copper-clad ceramic substrate) and the support pads 8, power electrode pads 6, and signal electrode pads 7. The connecting material between them is tin-lead alloy solder 10 with a low melting point, which can prevent the tin-lead alloy solder 10 from melting during the first vacuum reflow soldering.

[0144] S500, Weld the lower substrate 2 and the upper substrate 3, perform secondary reflow soldering on the secondary reflow soldering fixture 12 with the lower substrate 2 and the upper substrate 3 positioned, and weld the upper substrate 3 to the support pad 8. The secondary reflow soldering process is adopted, and the process parameters include: temperature range of 250℃ and time of 20min.

[0145] Example 5: A method for fabricating a bond-free, all-pad interconnect SiC power module package structure, as proposed in Example 5, is used for fabricating an all-pad interconnect SiC power module package structure. The fabrication method includes:

[0146] S100: Welding chip 1. A printed layer 21 for sintering and welding is printed on the lower substrate 2. After placing chip 1 on the printed layer 21, chip 1 is sintered and fixed onto the printed layer 21 accordingly. S100 Welding chip 1 includes the following steps:

[0147] S110. Silver paste 9 is printed onto the printing area of ​​the lower substrate 2 using a printing machine to form a printing layer 21.

[0148] S120. Dry the silver paste 9 in a vacuum oven at 125°C for 18 minutes.

[0149] S130, The chip 1 is placed on the surface of the silver paste 9 of the printed layer 21 using a pick and place machine;

[0150] S140. The chip 1 is sintered for 5 minutes at 250°C and 18 MPa using a pressure silver sintering process.

[0151] S200. Position each terminal, pad, and lower substrate 2. Place the lower substrate 2, on which the chip 1 is fixed, in the primary reflow soldering fixture 11. Place the first power terminal 41, the third power terminal 43, the drive signal terminal 5, the power electrode pad 6, the signal electrode pad 7, and the support pad 8 in the corresponding positions of the lower substrate 2 and the chip 1. Each terminal, pad, and the lower substrate 2 and the chip 1 are connected by primary reflow solder. The primary reflow solder is Sn5Pb95. The first power terminal 41 is placed in the positive position. The primary reflow soldering fixture 11 includes a primary fixture base plate 111 and a primary fixture clamping plate 112. The primary fixture base plate 111 has a first positioning groove 1111 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. After the primary fixture clamping plate 112 is closed, a second positioning groove 1121 for positioning the drive signal terminal 5 is formed between the primary fixture base plate 111 and the primary fixture clamping plate 112. The primary reflow soldering fixture 11 used in this step is mainly used to fix the first power terminal 41DC+, the third power terminal 43AC and the drive signal terminal 5. The connecting material between them is a high-melting-point tin-lead alloy solder 10, which effectively ensures the stability of the terminal welding during the secondary vacuum reflow soldering.

[0152] S300. Weld and fix each terminal, gasket and lower substrate 2. Perform a first reflow soldering on the first reflow soldering fixture 11 with each terminal, gasket and lower substrate 2 in place. The first reflow soldering process is adopted. The process parameters include: temperature of 300℃ and time of 22min.

[0153] S400. Position the lower substrate 2 and the upper substrate 3. First, place the lower substrate 2 in the secondary reflow soldering fixture 12. Apply secondary reflow solder to the support pad 8 of the lower substrate 2. The secondary reflow solder is Sn96.5Ag3.0Cu0.5. Then, place the upper substrate 3, which has the second power terminal 42 soldered on in the opposite direction, onto the secondary reflow soldering fixture 12. The secondary reflow soldering fixture 12 includes a secondary fixture body 121. The secondary fixture body 121 has a third positioning groove 1211 for positioning the lower substrate 2, the first power terminal 41, and the third power terminal 43. Positioning posts 1212 for positioning the upper substrate 3 are set at the four corners of the third positioning groove 1211. The secondary reflow soldering fixture 12 used in the secondary reflow soldering process is mainly used to fix the upper substrate 3 (double-sided copper-clad ceramic substrate) and the support pads 8, power electrode pads 6, and signal electrode pads 7. The connecting material between them is tin-lead alloy solder 10 with a low melting point, which can prevent the tin-lead alloy solder 10 from melting during the first vacuum reflow soldering.

[0154] S500, weld the lower substrate 2 and the upper substrate 3, perform secondary reflow soldering on the secondary reflow soldering fixture 12 with the lower substrate 2 and the upper substrate 3 positioned, and weld the upper substrate 3 to the support pad 8. The secondary reflow soldering process is adopted, and the process parameters include: temperature range of 230℃ and time of 22min.

[0155] Through the implementation of the above embodiments, the problems of high parasitic inductance and high loss of traditional silicon carbide (SiC) power devices, as well as the complex process and high cost of conventional wireless packaging structures, are solved. The packaging method involved in this application forms a novel packaging structure without bonding wires. It uses pads (the material of the pads is not limited to copper, silver, molybdenum or copper-molybdenum alloy, etc.) to replace traditional copper or aluminum bonding wires, and performs full pad interconnect packaging, which achieves extremely low inductance and optimal thermal resistance, thereby increasing the power density of the device and reducing power consumption, thus achieving the purpose of this invention.

[0156] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A bonding-wire-free, all-pad interconnect SiC power module packaging structure, characterized in that: The packaging structure includes a lower substrate (2), an upper substrate (3), a chip (1), a power stack terminal (4), a drive signal terminal (5), a power electrode pad (6), a signal electrode pad (7), and a support pad (8). The lower substrate (2) and the upper substrate (3) are formed by etching grooves to form a current flow path. The upper surface of the lower substrate (2) has multiple printing areas, and each printing area is printed with a printing layer (21); Multiple chips (1) are sintered and fixed on each of the printed layers (21); The power stacked terminal (4) includes a first power terminal (41), a second power terminal (42), and a third power terminal (43). The first power terminal (41) and the second power terminal (42) are stacked structures. The first power terminal (41) and the second power terminal (42) are each sintered and fixed on the same side of the lower substrate (2) and the upper substrate (3). The third power terminal (43) is sintered and fixed on the other side of the lower substrate (2). Multiple drive signal terminals (5) are sintered and fixed on the lower substrate (2) corresponding to each chip (1); The power electrode pad (6) is sintered between the source electrode of the chip (1) and the etched trench on the lower surface of the upper substrate (3); The signal electrode pad (7) is sintered between the driving electrode of the chip (1) and the etched trench on the lower surface of the upper substrate (3). The signal electrode pad (7) is electrically connected to the gate and Kelvin electrodes on the chip (1). The support pad (8) is a support structure for supporting the lower substrate (2) and the upper substrate (3). The support pad (8) is located in the area outside the etched trench and the printing area. The support pad (8) is sintered and fixed between the lower substrate (2) and the upper substrate (3). The upper substrate (3) is fixed on the power electrode pad (6), signal electrode pad (7), and support pad (8) by secondary reflow soldering.

2. The SiC power module packaging structure with no bond wire and full pad interconnect according to claim 1, characterized in that: Both the lower substrate (2) and the upper substrate (3) are made of double-sided copper-clad ceramic substrates, and the power terminals and signal terminals are sintered onto the copper layer of the lower substrate (2) by solder.

3. The bonding wire-free, all-pad interconnect SiC power module packaging structure according to claim 1, characterized in that: The first power terminal (41) and the second power terminal (42) are the same h-shaped structure. The h-shaped structure has a first leg (401) on one side and two second legs (402) on the other side. In the packaged state, the first power terminal (41) is placed facing forward and the second power terminal (42) is placed facing backward, so that the two second legs (402) of the first power terminal (41) and the second power terminal (42) overlap and the first leg (401) of the first power terminal (41) and the second power terminal (42) are misaligned, thereby forming a stacked structure of the first power terminal (41) and the second power terminal (42).

4. The SiC power module packaging structure with no bond wires and full pad interconnect according to claim 1, characterized in that: The first power terminal (41) and the second power terminal (42) have two support legs (402) with soldering areas (403) on the same side. After the first power terminal (41) is sintered and fixed on the lower substrate (2), the soldering area (403) on the first power terminal (41) faces upward. After the second power terminal (42) is sintered and fixed on the lower substrate (2), the soldering area (403) on the second power terminal (42) faces downward. The soldering area (403) on the first power terminal (41) and the soldering area (403) on the second power terminal (42) are aligned and soldered.

5. The bonding-wire-free, all-pad interconnect SiC power module packaging structure according to claim 1, characterized in that: The first power terminal (41), the second power terminal (42), and the third power terminal (43) are respectively a DC+ power terminal, a DC- power terminal, and an AC power terminal, and a hole for connecting the power supply and the load is provided at the outward end of the first power terminal (41), the second power terminal (42), and the third power terminal (43).

6. The SiC power module packaging structure with no bond wire and all-pad interconnect according to claim 1, characterized in that: The signal electrode pad (7) includes a gate pad (71) and a Kelvin electrode pad (72). The gate pad (71) is connected to the gate on the chip (1), and the Kelvin electrode pad (72) is connected to the Kelvin electrode on the chip (1).

7. A method for fabricating a bonding-wire-free, all-pad interconnect SiC power module package structure, used for fabricating the all-pad interconnect SiC power module package structure as described in any one of claims 1 to 6, characterized in that: The preparation method includes: S100, Welding chip (1), Printing a printed layer (21) for sintering welding on the lower substrate (2), placing chip (1) on the printed layer (21) and then sintering and fixing chip (1) on the printed layer (21). S200, Position each terminal, pad and lower substrate (2), place the lower substrate (2) with chip (1) fixed in it in the first reflow soldering fixture (11), place the first power terminal (41), the third power terminal (43), the drive signal terminal (5), the power electrode pad (6), the signal electrode pad (7) and the support pad (8) in the corresponding positions of the lower substrate (2) and the chip (1), and there is first reflow solder between each terminal, pad and the lower substrate (2) and the chip (1), wherein the first power terminal (41) is placed in the positive position; S300, Weld and fix each terminal, gasket and lower substrate (2), and perform a first reflow soldering on the first reflow soldering fixture (11) with each terminal, gasket and lower substrate (2) in place; S400, Position the lower substrate (2) and the upper substrate (3). First, place the lower substrate (2) in the secondary reflow soldering fixture (12). Apply secondary reflow solder to the support pad (8) of the lower substrate (2). Then, place the upper substrate (3) with the reverse-positioned second power terminal (42) onto the secondary reflow soldering fixture (12). S500, Weld the lower substrate (2) and the upper substrate (3), perform secondary reflow soldering on the secondary reflow soldering fixture (12) with the lower substrate (2) and the upper substrate (3) positioned, and weld the upper substrate (3) onto the support pad (8).

8. The method for fabricating the bonding-wire-free, all-pad interconnect SiC power module packaging structure according to claim 7, characterized in that: Step S100, chip welding (1), includes the following steps: S110. Silver paste (9) is printed on the printing area of ​​the lower substrate (2) using a printing press to form a printing layer (21). S120. Dry the silver paste (9) in a vacuum oven at 120~130℃ for 15~20min; S130, The chip (1) is placed on the surface of the silver paste (9) of the printed layer (21) by a pick and place machine; S140. The chip (1) is sintered for 4-6 minutes at 240-260℃ and 15-20Mpa using a pressure silver sintering process.

9. The method for fabricating the bonding-wire-free, all-pad interconnect SiC power module packaging structure according to claim 7, characterized in that: In step S200, when positioning each terminal, pad and lower substrate (2), the primary reflow solder is Sn5Pb95. In step S400, when positioning the lower substrate (2) and upper substrate (3), the secondary reflow solder is Sn96.5Ag3.0Cu0.

5. The melting point of the primary reflow solder is higher than that of the secondary reflow solder.

10. The method for fabricating the bonding-wire-free, all-pad interconnect SiC power module packaging structure according to claim 7, characterized in that: In step S300, the terminals, gaskets and lower substrate (2) are welded and fixed. A one-time reflow soldering process is adopted. The process parameters include: temperature range of 280℃~320℃ and time of 20min~25min. In step S500, when welding the lower substrate (2) and the upper substrate (3), a secondary reflow soldering process is adopted. The process parameters include: temperature range of 210℃~250℃ and time of 20min~25min.

11. The method for fabricating the bonding-wire-free, all-pad interconnect SiC power module packaging structure according to claim 7, characterized in that: In step S200, when positioning each terminal pad and the lower substrate (2), the primary reflow soldering fixture (11) used includes a primary fixture base plate (111) and a primary fixture clamping plate (112). The primary fixture base plate (111) is provided with a first positioning groove (1111) for positioning the lower substrate (2), the first power terminal (41), and the third power terminal (43). After the primary fixture clamping plate (112) is closed, a second positioning groove (1121) for positioning the drive signal terminal (5) is formed between the primary fixture base plate (111) and the primary fixture clamping plate (112). In step S400, when positioning the lower substrate (2) and the upper substrate (3), the secondary reflow soldering fixture (12) used includes a secondary fixture body (121). The secondary fixture body (121) is provided with a third positioning groove (1211) for positioning the lower substrate (2), the first power terminal (41), and the third power terminal (43). Positioning posts (1212) for positioning the upper substrate (3) are provided at the four corners of the third positioning groove (1211).

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