Grid voltage bootstrapped switch and application thereof

Abstract

The invention relates to the technical field of analog integrated circuits, in particular to a gate voltage bootstrap switch and application thereof, and the switch comprises first to eighth MOS transistors, tenth to twelfth MOS transistors, a direction device, a first capacitor, a second capacitor, a first resistor and a second resistor; compared with the prior art, the area of a traditional grid voltage bootstrap switch is reduced, the linearity of the traditional grid voltage bootstrap switch is improved, and harmonic distortion is reduced; in addition, the grid voltage bootstrapped switch is applied to a Sigma Delta modulator of an MASH2 + 2 structure, and effective digits of 19 digits can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly to a gate voltage bootstrap switch and its application. Background Art

[0002] An analog-to-digital converter (ADC) converts a continuous-time and continuous-amplitude signal into a discrete-time and discrete-amplitude signal. The discretization in time is usually achieved by a sample-and-hold (S / H) or track-and-hold (T / H) circuit, using MOS switches and capacitors as signal storage devices. A simple MOS switch limits the input dynamic range (DR) of the ADC because the switch output cannot follow a rail-to-rail input with high linearity. To solve this problem and improve the DR of the ADC, gate voltage bootstrap switches are widely used in the front end of the ADC. Since the state of some transistors depends on the internal node voltage, and the internal node voltage itself is affected by the amplitude of the input signal, distortion may occur. The input signal is connected to the gate voltage bootstrap switch through the impedance of the previous stage, usually a Burrer in the analog circuit. It is found by simulation that the input impedance will cause higher harmonic distortion and increase the nonlinearity of the output signal.

[0003] When designing a high-precision Sigma-Delta ADC, it is necessary to make the signal input to the Sigma-Delta modulator have very high linearity and very low harmonic distortion. To improve the linearity of the output signal and reduce the harmonic distortion, the buffer driving the gate voltage bootstrap switch should be designed to have a very low output impedance; however, this is a huge design challenge and consumes a large amount of power.

[0004] Traditional gate voltage bootstrap switches use a voltage multiplier circuit (two capacitors and two MOS transistors). In analog circuits, capacitors generally occupy the most area, so the voltage multiplier circuit will cause a large area consumption.

[0005] In summary, the traditional gate voltage bootstrap switch has the following problems:

[0006] 1. It cannot meet the requirements of high-precision Sigma Delta ADCs;

[0007] 2. The Buffer module of the previous stage will introduce input impedance, reduce the linearity of the signal, and increase the harmonic distortion of the signal;

[0008] 3. The capacitors used in the voltage multiplier circuit will occupy a large area;

[0009] 4. The potential difference between the substrate and the source terminal of the main switch will change with the change of the input signal, resulting in a change in the threshold voltage of the main switch and introducing nonlinearity. Summary of the Invention

[0010] In order to reduce the area of a traditional bootstrap switch, improve the linearity of the traditional bootstrap switch, and reduce harmonic distortion, the present invention proposes a bootstrap switch, which includes a first MOS transistor to an eighth MOS transistor, a tenth MOS transistor to a twelfth MOS transistor, a directioner, a first capacitor, a second capacitor, a first resistor, and a second resistor, wherein:

[0011] The clock control signal is connected to the input terminal of the inverter, the gate of the first MOS transistor, and the gate of the eighth MOS transistor. The source of the first MOS transistor is grounded, and the drain is connected to one end of the first capacitor, one end of the first resistor, and the sources of the second MOS transistor and the third MOS transistor;

[0012] The gate of the second MOS transistor is connected to the gate of the fourth MOS transistor and the output terminal of the inverter. The drain of the second MOS transistor is connected to the drains of the fourth MOS transistor and the third MOS transistor and the gate of the fifth MOS transistor;

[0013] The gate of the third MOS transistor is connected to the gate of the eleventh MOS transistor, the gate and the drain of the twelfth MOS transistor;

[0014] The source of the fourth MOS transistor is connected to the source of the sixth MOS transistor, the gate of the seventh MOS transistor, and the power supply terminal;

[0015] The source of the fifth MOS transistor is connected to the other end of the first capacitor and the drain of the sixth MOS transistor. The drain of the fifth MOS transistor is connected to the gate of the sixth MOS transistor, the gate of the tenth MOS transistor, and the drain of the seventh MOS transistor;

[0016] The source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, and the source of the eighth MOS transistor is grounded;

[0017] The source of the tenth MOS transistor is connected to the other end of the first resistor, and the drain of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and one end of the second resistor;

[0018] The other end of the second resistor is connected to the input signal terminal;

[0019] The drain of the eleventh MOS transistor is connected to one end of the second capacitor as the output signal, and the other end of the second capacitor is grounded;

[0020] The source of the twelfth MOS transistor is connected to the input signal terminal.

[0021] Further, when the clock control signal is at a high level, the seventh MOS transistor and the eighth MOS transistor are turned on, and the eleventh MOS transistor is turned off; when the clock control signal is at a low level, the first MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are turned off, and the tenth MOS transistor and the eleventh MOS transistor are turned off.

[0022] Further, the first MOS transistor, the second MOS transistor, the third MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor are N-type MOS transistors; the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are P-type MOS transistors.

[0023] The present invention also proposes an application of a bootstrap switch, applying a bootstrap switch to a sample-and-hold circuit.

[0024] The present invention also proposes an application of a bootstrap switch, using a bootstrap switch as an input sampling network of a MASH 2+2 architecture modulator.

[0025] The present invention also proposes an application of a bootstrap switch, applying a bootstrap switch to a Sigma-Delta ADC system.

[0026] Compared with a conventional MOS transistor sampling switch, the circuit structure of the present invention has higher linearity and smaller harmonic distortion; compared with Figure 5 the conventional bootstrap switch shown, it occupies a smaller area and further improves linearity. When the present invention is applied to a Sigma-Delta ADC system, it can reduce the design difficulty of the ADC front-end Buffer module. The present invention reduces the influence of the input impedance introduced by the ADC front-end Buffer module on the bootstrap switch, improves the linearity of the bootstrap switch, and reduces harmonic distortion. Description of the Drawings

[0027] Figure 1 is the schematic diagram of the simulation verification of the bootstrap switch of the present invention;

[0028] Figure 2 is the overall block diagram of the modulator using the bootstrap switch as a sampling network of the present invention;

[0029] Figure 3 is the output spectrum analysis result diagram of the modulator of the present invention;

[0030] Figure 4 is the circuit schematic diagram of the MOS transistor as a sampling switch of the present invention;

[0031] Figure 5 is the circuit schematic diagram of the conventional bootstrap switch;

[0032] Figure 6 is the circuit schematic diagram of the improved bootstrap switch of the present invention;

[0033] In Figure 6Among them, M1 is the first MOS transistor; M2 is the second MOS transistor; M3 is the third MOS transistor; M4 is the fourth MOS transistor; M5 is the fifth MOS transistor; M6 is the sixth MOS transistor; M7 is the seventh MOS transistor; M8 is the eighth MOS transistor; M10 is the tenth MOS transistor; M11 is the eleventh MOS transistor; M12 is the twelfth MOS transistor; C1 is the first capacitor; Cs is the second capacitor; Ry is the first resistor; Zin is the second resistor; vin is the input signal; vout is the output signal; CLK is the clock control signal; VDD is the power supply terminal. Detailed implementation mode

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0035] The present invention provides a gate voltage bootstrap switch, including the first MOS transistor to the eighth MOS transistor, the tenth MOS transistor to the twelfth MOS transistor, a directioner, the first capacitor, the second capacitor, the first resistor, and the second resistor, wherein:

[0036] The clock control signal CLK is connected to the input terminal of the inverter, the gate of the first MOS transistor M1, and the gate of the eighth MOS transistor M8. The source of the first MOS transistor M1 is grounded, and the drain is connected to one end of the first capacitor C1, one end of the first resistor Ry, and the sources of the second MOS transistor M2 and the third MOS transistor M3 together.

[0037] The gate of the second MOS transistor M2 is connected to the gate of the fourth MOS transistor M4 and the output terminal of the inverter together. The drain of the second MOS transistor M2 is connected to the drains of the fourth MOS transistor M4 and the third MOS transistor M3 and the gate of the fifth MOS transistor M5 together.

[0038] The gate of the third MOS transistor M3 is connected to the gate of the eleventh MOS transistor M11, the gate and the drain of the twelfth MOS transistor M12 together.

[0039] The source of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7, and the power supply terminal VDD together.

[0040] The source of the fifth MOS transistor M5 is connected to the other end of the first capacitor C1 and the drain of the sixth MOS transistor M6 together. The drain of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6, the gate of the tenth MOS transistor M10, and the drain of the seventh MOS transistor M7 together.

[0041] The source of the seventh MOS transistor M7 is connected to the drain of the eighth MOS transistor M8, and the source of the eighth MOS transistor M8 is grounded;

[0042] The source of the tenth MOS transistor M10 is connected to the other end of the first resistor Ry, and the drain of the tenth MOS transistor M10 is connected to the source of the eleventh MOS transistor M11 and one end of the second resistor Zin;

[0043] The other end of the second resistor Zin is connected to the input signal vin terminal;

[0044] The drain of the eleventh MOS transistor M11 is connected to one end of the second capacitor Cs together as the output signal vout, and the other end of the second capacitor Cs is grounded;

[0045] The source of the twelfth MOS transistor M12 is connected to the input signal vin terminal.

[0046] The specific structure of the present invention includes 2 capacitors (including the first capacitor C1 and the second capacitor Cs), 1 inverter, 8 NMOS transistors (including the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the seventh MOS transistor M7, the eighth MOS transistor M8, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12), 3 PMOS transistors (including the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6), and 2 resistors (including the first resistor Ry and the second resistor Zin). Compared with the traditional gate voltage bootstrap switch circuit provided by the prior art shown in the figure, the present invention has the following advantages:

[0047] 1. This invention eliminates the clock voltage multiplier circuit with the cross - design of two capacitors and MOS transistors used in the traditional gate voltage bootstrap switch, and only uses a single first capacitor C1; compared with the traditional gate voltage bootstrap switch, two capacitors are used less, saving the circuit area.

[0048] 2. The present invention improves the linearity of the traditional gate voltage bootstrap switch and reduces harmonic distortion. The present invention analyzes the influence of the input impedance introduced by the pre - stage analog Buffer on the linearity of the output signal of the traditional gate voltage bootstrap switch. By connecting the first resistor Ry in series at the source end of the tenth MOS transistor M10, the first resistor Ry provides negative feedback, reduces the leakage current of the MOS transistor, and improves the linearity of sampling.

[0049] 3. In the conventional gate - voltage - bootstrap switch, the voltage difference between the substrate and the source terminal of the main switching transistor changes with the input signal, which causes the change of the threshold voltage of the main switching transistor, resulting in the on - resistance of the main switch changing with the input signal. In the present invention, the substrate terminal of the main switching transistor is connected to the input signal vin through the source terminal of the twelfth MOS transistor M12, so that the potential difference between the substrate terminal and the source terminal of the twelfth MOS transistor M12 does not change with the input signal, reducing the non - linearity of the on - resistance of the main switching transistor, thereby reducing the harmonic distortion of the sampled signal.

[0050] To verify the linearity of the gate - voltage - bootstrap switch of the present invention, a sample - and - hold circuit as shown in Figure 1 is built. By performing a fast Fourier transform on the sampled output signal, its spectral characteristics and performance parameters related to linearity can be obtained. Table 1 lists the simulation results of the important parameters reflecting the output linearity of the sample - and - hold circuit, namely the spurious - free dynamic range and the total harmonic distortion, under different process corners. It can be found that if only the non - linear error of the bootstrap switch is considered, the linear performance of the modulator output will be much higher than the expected index. Therefore, the non - linearity of the switch will not restrict the overall performance of the modulator.

[0051] Table 1 Simulation results of the linear performance of the improved gate - voltage - bootstrap switch

[0052]

[0053] As shown in Figure 2 , the gate - voltage - bootstrap switch of the present invention is used as the input sampling network of the MASH2 + 2 architecture modulator, and the overall circuit is simulated and analyzed. Using a 5.12 MHz sampling clock, 128 - fold oversampling, that is, a 20 kHz signal bandwidth, a sinusoidal signal with an input frequency of 5.6 kHz and an amplitude of - 3 dBFS is converted. 8192 points are sampled, and the spectrum analysis of the modulator output Yout is performed in MATLAB. The result is as shown in Figure 3 . At this time, the output SNDR of the modulator is 119.5 dB, and the corresponding effective number of bits ENOB is 19.56 bits.

[0054] The principle of a gate - voltage - bootstrap switch of the present invention is as shown in Figure 4 and Figure 6, in the solution of the present invention, the eleventh MOS transistor is the main switching transistor, and the remaining MOS transistors and capacitors are the auxiliary module. When the clock control signal CLK is at a high level, the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned on. The drain voltage of the seventh MOS transistor M7 is low, that is, the gate voltage of the eleventh MOS transistor M11, which is the main switching transistor, is at a low level. The eleventh MOS transistor M11, which is the main switching transistor, is turned off. At this time, the circuit is in a holding state, and the output voltage vout remains unchanged; the first MOS transistor M1, the second MOS transistor M2, and the fifth MOS transistor M5 are turned on to charge the first capacitor C1. After the charging is completed, the voltage difference across the first C1 is approximately equal to the power supply terminal voltage VDD. When the clock control signal CLK is at a low level, the first MOS transistor M1, the seventh MOS transistor M7, and the eighth MOS transistor M8 are turned off; the gate voltages of the fourth MOS transistor M4 and the second MOS transistor M2 are at a high level. The fourth MOS transistor M4 is turned off, and the second MOS transistor M2 is turned on; the gate voltages of the tenth MOS transistor M10 and the eleventh MOS transistor M11 are at a high level. The tenth MOS transistor M10 and the eleventh MOS transistor M11 are turned on. The input signal voltage vin is applied to the lower plate of the first capacitor C1 through the first resistor Ry. Due to the charge sharing effect, the voltage of the upper plate of the first capacitor C1 also increases by vin and becomes VDD + vin. And at this time, the fifth MOS transistor M5 is turned on to transmit this voltage to the gate of the main switching transistor, so that the gate voltage of the eleventh MOS transistor, which is the main switching transistor, is V g＝ VDD + vin, and the source voltage is V s＝ vin, and the difference between the gate voltage and the source voltage is V gs＝ VDD, and the difference between the gate voltage and the source voltage V gs does not change with the change of the input voltage. And at this time, the twelfth MOS transistor M12 is turned on to connect the substrate of the main switch to the input signal vin, so that the potentials of the source end and the substrate end of the main switch are both vin, eliminating the substrate bias effect of the main switching transistor, making the threshold voltage of the main switching transistor not change with the input signal, and further improving the non-linearity of the switch.

[0055] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A gate voltage bootstrap switch, characterized in that: It includes the first MOS tube to the eighth MOS tube, the tenth MOS tube to the twelfth MOS tube, a direction indicator, a first capacitor, a second capacitor, a first resistor, and a second resistor, wherein: The clock control signal is connected to the input end of the inverter, the gate of the first MOS tube, and the gate of the eighth MOS tube. The source of the first MOS tube is grounded, and the drain is connected to one end of the first capacitor, one end of the first resistor, and the sources of the second MOS tube and the third MOS tube. The gate of the second MOS tube is connected with the gate of the fourth MOS tube and the output end of the inverter, and the drain of the second MOS tube is connected with the drains of the fourth MOS tube and the third MOS tube and the gate of the fifth MOS tube; The gate of the third MOS tube is connected with the gate of the eleventh MOS tube and the gate and drain of the twelfth MOS tube; The source of the fourth MOS tube is connected with the source of the sixth MOS tube, the gate of the seventh MOS tube and the power supply terminal; The source of the fifth MOS tube is connected to the other end of the first capacitor and the drain of the sixth MOS tube, and the drain of the fifth MOS tube is connected to the gate of the sixth MOS tube, the gate of the tenth MOS tube and the drain of the seventh MOS tube; The source of the seventh MOS tube is connected to the drain of the eighth MOS tube, and the source of the eighth MOS tube is grounded; The source of the tenth MOS tube is connected to the other end of the first resistor, and the drain of the tenth MOS tube is connected to the source of the eleventh MOS tube and one end of the second resistor; The other end of the second resistor is connected to the input signal end; The drain of the eleventh MOS tube is connected to one end of the second capacitor as an output signal, and the other end of the second capacitor is grounded; The source of the twelfth MOS tube is connected to the input signal terminal.

2. The gate voltage bootstrap switch for Sigma-Delta ADC according to claim 1, characterized in that: When the clock control signal is at a high level, the seventh MOS tube and the eighth MOS tube are turned on, and the eleventh MOS tube is turned off; when the clock control signal is at a low level, the first MOS tube, the seventh MOS tube, the eighth MOS tube are turned off, and the tenth MOS tube and the eleventh MOS tube are turned off.

3. A gate voltage bootstrap switch according to claim 1 or 2, characterized in that: The first MOS tube, the second MOS tube, the third MOS tube, the seventh MOS tube, the eighth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube are N-type MOS tubes; the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are P-type MOS tubes.

4. An application of a gate voltage bootstrap switch, characterized in that: The gate voltage bootstrap switch described in claim 1 is applied to a sample-and-hold circuit.

5. An application of a gate voltage bootstrap switch, characterized in that: The gate voltage bootstrap switch described in claim 1 is used as an input sampling network of a MASH2+2 architecture modulator.

6. An application of a gate voltage bootstrap switch, characterized in that: The gate voltage bootstrap switch described in claim 1 is applied to a Sigma-Delta ADC system.

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