Enhanced GaN HEMT negative voltage driving circuit compatible with common CMOS technology

Abstract

The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) negative voltage driving circuit compatible with a common CMOS (Complementary Metal Oxide Semiconductor) process, which comprises a main driving unit, the input end of the main driving unit is connected with an input signal VIN, the output end of the main driving unit is connected with the grid electrode of an enhanced GaN HEMT, the main driving unit is respectively connected with the output end of a negative voltage generation unit and the output end of an output power tube breakdown prevention unit, and the output power tube breakdown prevention unit is connected with the grid electrode of the enhanced GaN HEMT. The input ends of the negative voltage generation unit and the output power tube breakdown prevention unit are respectively connected with an input signal falling edge detection pulse unit, and the input end of the input signal falling edge detection pulse unit is connected with an input signal VIN. According to the enhanced GaN HEMT negative voltage driving circuit capable of being compatible with the common CMOS technology, the negative voltage generation circuit with the adjustable negative voltage generation duration is introduced, the negative crosstalk voltage is not increased while the positive crosstalk voltage in GaN HEMT half-bridge application is restrained, the situation of different dead zone durations in the GaN HEMT half-bridge application can be dealt with, an output power tube breakdown prevention unit is introduced, and therefore the output power tube breakdown prevention effect is achieved. Therefore, the method can be compatible with a common CMOS technology.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and relates to an enhanced GaN HEMT negative voltage drive circuit that is compatible with ordinary CMOS processes. Background Art

[0002] As a new type of wide bandgap semiconductor material, GaN (gallium nitride) material has a wider bandgap width, a higher critical breakdown electric field, a higher electron saturation rate, and a higher limit operating temperature compared with Si (silicon) material, making it an ideal material for preparing medium and high voltage power devices. In recent years, GaN devices have been more and more widely used in industries such as 5G communication, cloud computing servers, and electric vehicles, which require miniaturization, lightweight, and high efficiency of power modules. However, the higher switching frequency of GaN means larger dv / dt and di / dt, resulting in GaN power devices being more sensitive to the parasitic parameters of the circuit than Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which brings challenges to the design of power converters. For example, the high dv / dt interacts with the Miller capacitance of the complementary side switch, causing a large impact on the gate of the symmetric tube and forming a crosstalk problem.

[0003] In recent years, in view of the crosstalk problem caused by the high-speed conduction of GaN HEMT (High Electron Mobility Transistor) power devices in a bridge circuit, relying on negative voltage to turn off the power device is a commonly used method. However, although negative voltage turn-off suppresses the positive crosstalk voltage, it also exacerbates the negative crosstalk voltage; in addition, the drive of enhanced GaN HEMT requires a gate turn-on voltage of 5V to 6V and a gate turn-off voltage of -3V to 0V. Then, the drive circuit requires a tube with a breakdown voltage of more than 5V, that is, the ordinary 0.5um CMOS process cannot be compatible, and the BCD process is required to complete the design, which makes the layout area of the drive power tube account for a relatively large proportion.

[0004] In summary, the existing negative voltage drive technology for enhanced GaN HEMT has the problem that the negative crosstalk voltage is exacerbated when suppressing the positive crosstalk voltage, and the problem that if the drive technology integrates negative voltage, it cannot be compatible with the ordinary CMOS process. Summary of the Invention

[0005] The purpose of the present invention is to provide an enhanced GaN HEMT negative voltage drive circuit that is compatible with ordinary CMOS processes, which solves the problem that the negative crosstalk voltage is exacerbated when suppressing the positive crosstalk voltage in the prior art, and also solves the problem that if the drive technology integrates negative voltage, it cannot be compatible with the ordinary CMOS process.

[0006] The technical solution adopted by the present invention is an enhanced GaN HEMT negative voltage drive circuit compatible with ordinary CMOS processes, including a main drive unit. The input end of the main drive unit is connected to an input signal V IN , the output end of the main drive unit is connected to the gate of the enhanced GaN HEMT, the main drive unit is respectively connected to the output end of a negative voltage generation unit and the output end of a unit for preventing the output power transistor from breakdown. The input ends of the negative voltage generation unit and the unit for preventing the output power transistor from breakdown are respectively connected to an input signal falling edge detection pulse unit, and the input end of the input signal falling edge detection pulse unit is connected to the input signal V IN connection.

[0007] The features of the present invention also lie in that: The main drive unit includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input end of the inverter chain buffer1 is connected to the input signal V IN connection, the output end of the inverter chain buffer1 is connected to the gate of the output power transistor MP0, and the sources of the inverter chain buffer1 and the output power transistor MP0 are connected to the output end of the unit for preventing the output power transistor from breakdown.

[0008] The pull-down branch includes an inverter chain buffer2 and an output power transistor MN0. The input end of the inverter chain buffer2 is connected to the input signal V IN connection, the output end of the inverter chain buffer2 is connected to the gate of the output power transistor MN0, and the source of the output power transistor MN0 is connected to the low-level end of the inverter chain buffer2 and the output end of the negative voltage generation unit; The input ends of the inverter chain buffer1 and the inverter chain buffer2 are connected, and the drains of the output power transistor MP0 and the output power transistor MN0 are respectively connected to gate resistors and then connected to the gate of the enhanced GaN HEMT.

[0009] The unit for preventing the output power transistor from breakdown includes a second PMOS transistor MP2 and a third NMOS transistor MN3. The source of the second PMOS transistor MP2 is connected to the power supply V DD, the source of the third NMOS transistor MN3 is grounded, the gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected, the gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected to a control signal S3, the drains of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected, and the drain of the second PMOS transistor MP2, the high-level end of the inverter chain buffer1, the drain of the third NMOS transistor MN3, and the source of the output power transistor MP0 are connected.

[0010] The negative voltage generation unit includes a first PMOS transistor MP1, and the source of the first PMOS transistor MP1 is connected to an internal power supply V CC , the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the upper plate of the capacitor C1, the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to a control signal S1.

[0011] The source of the first NMOS transistor MN1 is grounded; the lower plate of the capacitor C1 is respectively connected to the drain of the second NMOS transistor MN2, the source of the output power transistor MN0 in the main drive unit, and the low-level end of the inverter chain buffer2. The gate of the second NMOS transistor MN2 is connected to a control signal S2, and the source of the second NMOS transistor MN2 is grounded and connected to the source of the first NMOS transistor MN1.

[0012] The input signal falling-edge detection pulse unit includes a third PMOS transistor MP3. The source of the third PMOS transistor MP3 is connected to one end of a resistor R, and the other end of the resistor R is connected to a power supply V DD , the source of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is connected to its gate, the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and the drain of the third PMOS transistor MP3 is connected to one end of a current source I, and the other end of the current source I is grounded.

[0013] The drain of the fourth PMOS transistor MP4 is connected to the source of a fifth PMOS transistor MP5. The gate of the fifth PMOS transistor MP5 is connected to the gate of a fourth NMOS transistor MN4. The gate of the fifth PMOS transistor MP5 and the gate of the fourth NMOS transistor MN4 are connected to the input signal V IN is connected; The drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4. The drain of the fifth PMOS transistor MP5 and the drain of the fourth NMOS transistor MN4 are respectively connected to the upper plate of the capacitor C2 and one input terminal of an OR gate or. The other input terminal of the OR gate or is connected to the input signalV IN The output terminal of the connection, OR gate or is the control signal S, and the control signal S includes a control signal S1, a control signal S2, and a control signal S3; the source electrode of the fourth NMOS transistor MN4 and the lower plate of the capacitor C2 are grounded.

[0014] The beneficial effects of the present invention are as follows: by introducing a negative pressure generation circuit with adjustable negative pressure generation duration, the present invention does not require an additional negative pressure power supply. While suppressing the positive crosstalk voltage in the GaN HEMT half-bridge application, the negative crosstalk voltage is not increased, and the duration of negative pressure generation can be adjusted by an off-chip resistor, which can cope with different dead time durations in the GaN HEMT half-bridge application; and a unit for preventing the output power transistor from being broken down is added, and the drive circuit can also be designed under a common CMOS process, solving the breakdown problem caused by the insufficient withstand voltage ability of the output power transistor driven by negative pressure under the common 5V CMOS process, and having good process compatibility. Brief Description of the Drawings

[0015] Figure 1 is a schematic structural diagram of an enhanced GaN HEMT negative pressure drive circuit compatible with a common CMOS process according to the present invention; Figure 2 is a circuit structure diagram of the negative pressure generation unit in the present invention; Figure 3 is a circuit structure diagram of the input signal falling edge detection pulse unit in the present invention; Figure 4 is a schematic diagram of the logical relationship of the control signal in the present invention.

[0016] In the figure, 1, negative pressure generation unit; 2, unit for preventing the output power transistor from being broken down; 3, input signal falling edge detection pulse unit; 4, main drive unit. Detailed Embodiments

[0017] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0018] Embodiment 1 This embodiment proposes an enhanced GaN HEMT negative pressure drive circuit compatible with a common CMOS process, as Figure 1 shown, including a main drive unit 4, the input terminal of the main drive unit 4 is connected to an input signal V IN , the output terminal of the main drive unit 4 is connected to the gate of the enhanced GaN HEMT, the main drive unit 4 is respectively connected to the output terminal of the negative pressure generation unit 1 and the output terminal of the unit for preventing the output power transistor from being broken down 2, the input terminals of the negative pressure generation unit 1 and the unit for preventing the output power transistor from being broken down 2 are respectively connected to the input signal falling edge detection pulse unit 3, and the input terminal of the input signal falling edge detection pulse unit 3 is connected to the input signalV IN Connection

[0019] Embodiment 2 This embodiment proposes an enhanced GaN HEMT negative voltage drive circuit compatible with the ordinary CMOS process, as Figure 1 shown, which includes a main drive unit 4. The input end of the main drive unit 4 is connected with an input signal V IN , the output end of the main drive unit 4 is connected with the gate of the enhanced GaN HEMT. The main drive unit 4 is respectively connected with the output ends of a negative voltage generation unit 1 and an anti-output power transistor breakdown unit 2. The input ends of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2 are respectively connected with an input signal falling edge detection pulse unit 3, and the input end of the input signal falling edge detection pulse unit 3 is connected with the input signal V IN Connection. The main drive unit 4 includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input end of the inverter chain buffer1 is connected with the input signal V IN , the output end of the inverter chain buffer1 is connected with the gate of the output power transistor MP0, and the sources of the inverter chain buffer1 and the output power transistor MP0 are connected with the output end of the anti-output power transistor breakdown unit 2.

[0020] Embodiment 3 This embodiment proposes an enhanced GaN HEMT negative voltage drive circuit compatible with the ordinary CMOS process, as Figure 1 shown, which includes a main drive unit 4. The input end of the main drive unit 4 is connected with an input signal V IN , the output end of the main drive unit 4 is connected with the gate of the enhanced GaN HEMT. The main drive unit 4 is respectively connected with the output ends of a negative voltage generation unit 1 and an anti-output power transistor breakdown unit 2. The input ends of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2 are respectively connected with an input signal falling edge detection pulse unit 3, and the input end of the input signal falling edge detection pulse unit 3 is connected with the input signal V IN Connection.

[0021] The main drive unit 4 includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input end of the inverter chain buffer1 is connected with the input signal V INThe output terminal of the inverter chain buffer1 is connected to the gate of the output power transistor MP0. The sources of the inverter chain buffer1 and the output power transistor MP0 are connected to the output terminal of the anti-output power transistor breakdown unit 2. The pull-down branch includes an inverter chain buffer2 and an output power transistor MN0. The input terminal of the inverter chain buffer2 is connected to the input signal V IN . The output terminal of the inverter chain buffer2 is connected to the gate of the output power transistor MN0. The source of the output power transistor MN0 is connected to the low-level end of the inverter chain buffer2 and the output terminal of the negative voltage generation unit 1. The input terminals of the inverter chain buffer1 and the inverter chain buffer2 are connected. The drains of the output power transistor MP0 and the output power transistor MN0 are respectively connected to gate resistors and then connected to the gate of the enhancement-mode GaN HEMT.

[0022] Embodiment 4 This embodiment proposes an enhancement-mode GaN HEMT negative voltage drive circuit compatible with the ordinary CMOS process, as Figure 1 shown, which includes a main drive unit 4. The input terminal of the main drive unit 4 is connected to an input signal V IN . The output terminal of the main drive unit 4 is connected to the gate of the enhancement-mode GaN HEMT. The main drive unit 4 is respectively connected to the output terminals of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2. The input terminals of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2 are respectively connected to an input signal falling-edge detection pulse unit 3. The input terminal of the input signal falling-edge detection pulse unit 3 is connected to the input signal V IN connection.

[0023] The main drive unit 4 includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input terminal of the inverter chain buffer1 is connected to the input signal V IN . The output terminal of the inverter chain buffer1 is connected to the gate of the output power transistor MP0. The sources of the inverter chain buffer1 and the output power transistor MP0 are connected to the output terminal of the anti-output power transistor breakdown unit 2. The pull-down branch includes an inverter chain buffer2 and an output power transistor MN0. The input terminal of the inverter chain buffer2 is connected to the input signal V INThe output terminal of the inverter chain buffer2 is connected to the gate of the output power transistor MN0. The source of the output power transistor MN0 is connected to the low-level terminal of the inverter chain buffer2 and the output terminal of the negative voltage generation unit 1. The input terminals of the inverter chain buffer1 and the inverter chain buffer2 are connected. The drains of the output power transistor MP0 and the output power transistor MN0 are respectively connected to gate resistors and then connected to the gate of the enhancement-mode GaN HEMT.

[0024] Combined Figure 2 As shown, the anti-output power transistor breakdown unit 2 includes a second PMOS transistor MP2 and a third NMOS transistor MN3. The source of the second PMOS transistor MP2 is connected to the power supply V DD , the source of the third NMOS transistor MN3 is grounded. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. A control signal S3 is connected to the gates of the second PMOS transistor MP2 and the third NMOS transistor MN3. The drains of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. The drain of the second PMOS transistor MP2, the high-level terminal of the inverter chain buffer1, the drain of the third NMOS transistor MN3, and the source of the output power transistor MP0 are connected.

[0025] Embodiment 5 This embodiment proposes an enhancement-mode GaN HEMT negative voltage drive circuit that is compatible with the ordinary CMOS process. As Figure 1 shown, it includes a main drive unit 4. The input terminal of the main drive unit 4 is connected to an input signal V IN , the output terminal of the main drive unit 4 is connected to the gate of the enhancement-mode GaN HEMT. The main drive unit 4 is respectively connected to the output terminal of the negative voltage generation unit 1 and the output terminal of the anti-output power transistor breakdown unit 2. The input terminals of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2 are respectively connected to an input signal falling-edge detection pulse unit 3. The input terminal of the input signal falling-edge detection pulse unit 3 is connected to the input signal V IN connection.

[0026] The main drive unit 4 includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input terminal of the inverter chain buffer1 is connected to the input signal V IN connection. The output terminal of the inverter chain buffer1 is connected to the gate of the output power transistor MP0. The inverter chain buffer1 and the source of the output power transistor MP0 are connected to the output terminal of the anti-output power transistor breakdown unit 2. The pull-down branch includes an inverter chain buffer2 and an output power transistor MN0. The input terminal of the inverter chain buffer2 is connected to the input signalV IN The output terminal of the inverter chain buffer2 is connected to the gate of the output power transistor MN0. The source of the output power transistor MN0 is connected to the low-level end of the inverter chain buffer2 and the output terminal of the negative voltage generation unit 1. The input terminals of the inverter chain buffer1 and the inverter chain buffer2 are connected. The drains of the output power transistor MP0 and the output power transistor MN0 are respectively connected to gate resistors and then connected to the gate of the enhancement-mode GaN HEMT.

[0027] Combined Figure 2 As shown, the anti-output power transistor breakdown unit 2 includes a second PMOS transistor MP2 and a third NMOS transistor MN3. The source of the second PMOS transistor MP2 is connected to the power supply V DD , the source of the third NMOS transistor MN3 is grounded. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected to a control signal S3. The drains of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. The drain of the second PMOS transistor MP2, the high-level end of the inverter chain buffer1, the drain of the third NMOS transistor MN3, and the source of the output power transistor MP0 are connected.

[0028] The negative voltage generation unit 1 includes a first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to an internal power supply V CC , the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the upper plate of the capacitor C1. The gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1. The gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to a control signal S1. The source of the first NMOS transistor MN1 is grounded; the lower plate of the capacitor C1 is respectively connected to the drain of the second NMOS transistor MN2, the source of the output power transistor MN0 in the main driving unit 4, and the low-level end of the inverter chain buffer2. The gate of the second NMOS transistor MN2 is connected to a control signal S2. The source of the second NMOS transistor MN2 is grounded and connected to the source of the first NMOS transistor MN1.

[0029] Embodiment 6 This embodiment proposes an enhancement-mode GaN HEMT negative voltage driving circuit compatible with the ordinary CMOS process. As Figure 1 shown, it includes a main driving unit 4. The input terminal of the main driving unit 4 is connected to an input signal V IN, the output terminal of the main drive unit 4 is connected to the gate of the enhanced GaN HEMT. The main drive unit 4 is respectively connected to the output terminal of the negative voltage generation unit 1 and the output terminal of the anti-output power transistor breakdown unit 2. The input terminals of the negative voltage generation unit 1 and the anti-output power transistor breakdown unit 2 are respectively connected to the input signal falling edge detection pulse unit 3, and the input terminal of the input signal falling edge detection pulse unit 3 is connected to the input signal V IN connected.

[0030] The main drive unit 4 includes a pull-up branch and a pull-down branch. The pull-up branch includes an inverter chain buffer1 and an output power transistor MP0. The input terminal of the inverter chain buffer1 is connected to the input signal V IN connected. The output terminal of the inverter chain buffer1 is connected to the gate of the output power transistor MP0. The source electrodes of the inverter chain buffer1 and the output power transistor MP0 are connected to the output terminal of the anti-output power transistor breakdown unit 2. The pull-down branch includes an inverter chain buffer2 and an output power transistor MN0. The input terminal of the inverter chain buffer2 is connected to the input signal V IN connected. The output terminal of the inverter chain buffer2 is connected to the gate of the output power transistor MN0. The source electrode of the output power transistor MN0 is connected to the low-level end of the inverter chain buffer2 and the output terminal of the negative voltage generation unit 1; the input terminals of the inverter chain buffer1 and the inverter chain buffer2 are connected. The drain electrodes of the output power transistor MP0 and the output power transistor MN0 are respectively connected to gate resistors and then connected to the gate of the enhanced GaN HEMT.

[0031] Combined Figure 2 As shown, the anti-output power transistor breakdown unit 2 includes a second PMOS transistor MP2 and a third NMOS transistor MN3. The source electrode of the second PMOS transistor MP2 is connected to the power supply V DD , the source electrode of the third NMOS transistor MN3 is grounded. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected to a control signal S3. The drains of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected. The drain of the second PMOS transistor MP2, the high-level end of the inverter chain buffer1, the drain of the third NMOS transistor MN3, and the source electrode of the output power transistor MP0 are connected.

[0032] The negative voltage generation unit 1 includes a first PMOS transistor MP1. The source electrode of the first PMOS transistor MP1 is connected to an internal power supply V CC, the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the upper plate of the capacitor C1. The gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and a control signal S1 is connected between the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is grounded; the lower plate of the capacitor C1 is respectively connected to the drain of the second NMOS transistor MN2, the source of the output power transistor MN0 in the main driving unit 4, and the low-level end of the inverter chain buffer2. The gate of the second NMOS transistor MN2 is connected with a control signal S2, and the source of the second NMOS transistor MN2 is grounded and connected to the source of the first NMOS transistor MN1.

[0033] Combined with Figure 3 As shown, the input signal falling-edge detection pulse unit 3 includes a third PMOS transistor MP3. One end of a resistor R is connected to the source of the third PMOS transistor MP3, and the other end of the resistor R is connected to a power supply V DD , the source of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is connected to its gate, the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and one end of a current source I is connected to the drain of the third PMOS transistor MP3, and the other end of the current source I is grounded. The drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5. The gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth NMOS transistor MN4. The gate of the fifth PMOS transistor MP5 and the gate of the fourth NMOS transistor MN4 are connected to the input signal V IN connected; the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4. The drain of the fifth PMOS transistor MP5 and the drain of the fourth NMOS transistor MN4 are respectively connected to the upper plate of the capacitor C2 and one input terminal of the OR gate or. The other input terminal of the OR gate or is connected to the input signal V IN connected, and the output terminal of the OR gate or is the control signal S. The control signal S includes the control signal S1, the control signal S2, and the control signal S3; the source of the fourth NMOS transistor MN4 and the lower plate of the capacitor C2 are grounded.

[0034] The enhanced GaN HEMT negative voltage driving circuit compatible with the ordinary CMOS process in the embodiment of the present invention, as Figure 1 shown, includes a negative voltage generation unit 1, an anti-output power transistor breakdown unit 2, an input signal falling-edge detection pulse unit 3, and a main driving unit 4.

[0035] The output voltage of the enhanced GaN HEMT negative voltage driving circuit compatible with the ordinary CMOS process V GLThere are three levels. The high level is V DD , which is the turn-on voltage of the GaN HEMT. The low level is - V CC and 0V, which are the turn-off voltages of the GaN HEMT, and the holding duration of - V CC can be adjusted by an external resistor; Among them V DD is the input power supply of the driving circuit of the present invention, generally 5V or 6V for the GaN HEMT; V CC is the internal power supply of the driving circuit, which can be generated by an LDO (low dropout regulator). The value of the internal power supply V CC is equal to the absolute value of the required negative voltage value V EE , generally 2V or 3V for the GaN HEMT.

[0036] The output terminal of the negative voltage generation unit 1 V EE is connected to the pull-down branch in the main driving unit 4, replacing the traditional driving scheme of turning off the enhancement-mode GaN HEMT with 0V. It can autonomously generate a negative voltage and turn off the power device with the negative voltage, suppressing the crosstalk problem caused by the high dv / dt during the half-bridge switching of the GaN HEMT; at the same time, it can also select V EE to switch between zero voltage and negative voltage by changing the input logic of the negative voltage generation unit.

[0037] The output terminal of the anti-output power transistor breakdown unit 2 V SW is connected to the pull-up branch in the main driving unit. When V GL is a negative voltage, it is used to pull the source voltage of the output power transistor MP0 in the pull-up branch of the main driving unit 4, that is V SW to 0V to prevent the source-drain withstand voltage of MP0 from being insufficient and breakdown. At other times, the source voltage of MP0 V SW is normally pulled to V DD .

[0038] The output signal of the main driving unit 4 is V GL, the output power transistor MP0 and the output power transistor MN0 serve as the output power transistors of the pull-up branch and the pull-down branch respectively, providing pull current and sink current for the gate of the GaN HEMT, and the gates of MP0 and MN0 need to be driven by the optimized inverter chain buffer1 and inverter chain buffer2 respectively.

[0039] Combined with Figure 2 As shown, the negative voltage generation unit 1 is respectively connected to the source of the output power transistor MN0 and the inverter chain buffer2 in the main drive unit, and its function is to generate a negative voltage, replacing the traditional 0V turn-off driving scheme for the enhancement-mode GaN HEMT, and without using an additional negative voltage power supply, suppressing the crosstalk problem caused by the high dv / dt during the half-bridge switching of the GaN HEMT.

[0040] The output power transistor breakdown prevention unit 2 is connected to the source of the output power transistor MP0 and the inverter chain buffer1 in the main drive unit 4. When the output signal V GL is a negative voltage, it is used to pull the source voltage of the output power transistor MP0 V SW to GND, that is, 0V, to prevent the output power transistor MP0 from breaking down due to insufficient source-drain withstand voltage. At other times, the source voltage of the output power transistor MP0 V SW is normally pulled to V DD .

[0041] Combined with Figure 3 As shown, the input signal falling edge detection pulse unit 3 is used to detect the falling edge of the input signal V IN and output a control signal S with adjustable pulse width. The control signal S serves as the input of the negative voltage generation unit 1 and the output power transistor breakdown prevention unit 2 respectively. During the turn-off period of the GaN HEMT, it is turned off with a negative voltage when a positive dv / dt occurs, that is, S outputs a low level; after the positive dv / dt occurs and before the negative dv / dt occurs, it resumes to be turned off with the traditional zero voltage, that is, S outputs a high level, suppressing the positive crosstalk voltage in the half-bridge application of the GaN HEMT without increasing the negative crosstalk voltage.

[0042] The negative voltage generation unit 1 includes a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, and a capacitor C1; the source of the first PMOS transistor MP1 is connected to the internal power supply V CC, the gate is connected to the gate of the first NMOS transistor MN1 and is controlled by the control signal S1. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and is connected to the upper plate of the capacitor C1; the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded together to GND; the gate of the second NMOS transistor MN2 is controlled by the control signal S2, and the drain is connected to the lower plate of the capacitor C1; the lower plate of the capacitor C1 is the output voltage of the negative voltage generation unit 1 V EE , and is connected to the source of the output power transistor MN0 in the main drive unit 4 and the low-level end of the inverter chain buffer2.

[0043] The internal power supply in the negative voltage generation unit 1 V CC can be generated by the LDO inside the drive chip. The internal power supply V CC value is equal to the absolute value of the negative voltage to be generated V EE For GaN HEMT, it is generally 2V or 3V; the first PMOS transistor MP1, the first NMOS transistor MN1, and the second NMOS transistor MN2 are all power transistors with larger sizes and charge and discharge the capacitor C1, so their gates all require optimized inverter chain drives; the capacitor C1 is an off-chip capacitor and its value is in the nF level.

[0044] Combined Figure 4 As shown, the control signal S1 and the control signal S2 are opposite logic levels and both come from the control signal S output by the input signal falling edge detection pulse unit 3. When the control signal S1 is at a low level and the control signal S2 is at a high level, the upper plate of the capacitor C1 is charged to the internal power supply V CC through the first PMOS transistor MP1, and the lower plate of the capacitor C1 is pulled to GND, that is, 0V by the second NMOS transistor MN2; when the control signal S1 is at a high level and the control signal S2 is at a low level, the upper plate of the capacitor C1 is discharged to GND, that is, 0V through the first NMOS transistor MN1. Since the voltage value across the capacitor C1 cannot change suddenly, a negative voltage appears at the lower plate of the capacitor C1 at this time V EE and the negative voltage value is - V CC . Therefore, the output of the negative voltage generation circuit can be controlled by the logic levels of the control signal S1 and the control signal S2 V EE to switch between 0V and - V CC , so that the low level of the output signal V GL can be between 0V and - VCC Switch between.

[0045] The second NMOS transistor MN2 is an NMOS transistor with a deep N-well. The substrate of the second NMOS transistor MN2 needs to be connected to the drain, that is V EE At this point, the high and low levels of the gate control signal S2 of the second NMOS transistor MN2 need to be shifted from the ordinary 0~5V level to - V CC ~5- V CC So as to normally control the turn-on and turn-off of MN2. V EE It is necessary to generate after the V GL voltage has a downward trend and before it V GL drops to the lowest voltage, so that the drain-source breakdown voltage of MN0 will not exceed the maximum breakdown voltage, and V GL there is a negative voltage available.

[0046] The output power transistor breakdown prevention unit 2 includes a second PMOS transistor MP2 and a third NMOS transistor MN3; the source of the second PMOS transistor MP2 is connected to the power supply V DD The gate is connected to the gate of the third NMOS transistor MN3 and is controlled by the control signal S3; the source of the third NMOS transistor MN3 is connected to the ground GND, and the drains of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected together as the output end of the output power transistor breakdown prevention unit 2, and are connected to the source of the output power transistor MP0 and the high-level end of the inverter chain buffer1.

[0047] The driving level of the GaN HEMT is between 5~6V. Considering the compatibility of the ordinary CMOS process, the power supply V DD is generally 5V; the second PMOS transistor MP2 and the third NMOS transistor MN3 are both power transistors with larger sizes, and the source level of the output power transistor MP0 is V DD switched between and GND, so the gates all require optimized inverter chain drive.

[0048] The principle of the output power transistor breakdown prevention unit 2 is combined with Figure 1 and Figure 4 As shown, the second PMOS transistor MP2 and the third NMOS transistor MN3 are equivalent to a single-pole double-throw switch, and can select V SW At V DDSwitching between and GND, so the size needs to be designed large to ensure fast switching speed and not affect the original pulling current magnitude. In addition, when the control signal S1 is high, the control signal S2 is low, and the output of the negative voltage generation unit 1 is negative voltage, that is V GL At this time, when it is negative voltage, to avoid the source-drain voltage value of the output power transistor MP0 being V DD - V EE greater than V DD the breakdown voltage of this problem, the control signal S3 needs to be at a high level, and V SW is pulled to GND, that is 0V through the third NMOS transistor MN3; when the output of the negative voltage generation unit 1 is 0V, the control signal S3 needs to be at a low level, V SW is normally pulled to V DD .

[0049] V SW The falling edge of needs to be generated after the voltage of has a downward trend and before V GL otherwise, within the small dead time generated by the output power transistor MP0 and the output power transistor MN0, the level that should have been maintained at V GL will discharge to GND through the output power transistor MP0 and the third NMOS transistor MN3. V EE The input signal falling edge detection pulse unit 3 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a capacitor C2, a resistor R, a current source I, and an OR gate or; the gate and drain of the third PMOS transistor MP3 are connected together and connected to the gate of the fourth PMOS transistor MP4, the drain of the third PMOS transistor MP3 is connected to the current source I, and the source of the third PMOS transistor MP3 is connected to the resistor R; the fourth PMOS transistor MP4 and the other end of the resistor R are connected to the power supply V DD level V GL will discharge to GND through the output power transistor MP0 and the third NMOS transistor MN3.

[0050] The input signal falling edge detection pulse unit 3 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a capacitor C2, a resistor R, a current source I, and an OR gate or; the gate and drain of the third PMOS transistor MP3 are connected together and connected to the gate of the fourth PMOS transistor MP4, the drain of the third PMOS transistor MP3 is connected to the current source I, and the source of the third PMOS transistor MP3 is connected to the resistor R; the fourth PMOS transistor MP4 and the other end of the resistor R are connected to the power supply V DD, the drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5; the gates of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are connected together as the input terminal of the input signal falling edge detection pulse unit 3, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4, the upper plate of the capacitor C2, and one input terminal of the OR gate or; the source of the fourth NMOS transistor MN4 and the lower plate of the capacitor C2 are grounded together to GND; the other input terminal of the OR gate or is the input signal V IN , the output of the OR gate or is the output signal of the input signal falling edge detection pulse unit 3, and this output signal is transmitted as a control signal to the subsequent anti-output power transistor breakdown unit 2 and the negative voltage generation unit 1.

[0051] If the resistor R in the input signal falling edge detection pulse unit 3 is set as an off-chip resistor, its resistance value is adjustable, so that the input signal V IN The pulse width of the control signal S output by the input signal falling edge detection pulse unit 3 can be adjusted, so that the duration of the generated negative voltage can be arbitrarily adjusted according to needs by adjusting the resistance value of the off-chip resistor.

[0052] The main drive unit 4 includes an output power transistor MP0 and an output power transistor MN0, as well as an inverter chain buffer1 and an inverter chain buffer2; the inverter chain buffer1 drives the gate of the output power transistor MP0, and the inverter chain buffer2 drives the gate of the output power transistor MN0; the output signal of the main drive unit 4 is V GL . The inverter chain buffer1 and the inverter chain buffer2 adopt an optimized inverter chain; gate resistors for driving GaN HEMT need to be added to the drains of the output power transistor MP0 and the output power transistor MN0 respectively.

Claims

1. An enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process, characterized in that: It comprises a main drive unit (4), the input end of the main drive unit (4) being connected to an input signal V IN The output end of the main driving unit (4) is connected to the gate of the enhanced GaN HEMT, the main driving unit (4) is respectively connected to the output end of the negative voltage generating unit (1) and the output end of the output power tube breakdown prevention unit (2), the input ends of the negative voltage generating unit (1) and the output power tube breakdown prevention unit (2) are respectively connected to the input signal falling edge detection pulse unit (3), and the input end of the input signal falling edge detection pulse unit (3) is connected to the input signal V IN connect.

2. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 1, characterized in that: The main driving unit (4) comprises a pull-up branch and a pull-down branch, the pull-up branch comprises an inverter chain buffer 1 and an output power tube MP0, the input end of the inverter chain buffer 1 is connected to the input signal V IN The output end of the inverter chain buffer1 is connected to the gate of the output power tube MP0, and the source of the inverter chain buffer1 and the output power tube MP0 is connected to the output end of the output power tube breakdown prevention unit (2).

3. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 2, characterized in that: The pull-down branch includes an inverter chain buffer2 and an output power tube MN0. The input end of the inverter chain buffer2 is connected to the input signal V IN The output end of the inverter chain buffer2 is connected to the gate of the output power tube MN0, and the source of the output power tube MN0 is connected to the low level end of the inverter chain buffer2 and the output end of the negative voltage generating unit (1); The input ends of the inverter chain buffer1 and the inverter chain buffer2 are connected, and the drain of the output power tube MP0 and the drain of the output power tube MN0 are respectively connected to the gate resistor and then connected to the gate of the enhanced GaN HEMT.

4. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 3, characterized in that: The output power tube breakdown prevention unit (2) comprises a second PMOS tube MP2 and a third NMOS tube MN3, wherein the source of the second PMOS tube MP2 is connected to the power supply V DD The source of the third NMOS tube MN3 is grounded, the gates of the second PMOS tube MP2 and the third NMOS tube MN3 are connected, the gates of the second PMOS tube MP2 and the third NMOS tube MN3 are connected with a control signal S3, the drains of the second PMOS tube MP2 and the third NMOS tube MN3 are connected, and the drain of the second PMOS tube MP2, the high level end of the inverter chain buffer1, the drain of the third NMOS tube MN3 and the source of the output power tube MP0 are connected.

5. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 4, characterized in that: The negative pressure generating unit (1) comprises a first PMOS tube MP1, the source of which is connected to an internal power source. V CC The drain of the first PMOS tube MP1 is respectively connected to the drain of the first NMOS tube MN1 and the upper plate of the capacitor C1, the gate of the first PMOS tube MP1 is connected to the gate of the first NMOS tube MN1, and the gate of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 are connected to the control signal S1.

6. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 5, characterized in that: The source of the first NMOS transistor MN1 is grounded; the lower plate of the capacitor C1 is respectively connected to the drain of the second NMOS transistor MN2, the source of the output power transistor MN0 in the main drive unit (4), and the low level end of the inverter chain buffer2; the gate of the second NMOS transistor MN2 is connected to the control signal S2; the source of the second NMOS transistor MN2 is grounded and connected to the source of the first NMOS transistor MN1.

7. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 6, characterized in that: The input signal falling edge detection pulse unit (3) comprises a third PMOS tube MP3, the source of the third PMOS tube MP3 is connected to one end of a resistor R, and the other end of the resistor R is connected to a power supply V DD , the source of the fourth PMOS tube MP4, the drain of the third PMOS tube MP3 is connected to the gate, the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, the drain of the third PMOS tube MP3 is connected to one end of the current source I, and the other end of the current source I is grounded.

8. The enhanced GaN HEMT negative voltage driving circuit compatible with ordinary CMOS process according to claim 7, characterized in that: The drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, the gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth NMOS transistor MN4, and the gates of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are connected to the input signal V IN connect; The drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4. The drain of the fifth PMOS transistor MP5 and the drain of the fourth NMOS transistor MN4 are respectively connected to the upper plate of the capacitor C2 and one input end of the OR gate or. The other input end of the OR gate or is connected to the input signal V IN The output end of the OR gate or is a control signal S, and the control signal S includes a control signal S1, a control signal S2, and a control signal S3; the source of the fourth NMOS tube MN4 and the lower plate of the capacitor C2 are grounded.

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