Substrate and electronic device

Abstract

The invention provides a substrate and an electronic device. The substrate comprises a first surface layer, and an external cable is arranged on the first surface layer; in the first direction, the external cable is arranged close to the first end of the first surface layer, the external cable comprises a plurality of cable conductors, the plurality of cable conductors extend along the first direction and are arranged at intervals along the second direction, one of the plurality of cable conductors is a grounding cable conductor, and the grounding cable conductor is arranged close to the third end; the first surface layer is also provided with a first ground copper foil connected with a ground cable; the first inner layer is adjacent to the first surface layer, the first inner layer is provided with a power supply copper foil, and the power supply copper foil is electrically connected with the BUCK power supply module; in the direction perpendicular to the substrate, the projection of the power supply copper foil is located in the projection range of the grounding cable and the first grounding copper foil. The projection of the power supply copper foil in the first inner layer is arranged in the projection range of the grounding cable and the first grounding copper foil on the first surface layer, so that mutual interference between an electronic element connected with the power supply copper foil and an external cable is reduced.

Description

Technical Field

[0001] The present application relates to communication technologies, and particularly to a substrate and an electronic device. Background Art

[0002] A substrate is a main component in an electronic device, and its main function is to provide connection and support for various electronic components to realize the functions of a circuit. For example, an external cable can be arranged on the substrate to realize connection with external devices, and a BUCK power module can be arranged to realize conversion and distribution of electric energy.

[0003] In the solutions of related technologies, the setting position of a power copper foil connected to a BUCK power module is poor, resulting in mutual interference between the electronic components connected to the power copper foil and the external cable. Summary of the Invention

[0004] To overcome the above defects in related technologies, the purpose of the present application is to provide a substrate and an electronic device, which are beneficial to reducing the mutual interference between the electronic components connected to the power copper foil and the external cable.

[0005] On the one hand, the present application provides a substrate, including a first surface layer, on which an external cable is arranged for connecting to an external device; the first surface layer includes a first end and a second end opposite to each other in a first direction and a third end and a fourth end opposite to each other in a second direction. In the first direction, the external cable is arranged close to the first end of the first surface layer. The external cable includes a plurality of cable lines, and the plurality of cable lines all extend in the first direction and are arranged at intervals in the second direction. One of the plurality of cable lines is a grounding cable line, and the grounding cable line is arranged close to the third end; a first ground copper foil connected to the grounding cable line is further arranged on the first surface layer;

[0006] a first inner layer adjacent to the first surface layer, on which a power copper foil is arranged and is electrically connected to a BUCK power module for supplying power to the electronic components on the substrate;

[0007] In the direction perpendicular to the substrate, the projection of the power copper foil is located within the projection ranges of the grounding cable line and the first ground copper foil.

[0008] In a possible implementation manner, a second surface layer is further included. In the direction perpendicular to the substrate, the second surface layer is arranged opposite to the first surface layer; the BUCK power module is arranged on the second surface layer and is electrically connected to the power copper foil through a power via.

[0009] In a possible implementation, it further includes a second inner layer adjacent to the second surface layer, and a second ground copper foil is provided on the second inner layer; other components are also provided on the second surface layer. In the direction perpendicular to the substrate, the projection of the other components is within the projection range of the power supply copper foil, and the projections of the other components and the power supply copper foil are both within the projection range of the second ground copper foil.

[0010] In a possible implementation, the other components include a power supply trace, a signal trace, or an R232 module.

[0011] In a possible implementation, a third ground copper foil is further provided on the first inner layer, and the third ground copper foil is located on the side of the power supply copper foil facing the fourth end; in the direction perpendicular to the substrate, except for the ground cable, the projections of multiple cables are all within the projection range of the third ground copper foil.

[0012] In a possible implementation, a grounding component is further provided on the first inner layer, and the grounding component is located on the side of the power supply copper foil facing the third end, and the power supply copper foil is electrically connected to the first ground copper foil and the second ground copper foil.

[0013] In a possible implementation, the grounding component includes a ground copper foil or a ground wire.

[0014] In a possible implementation, the grounding component is a ground wire, and a plurality of ground vias are provided on the ground wire, and the ground wire is electrically connected to the first ground copper foil and the second ground copper foil through the plurality of ground vias.

[0015] In a possible implementation, an external connector is further provided on the first surface layer, and the external cable is connected to the external connector.

[0016] On the other hand, the present application provides an electronic device including the substrate as described in any one of the above.

[0017] The present application provides a substrate and an electronic device. The substrate includes a first surface layer, on which an external cable is provided for connecting to an external device. The first surface layer includes a first end and a second end opposite to each other in a first direction, and a third end and a fourth end opposite to each other in a second direction. In the first direction, the external cable is disposed close to the first end of the first surface layer. The external cable includes a plurality of cable lines, all of which extend in the first direction and are spaced apart in the second direction. One of the plurality of cable lines is a ground cable line, which is disposed close to the third end. A first ground copper foil connected to the ground cable line is also provided on the first surface layer. A first inner layer is adjacent to the first surface layer and is provided with a power copper foil, which is electrically connected to a BUCK power module and is used to supply power to electronic components on the substrate. In a direction perpendicular to the substrate, the projection of the power copper foil is within the projection ranges of the ground cable line and the first ground copper foil on the first surface layer. By disposing the projection of the power copper foil in the first inner layer within the projection ranges of the ground cable line and the first ground copper foil on the first surface layer, the present application reduces the mutual interference between the electronic components connected to the power copper foil and the external cable. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a schematic structural diagram of a substrate in the related art;

[0020] Figure 2 is Figure 1 a cross-sectional view of the substrate at the position of the external connector in [reference];

[0021] Figure 3 is a schematic structural diagram of a substrate provided by an embodiment of the present application;

[0022] Figure 4 is a cross-sectional view of the pulsed magnetic field at a position on the substrate of an external connector and a BUCK power module provided by an embodiment of the present application;

[0023] Figure 5 is a cross-sectional view of the pulsed magnetic field at another position on the substrate of an external connector and a BUCK power module provided by an embodiment of the present application;

[0024] Figure 6 is a cross-sectional view of the pulsed electric field at a position on the substrate of an external connector and a BUCK power module provided by an embodiment of the present application;

[0025] Figure 7 A cross-sectional view of the pulse electric field at another position on the substrate of the external connector and the BUCK power module provided by an embodiment of the present application;

[0026] Figure 8 A cross-sectional view of the magnetic field at a position on the substrate of the MOSFET power switch provided by an embodiment of the present application;

[0027] Figure 9 A cross-sectional view of the pulse electric field at a position on the substrate of the MOSFET power switch provided by an embodiment of the present application;

[0028] Figure 10 A cross-sectional view of the magnetic field at another position on the substrate of the MOSFET power switch provided by an embodiment of the present application;

[0029] Figure 11 A cross-sectional view of the pulse electric field at another position on the substrate of the MOSFET power switch provided by an embodiment of the present application;

[0030] Figure 12 A cross-sectional view of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil along one direction provided by an embodiment of the present application;

[0031] Figure 13 A cross-sectional view of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil along another direction provided by an embodiment of the present application. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application.

[0033] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0034] Such as Figure 1 and Figure 2As shown in the figure, in the related technology solution, an external cable 74 is provided on the first surface at position A of the substrate. The cable is connected to an external connector on the first surface. The pad definition order of the external connector is divided into pad 1 from left to right: connected to the GND of the external cable 74; pad 2: connected to the input power supply VIN of the external cable 74; pad 3: connected to the SENSE pin of the external cable 74; pad 4: connected to the CAM-L of the external cable 74; pad 5: connected to the CAM-H of the external cable 74; pad 6: connected to the V_OUT1 of the external cable 74; pad 7: connected to the V_OUT2 of the external cable 74; pad 8: connected to the V_OUT3 of the external cable 74; pad 9: connected to the V_OUT4 of the external cable 74.

[0035] An external cable 74 and an external connector 69 are provided on the first surface of the substrate. A BUCK power module, an LDO1 module, an LDO2 module, an LDO3 module, a bead 1, and a bead 2 are provided on the second surface at the position of the external cable 74.

[0036] The output capacitor (set on the second surface) of the BUCK power module leads out to the Vcc copper foil on the second surface, and is respectively connected to the input ends of the LDO1 module, the LDO2 module, the LDO3 module, one end pad of the bead 1, and one end pad of the bead 2 through the Vcc copper foil; the output ends of the LDO1 module, the LDO2 module, and the LDO3 module respectively lead out vias 5, 3, and 4; if a power trace Vo2 is set on the second layer of via 5, a power trace Vo6 power trace is set on the second layer of via 3, and a power trace Vo4 power trace is set on the second layer of via 4. Vias 1 and 2 are respectively led out from the other end pads of the bead 1 and the bead 2.

[0037] A Vo1 power trace is set on the second layer of via 1, a Vo2 power trace is set on the second layer of via 5, a Vo3 power trace is set on the second layer of via 6, a Vo4 power trace is set on the second layer of via 4, a Vo6 power trace is set on the second layer of via 6, and a Vo5 power trace is set on the second layer of via 2. If all power traces are set on the second layer, then all the power traces on the second layer will be adjacent to all the pads of the external connector on the first surface. The input voltage of pad 2 of the external connector is as high as 8 - 100V, and it is also necessary to perform 200V - 500V surge tests (the 200V surge test corresponds to the 24V engine surge test including the engine, and the 500V surge test corresponds to the 48V - 72V electric bicycle and electric motorcycle surge tests). The 6th, 7th, 8th, and 9th pads of the external connector output 4 channels of 8 - 100V power respectively after the 8 - 100V power in pad 2 of the external connector is controlled by 4 - way switches.

[0038] The Vo1 power trace on the second layer is adjacent to the pad of pin 2 of the external connector. The pad of pin 2 of the external connector contains a power supply of 8 - 100V, a surge of 200V - 500V, power supply noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo1 power trace on the second layer is not a GND plane. The 8 - 100V power supply, the surge of 200V - 500V, noise, and 8KV static electricity in the pad of pin 2 on the first surface layer will all be coupled to the Vo1 power trace on the second layer. The Vo1 power trace on the second layer supplies power to the Bluetooth module, and the Bluetooth module will be interfered by the 8 - 100V power supply, the surge of 200V - 500V, noise, and 8KV static electricity. If the Bluetooth module generates noise, it will also be coupled to the pad of pin 2 of the external connector on the first surface layer, and then taken out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0039] The Vo2 power trace on the second layer is adjacent to the pad of pin 3 of the external connector. The pad of pin 3 of the external connector contains noise and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo2 power trace on the second layer is not a GND plane. The noise and 8KV static electricity in the pad of pin 2 on the first surface layer will all be coupled to the Vo2 power trace on the second layer. The Vo2 power trace on the second layer supplies power to the MCU module, and the MCU module will be interfered by noise and 8KV static electricity. If the MCU module generates noise, it will also be coupled to the pad of pin 3 of the external connector on the first surface layer, and then taken out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0040] The Vo3 power trace on the second layer is adjacent to the pad of pin 4 of the external connector. The pad of pin 4 of the external connector contains noise and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo3 power trace on the second layer is not a GND plane. The noise and 8KV static electricity in the pad of pin 3 on the first surface layer will all be coupled to the Vo3 power trace on the second layer. The Vo3 power trace on the second layer supplies power to the LTE module, and the MCU module will be interfered by noise and 8KV static electricity. If the LTE module generates noise through the Vo3 power trace, it will also be coupled to the pad of pin 4 of the external connector on the first surface layer, and then taken out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0041] The Vo4 power trace on the second layer is adjacent to the pad of pin 6 of the external connector, and the pad of pin 6 of the external connector contains a power supply of 8 - 100V, power supply noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo4 power trace on the second layer is not a GND plane. The 8 - 100V power supply, noise, and 8KV static electricity in the pad of pin 6 on the first surface layer will all be coupled to the Vo4 power trace on the second layer. And the Vo4 power trace on the second layer supplies power to the LTE module. When the LTE module is powered, it will be interfered by noise and 8KV static electricity; if the noise generated by the LTE module through the Vo4 power trace, it will also be coupled to the pad of pin 6 of the external connector on the first surface layer, and then carried out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0042] The Vo6 power trace on the second layer is adjacent to the pad of pin 7 of the external connector, and the pad of pin 7 of the external connector contains a power supply of 8 - 100V, power supply noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo6 power trace on the second layer is not a GND plane. The 8 - 100V power supply, power supply noise, and 8KV static electricity in the pad of pin 7 on the first surface layer will all be coupled to the Vo6 power trace on the second layer. And the Vo6 power trace on the second layer supplies power to the GPS module. When the GPS module is powered, it will be interfered by the 8 - 100V power supply, power supply noise, and 8KV static electricity; if the noise generated by the GPS module through the Vo6 power trace, it will also be coupled to the pad of pin 6 of the external connector on the first surface layer, and then carried out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0043] The Vo5 power trace on the second layer is adjacent to the pad of pin 8 of the external connector, and the pad of pin 8 of the external connector contains a power supply of 8 - 100V, power supply noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo5 power trace on the second layer is not a GND plane. The 8 - 100V power supply, power supply noise, and 8KV static electricity in the pad of pin 8 on the first surface layer will all be coupled to the Vo5 power trace on the second layer. And the Vo5 power trace on the second layer supplies power to the GPS module. When the WIFI module is powered, it will be interfered by the 8 - 100V power supply, power supply noise, and 8KV static electricity; if the noise generated by the WIFI module through the Vo5 power trace, it will also be coupled to the pad of pin 8 of the external connector on the first surface layer, and then carried out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0044] Since the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer are routed along the Y direction of the substrate, and on the second surface layer, it is necessary to set up a CAM chip module, a charge pump module, a 485 module, a power conversion switch ( Figure 1Related components such as (not marked), etc., so only some signal traces can be set in the X direction of the third layer. In this way, the signal traces on the third layer can be staggered from the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer. Otherwise, the traces on the substrate 73 will not work. This also brings a problem, that is, the signal traces on the third layer are adjacent to the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer, resulting in mutual interference problems. At the same time, there is no complete GND plane for the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer on the third layer, resulting in a relatively large return current area for the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer during transmission, generating relatively large noise and affecting their respective loads (such as LTE modules, MCU modules, WIFI modules, Bluetooth modules, GPS modules, 485 modules). And the signal traces on the third layer also need to be adjacent to the components on the second surface layer (such as charge pumps, CAM chips, 485 chips), resulting in mutual interference problems. And a GPS antenna needs to be set on the first surface layer, and a GND plane needs to be set on the first surface layer of the GPS antenna, and signal traces and power traces cannot be set.

[0045] In addition, the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace arranged on the first inner layer are basically led out from the position of the output capacitor of the BUCK power module near the second surface layer of the substrate to each load near the B end of the substrate: Bluetooth module 70, MCU module 102, LTE module 32, GPS module 31, 485 module 30, and wifi module 101. The Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace arranged on the first inner layer almost span the entire substrate. The longer the trace, the greater the voltage drop. The line width of the Vo1 power trace is W1, and it is recommended that W1≥0.6mm; the line width of the Vo2 power trace is W2, and it is recommended that W2≥0.8mm; the spacing between the Vo1 power trace and the Vo2 power trace is W8, and it is recommended that W1≥0.2mm; the line width of the Vo3 power trace is W3, and it is recommended that W3≥2.5mm; the line width of the Vo4 power trace is W4, and it is recommended that W4≥0.6mm; the spacing between the Vo3 power trace and the Vo4 power trace is W10, and it is recommended that W1≥0.2mm; the line width of the Vo6 power trace is W5, and it is recommended that W5≥0.6mm; the line width of the Vo5 power trace is W6, and it is recommended that W6≥0.8mm; the spacing between the Vo6 power trace and the Vo5 power trace is W7, and it is recommended that W7≥0.2mm. The Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace almost fill up the routing space of the first inner layer. If the substrate density is very high and a 4-layer board cannot be used, the number of substrate layers needs to be increased (such as a 6-layer board), which greatly increases the cost of the substrate 73.

[0046] If all the power traces are arranged on the third layer, all the power traces on the third layer will be adjacent to all the components on the second surface layer (such as the 485 chip module, CAM chip module, and charge pump), resulting in mutual interference. The return current traces of all the power traces (Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace) on the third layer have a cross-partition problem (the return current area becomes larger) due to the lack of a complete GND plane on the second surface layer, and all the power traces on the third layer generate relatively large noise. First, it affects their corresponding loads. In addition, all the components on the second surface layer (such as the 485 chip module, CAM chip module, and charge pump) will also be affected by the signal quality in all the components on the second surface layer because there is no complete GND plane on the adjacent third layer. The original signal traces designed on the third layer must be arranged on the second layer, and a GND plane needs to be set below the GPS antenna body (B end), and signal traces and power traces cannot be set. The second-layer signal traces are adjacent to all the power traces on the third layer, and there is mutual interference between them.

[0047] Therefore, there are some risks in the stacking of the above substrate 73 and the layout of the power devices, which will cause mutual interference and affect signal quality, power quality, radio frequency spurious index, EMC radiation index and other problems.

[0048] In view of this, the embodiments of the present application aim to provide a substrate and an electronic device, by setting the projection of the power copper foil in the first inner layer within the projection range of the ground cable line and the first ground copper foil on the first surface layer, thereby reducing the mutual interference between the electronic components connected to the power copper foil and the external cable.

[0049] The content of the embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can understand the content of the present application in more detail. It should be noted that in this embodiment, the first direction is the -Z-Z direction, the second direction is the -X-X direction, and the third direction is the -Y-Y direction.

[0050] This embodiment provides a substrate 73, including a first surface layer, on which an external cable 74 is provided for connecting to an external device; the first surface layer includes a first end and a second end opposite to each other in the first direction and a third end and a fourth end opposite to each other in the second direction. In the first direction, the external cable 74 is disposed near the first end of the first surface layer. The external cable 74 includes a plurality of cable lines, all of which extend in the first direction and are spaced apart in the second direction. One of the plurality of cable lines is a ground cable line, and the ground cable line is disposed near the third end; a first ground copper foil G1 connected to the ground cable line is also provided on the first surface layer;

[0051] A first inner layer adjacent to the first surface layer, on which a power copper foil 86 is provided, which is electrically connected to the BUCK power module 51 and is used to supply power to the electronic components on the substrate 73;

[0052] In the direction perpendicular to the substrate 73, the projection of the power copper foil 86 is located within the projection range of the ground cable line and the first ground copper foil G1.

[0053] This embodiment sets the projection of the power copper foil 86 in the first inner layer within the projection range of the ground cable line and the first ground copper foil G1 on the first surface layer, thereby reducing the mutual interference between the electronic components connected to the power copper foil 86 and the external cable 74.

[0054] In a possible embodiment, it further includes a second surface layer, which is disposed opposite to the first surface layer in the direction perpendicular to the substrate 73; the BUCK power module 51 is disposed on the second surface layer, and the BUCK power module 51 is electrically connected to the power copper foil 86 through a power via.

[0055] In a possible embodiment, it further includes a second inner layer adjacent to the second surface layer, and a second ground copper foil G3 is provided on the second inner layer; other components are also provided on the second surface layer, and in the direction perpendicular to the substrate 73, the projection of the other components is within the projection range of the power supply copper foil 86, and the projections of the other components and the power supply copper foil 86 are both within the projection range of the second ground copper foil G3.

[0056] In this embodiment, the projection of other components on the second surface layer is set within the projection range of the power supply copper foil 86, and the projections of the other components and the power supply copper foil 86 are both set within the projection range of the second ground copper foil G3, so that the electronic components connected to the power supply copper foil 86 will not interfere with each other.

[0057] In a possible embodiment, the other components include a power supply trace, a signal trace or an R232 module 87.

[0058] In a possible embodiment, a third ground copper foil G2 is further provided on the first inner layer, and the third ground copper foil G2 is located on the side of the power supply copper foil 86 facing the fourth end; in the direction perpendicular to the substrate 73, the projections of multiple cable lines are within the projection range of the third ground copper foil G2 except for the grounding cable line.

[0059] In this embodiment, the projections of multiple cable lines except for the grounding cable line are set within the projection range of the third ground copper foil G2, so that the electronic components connected to the power supply copper foil 86 will not interfere with other cables in the external cable 74.

[0060] In a possible embodiment, a grounding component 84 is further provided on the first inner layer, the grounding component 84 is located on the side of the power supply copper foil 86 facing the third end, and the power supply copper foil 86 is electrically connected to the first ground copper foil G1 and the second ground copper foil G3.

[0061] In this embodiment, ground copper foils or ground wires are provided on the upper, lower, left, and right sides of the power supply copper foil 86, which belongs to three-dimensional ground wrapping, so that the electronic components connected to the power supply copper foil 86 will not interfere with other components.

[0062] In a possible embodiment, the grounding component 84 includes a ground copper foil or a ground wire.

[0063] In a possible embodiment, the grounding component 84 is a ground wire, and multiple ground vias are provided on the ground wire, and the ground wire is electrically connected to the first ground copper foil G1 and the second ground copper foil G3 through the multiple ground vias.

[0064] In a possible embodiment, an external connector 69 is further provided on the first surface layer, and the external cable 74 is connected to the external connector 69.

[0065] This embodiment further provides an electronic device, including the substrate 73 as described in the above embodiment.

[0066] Specifically, as Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 shown, among which, Figure 4 , Figure 6 is Figure 3 the cross-sectional view cut along the position of the substrate edge B3 - B4 in Figure 5 , Figure 7 is Figure 3 the cross-sectional view cut along the position of the substrate edge B1 - B2 in

[0067] An external cable 74 and an external connector 69 are arranged at the A end (the first end, the same below) of the first surface layer of the substrate 73. A BUCK power module 51 is arranged at the A end of the second surface layer of the external cable 74, that is, the BUCK power module 51 is arranged at the projection of the second surface layer of the external connector 69 on the first surface layer. The "-" pole pad of the output capacitor 47 in the BUCK power module 51 is connected to the ground cable line GND of the external cable 74. The "+" pole pad of the output capacitor 47 in the BUCK power module 51 leads out a power copper foil 72 (arranged on the second surface layer). Power vias 79 (referring to multiple power vias) are arranged on the power copper foil 72 near the "-" pole pad of the output capacitor 47. The more the number of the power vias 79, the smaller the parasitic inductance ESL and the DC resistance ESR of the power vias 79, the smaller the voltage drop generated in the power vias 79, and at the same time, the faster the response speed of the power dynamics and the smaller the ripple on the power copper foil 72.

[0067] The power copper foil 72 on the second surface layer is electrically connected to the power copper foil 86 on the first inner layer after changing layers through the power vias 79. The power copper foil 86 on the first inner layer crosses the projection of the ground cable line of the external connector 69 on the first surface layer on the first inner layer through the power vias 79. The GPS antenna 82 on the first surface layer and the R232 module 87 on the second surface layer, and other modules 89 on the second surface layer are projected on the first inner layer. As Figure 4 , Figure 6As shown, since the power copper foil 86 of the first inner layer falls on the traces of the first surface layer on the first ground copper foil G1 and the ground cable pad of the external connector, and does not fall on the pad of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69. The ground cable pad of the external connector 69 is electrically connected to the first ground copper foil G1 and belongs to the same network. They form an integral metal ground (that is, the ground cable of the external connector 69 is included by the first ground copper foil G1). A low-frequency pulse electric field e1 is formed between the power copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer and the ground cable pad of the external connector 69; a pulse electric field e5 is formed between the pad of pin 2 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a pulse electric field e6 is formed between the pad of pin 3 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a pulse electric field e7 is formed between the pad of pin 4 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a pulse electric field e8 is formed between the pad of pin 5 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a pulse electric field e9 is formed between the pad of pin 6 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a low-frequency pulse electric field e10 is formed between the pad of pin 7 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a low-frequency pulse electric field e11 is formed between the pad of pin 8 of the external connector 69 and the third ground copper foil G2 of the first inner layer; a low-frequency pulse electric field e12 is formed between the pad of pin 9 of the external connector 69 and the third ground copper foil G2 of the first inner layer. That is, the noise, surges, and static electricity generated in the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 7, pin 8, pin 9 of the external connector 69 will not be coupled to the power copper foil 86 of the first inner layer in the form of a pulse electric field. The noise generated in the power copper foil 86 of the first inner layer (including the noise generated by the BUCK power module and various loads electrically connected to the power copper foil 86 of the first inner layer) will not be coupled to the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 7, pin 8, pin 9 of the external connector 69 in the form of a pulse electric field.

[0068] A low-frequency pulsed electric field e4 is generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer, which is confined between the first inner layer and the second inner layer. At the projection position of the power copper foil 86 of the first inner layer on the second surface layer, an R232 module 87 and the like are provided. Although the R232 module 87 overlaps with the power copper foil 86, a pulsed electric field e14 is generated between the R232 module 87 and the second ground copper foil G3 of the second inner layer, which is confined between the second inner layer and the second surface layer. That is, the pulsed electric field e14 generated by the R232 module 87 on the second surface layer and the second ground copper foil G3 of the second inner layer does not overlap spatially with the low-frequency pulsed electric field e4 generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer, and there is no interference between them. In addition, power traces, signal traces, etc. can also be set at the projection position of the power copper foil 86 of the first inner layer on the second surface layer. It is not necessary to set the R232 module 87. The analysis principle is the same as that of setting the R232 module 87 on the second surface layer, and will not be described repeatedly.

[0069] As Figure 4 shown, a current i1 is generated in the power copper foil 86 of the first inner layer, and its return path on the first surface layer falls on the first ground copper foil G1 of the first surface layer and the pads of the external connector ground cable. A pulsed magnetic field B61 is generated between the power copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer and the pads of the external connector ground cable. And a current i10 is generated in the pad of pin 2 of the external connector 69, and its return path falls on the third ground copper foil G2 of the first inner layer. A pulsed magnetic field B13 is generated between the pad of pin 2 of the external connector 69 and the third ground copper foil G2 of the first inner layer. And so on, the pulsed magnetic fields generated between the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69 and the third ground copper foil G2 of the first inner layer are B13, B14, B15, B16, B17, B18, B19, B20 respectively. The return paths of the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 all fall on the third ground copper foil G2 of the first inner layer. Since the return ground of the power copper foil 86 of the first inner layer falls on the first ground copper foil G1 of the first surface layer and the pads of the ground cable of the external connector 69, and the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69 fall on the third ground copper foil G2 of the first inner layer, and the pulsed magnetic fields generated between them are staggered in space. That is, there is no coupling interference between the pulsed magnetic field B61 generated by the power copper foil 86 of the first inner layer and the pulsed magnetic fields generated by the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69.

[0070] A low-frequency pulsed magnetic field B62 is generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer, which is restricted between the first inner layer and the second inner layer. At the projection position of the power copper foil 86 of the first inner layer on the second surface layer, an R232 module 87, etc. are provided (to increase the layout and wiring density of the substrate 73, reduce the size and number of layers of the substrate 73, so as to reduce the cost of the substrate). Although the R232 module 87 overlaps with the power copper foil 86, a pulsed magnetic field B21 is generated between the R232 module 87 and the second ground copper foil G3 of the second inner layer, which is restricted between the second inner layer and the second surface layer. That is, the pulsed magnetic field B21 generated by the R232 module 87 on the second surface layer and the second ground copper foil G3 of the second inner layer and the pulsed magnetic field B62 generated by the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer do not overlap in space and there is no interference between them. In addition, power traces, signal traces, etc. can also be set at the projection position of the power copper foil 86 of the first inner layer on the second surface layer. It is not necessary to set the R232 module 87. The analysis principle is the same as that of setting the R232 module 87 on the second surface layer and will not be described repeatedly.

[0071] Such as Figure 3 , Figure 6As shown, a ground wire 84 is provided near the left board edge B3 of the power supply copper foil 86 on the first inner layer. Spaced ground vias 90 are provided on the ground wire 84 along the left board edge. The ground vias 90 achieve low-impedance electrical connection between the ground wire 84 and the first ground copper foil G1 on the first surface layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the second surface layer. A third ground copper foil G2 is provided on the right side of the power supply copper foil 86 on the first inner layer. The projection trajectory of the power supply copper foil 86 on the first inner layer on the second inner layer is the second ground copper foil G3 on the second inner layer; that is, the upper, lower, left, and right of the power supply copper foil 86 on the first inner layer are all ground copper foils, belonging to three-dimensional ground wrapping. Since the ground cable of the external connector 69 overlaps with the power supply copper foil 86 on the first inner layer in the vertical direction (Y direction) of the substrate 73, and the power supply copper foil 86 on the first inner layer does not overlap with other functional pins of the external connector 69 in the vertical direction (Y direction) of the substrate 73, it will not cause mutual interference between it and the functional pins of the external connector 69, and there will be no adjacent problems caused by cross-segmentation. Nor will the noise generated in the power supply copper foil 86 on the first inner layer (including the noise generated by the BUCK power module and the noise generated by various loads electrically connected to the power supply copper foil 86 on the first inner layer) be coupled to the pad of each pin of the external connector 69 and the external cable 74 in the form of pulsed electric field and pulsed magnetic field, resulting in excessive EMC radiation or conduction. The noise, surge, and static electricity generated by the pad of each pin of the external connector 69 and the external cable 74 will not be coupled to the power supply copper foil 86 on the first inner layer. At the same time, the signal traces, power traces, or components (including sensitive components and strongly interfering components) provided at the position where the power supply copper foil 86 on the first inner layer is projected on the second surface layer are separated by the second ground copper foil G3 on the second inner layer, and there will be no mutual influence between the power supply copper foil 86 on the first inner layer and the signal traces, power traces, or components provided at the position where the power supply copper foil 86 is projected on the second surface layer. Therefore, the position of the power supply copper foil 86 on the first inner layer is scientific and reasonable.

[0072] On the ground pin of the external connector 69 on the first surface layer ( Figures 3 to 7The projection of the middle ground pin, which can be or not be a ground cable, sets the power copper foil 86 at the first inner layer position. The projection of the ground pin of the external connector 69 sets the second ground copper foil G3 at the second inner layer position, and sets signal traces, power traces or components at the second surface layer position of the projection of the ground pin of the external connector 69. This not only saves the layout space on the front and back sides of the substrate 73, but also there is no mutual interference between the functional pins of the first surface layer external connector 69 and the power copper foil 86 of the first inner layer. At the same time, there is no mutual interference between the power copper foil 86 of the first inner layer and the signal traces, power traces or components set at the second surface layer position. Therefore, this setting position is scientific and reasonable. In addition, components are arranged on both the front and back sides of the position of the external connector 69 of the substrate, so that the density of the entire substrate 73 is greatly increased, saving the layout space of the substrate and the area of the substrate, that is, saving the cost of the substrate 73.

[0073] Continue to refer to Figure 3 、 Figure 5 and Figure 7 As shown, since the first ground copper foil G1 is set at the projection of the GPS antenna 82 on the first surface layer, a high-frequency pulse electric field e22 (1.575 GHz) is formed between the GPS antenna 82 and the first ground copper foil G1, providing good conditions for the GPS antenna 82 to receive signals sent by near-earth orbit satellites. And a low-frequency pulse electric field e1 is formed between the power copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer. Although the power copper foil 86 of the first inner layer and the GPS antenna 82 of the first surface layer overlap in the vertical direction, the low-frequency pulse electric field e1 generated by the power copper foil 86 and the high-frequency pulse electric field e22 generated by the GPS antenna 82 are separated in space by the third ground copper foil G2 of the first inner layer, that is, there is no coupling interference in the space pulse electric field between the power copper foil 86 of the first inner layer and the GPS antenna 82.

[0074] At the overlapping position of the GPS antenna 82 on the first surface layer, the power copper foil 86 of the first inner layer, and a certain functional module 89 on the second surface layer (which can be a GPS module, an RR232 module, a 485 module, etc., without restricting the type of components), a low-frequency pulse electric field e2 is formed between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of L02, and a pulse electric field e13 is formed between the certain functional module 89 on the second surface layer and the second ground copper foil G3 of L03. Although the power copper foil 86 of the first inner layer and the certain functional module 89 on the second surface layer overlap in the vertical direction, the low-frequency pulse electric field e1 generated by the power copper foil 86 and the pulse electric field e13 generated by the certain functional module 89 on the second surface layer are separated in space by the third ground copper foil G2 of the first inner layer, that is, there is no coupling interference in the space pulse electric field between the power copper foil 86 of the first inner layer and the certain functional module 89 on the second surface layer.

[0075] A current i1 is generated in the power supply copper foil 86 of the first inner layer. A pulsed magnetic field B61 is generated between the power supply copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer. A pulsed magnetic field B62 is generated between the power supply copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer. A current i19 is generated in a certain functional module 89 of the second surface layer. A pulsed magnetic field B22 is generated between the certain functional module 89 of the second surface layer and the second ground copper foil G3 of the second inner layer. Although the power supply copper foil 86 of the first inner layer and the certain functional module 89 of the second surface layer overlap in the vertical direction, the low-frequency pulsed magnetic field B62 generated by the power supply copper foil 86 and the pulsed magnetic field B22 generated by the certain functional module 89 of the second surface layer are spatially separated by the second ground copper foil G3 of the second inner layer. That is, there is no coupling interference between the power supply copper foil 86 of the first inner layer and the certain functional module 89 of the second surface layer in the spatial pulsed magnetic field. Although the power supply copper foil 86 of the first inner layer and the GPS antenna 82 of the first surface layer overlap in the vertical direction, the low-frequency pulsed magnetic field B62 generated by the power supply copper foil 86 and the pulsed magnetic field B70 generated by the GPS antenna 82 are spatially separated by the first ground copper foil G1 of the first surface layer. That is, there is no coupling interference between the power supply copper foil 86 of the first inner layer and the GPS antenna of the first surface layer in the spatial pulsed magnetic field.

[0076] The power supply copper foil 86 is arranged at the position of the projection of the GPS antenna 82 of the first surface layer on the first inner layer. The second ground copper foil G3 is arranged at the position of the projection of the power supply copper foil 86 of the first inner layer on the second inner layer. Signal traces, power traces or components are arranged at the position of the projection of the power supply copper foil 86 of the first inner layer on the second surface layer. This not only saves the layout space on both sides of the substrate, but also there is no mutual interference between the GPS antenna 82 of the first surface layer and the power supply copper foil 86 of the first inner layer. At the same time, there is no mutual interference between the power supply copper foil 86 of the first inner layer and the signal traces, power traces or components arranged at the position of the second surface layer. Therefore, this setting position is scientific and reasonable. In addition, components are arranged on both the front and back sides of the GPS position of the substrate, so that the density of the entire substrate 73 is greatly increased, saving the substrate layout space and the substrate area, that is, saving the cost of the substrate 73.

[0077] The ground cable pad in the external connector 69 is connected to the ground cable pin in the external connector 69. The ground cable pin in the external connector 69 is connected to the external cable 1 (connected to GND) to provide a ground loop for each functional pin such as the input power supply VIN of the external cable. The pad of pin 2 in the external connector 69 is connected to the pin of pin 2 in the external connector 69. The pin of pin 2 in the external connector 69 is connected to the external cable 2 (input power supply VIN).

[0078] The BUCK power module 51 is provided at the second surface position where the external cable 74 and the external connector 69 are projected. The BUCK power module 51 includes an input clamping and filtering circuit (not shown in the figure) and a BUCK power supply (not shown in the figure). One end of the input clamping and filtering circuit is connected to the pad of pin 2 in the external connector 69, and the other end of the input clamping and filtering circuit is connected to the input end of the BUCK power supply. The input clamping and filtering circuit and the BUCK power supply are both connected to the ground cable pad in the external connector 69. The "-" pole pad (i.e., the negative pole pad) of the output capacitor 47 of the BUCK power supply is connected to all the ground copper foils of the substrate 73, and the external power cable 74, the external power connector 69, and the BUCK power module 51 form a loop. The "+" pole pad (i.e., the positive pole pad) of the output capacitor 47 of the BUCK power supply leads out the power copper foil 72 to supply VCC to the entire substrate 73.

[0079] The external cable 74 and the external connector 69 inject a surge voltage of 200V - 500V into the BUCK power module 51, contact an 8KV electrostatic discharge, and there are various noises on the vehicle or on the motorcycle. So where is the appropriate position for the BUCK power module 51, the external cable 74, and the external connector 69?

[0080] Technical features: The substrate is long and strip-shaped. The external cable 74 and the external connector 69 are provided on the right side (the first surface layer of the substrate 73) above the substrate 73 (end A). The Bluetooth antenna and its clearance area are provided on the left side above the substrate 73 (the Bluetooth antenna radiator is provided on the first surface layer of the substrate 73). The LTE antenna and its clearance area are provided below the substrate 73 (end B) (the LTE antenna radiator is provided on the second surface layer of the substrate 73). The GPS antenna is provided between the external connector 69 and the LTE antenna and its clearance area. The element body containing metal around the GPS antenna body satisfies a 45-degree angle.

[0081] A. If the GPS antenna is placed on the second surface layer of the substrate, the GPS antenna will be on the same layer as the radiator of the LTE antenna, and the GPS antenna will be interfered by the LTE antenna. Therefore, the GPS antenna is preferably placed between the external connector 69 and the LTE antenna and its clearance area, and on the front surface of the substrate. The GPS antenna and the LTE antenna are distributed on different layers of the substrate to reduce the coupling of the LTE antenna transmitting signals to the GPS antenna and affect the sensitivity of the GPS antenna to receive satellite signals, etc.

[0082] B. Surge voltages of 200V to 500V are injected into the BUCK power module through the external cable 74 and the external connector 69, and there is contact with 8KV electrostatic discharge, as well as various noises on the vehicle or motorcycle. The external cable 74 and the external connector 69 need to be close to the upper part of the substrate 73, which is convenient for leading out the external cable 74 from the plastic housing (not shown in the figure). In addition, the external cable 74 and the external connector 69 (which are large metal parts) should be as close as possible to the upper part (A end) edge of the substrate 73, and a certain distance can be maintained from the GPS antenna, so as to meet the requirement that the element body containing metal around the GPS antenna body meets the 45-degree reception angle requirement, and at the same time avoid the interference of the 200V to 500V surge voltage, 8KV electrostatic discharge contact, various noises on the vehicle or motorcycle in the external connector 69 to the GPS antenna.

[0083] C. Since the external cable 74 and the external connector 69 are arranged on the first surface layer close to the upper part (A end) edge of the long strip-shaped substrate 73, while the LTE antenna and its clearance area are arranged close to the lower part (B end) edge of the long strip-shaped substrate 73. The external cable 74 and the external connector 69 are far from the TE antenna and its clearance area, and the LTE antenna will not be interfered by the 200V to 500V surge voltage, 8KV electrostatic discharge contact, various noises on the vehicle or motorcycle in the external connector 69.

[0084] D. The input terminal of the BUCK power module is subject to a surge voltage of 200V - 500V, contact with 8KV electrostatic discharge, various noises in automobiles or motorcycles, and the switching noise generated by the BUCK power supply in the BUCK power module, which has strong interference on the GPS antenna, GPS module, LTE module, LTE antenna, Bluetooth module, and Bluetooth antenna. Therefore, the BUCK power module is preferably placed in the projection area of the external cable 74 (the first surface layer) and the external connector 69 (the first surface layer) on the second surface layer of the substrate. The switching circuits of the input capacitor, switching transistor, freewheeling diode, inductor, and output capacitor in the BUCK power supply generate noises including: pulsed electromagnetic field radiation, pulsed magnetic field radiation generated by the inductor, etc. The GPS antenna on the first surface layer is an extremely sensitive component. Placing the BUCK power module at the projection position of the GPS antenna on the second surface layer, the input terminal of the BUCK power module has a surge voltage of 200V - 500V, contact with 8KV electrostatic discharge, various noises in automobiles or motorcycles, and the pulsed electromagnetic field radiation and pulsed magnetic field radiation generated by the inductor in the BUCK power supply may be coupled into the GPS antenna, and the common ground noise of the freewheeling diode will also be coupled into the G1 ground copper foil adjacent to the GPS antenna and the GPS module. Therefore, the BUCK power module cannot be placed on the second surface layer corresponding to the GPS antenna (the first surface layer) to avoid interference to the GPS antenna. The external cable 74 and external connector 69 on the first surface layer are not sensitive components. Placing the BUCK power module in the projection area of the external cable 74 and external connector 69 on the first surface layer on the second surface layer will not affect the normal functions of the external cable 74 and external connector 69. At the same time, the VIN power supply of the external cable 74 and external connector 69 is closer to the BUCK power module, the loop of the VIN power supply trace is shorter, the voltage drop on the VIN power supply trace is smaller, and the interference to other parts is also smaller.

[0085] E. Figure 8 A partial cross-section of the external cable + Bluetooth antenna + BUCK power supply on the substrate 73 is given Figure 1 , Figure 4 A partial cross-section of the external cable + Bluetooth antenna + BUCK power supply on the substrate 73 is given Figure 2 . As Figure 8 , Figure 4 shown, the BUCK power module 43 presents an input capacitor 104, a BUCK chip 105, an inductor 106, and an output capacitor 107, and in the input clamping and filtering circuit Figure 8 , Figure 4Unlabeled, with a very compact layout. A shielding cover is added to the BUCK power module 43 mainly to avoid radiation interference to the left Bluetooth antenna and at the same time reduce the EMI radiation and spurious indexes of the BUCK power module 43 to the whole machine. At least one layer of ground copper foil (such as at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer) needs to be set on the substrate between the BUCK power module 43 (second surface layer) and the external cables 74 and external connectors 69 on the first surface layer to separate the BUCK power module 43 (second surface layer) from the external cables 74 and external connectors 69 on the first surface layer (the most important technical feature), that is, the BUCK power module 43 on the second surface layer is covered by at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, and the external cables 74 and external connectors 69 on the first surface layer are covered by at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. There are two purposes: at least one of the ground copper foils provides a complete return path for the BUCK power module 43 on the second surface layer, which can minimize the switching noise generated by the BUCK power module 43, reduce the conduction and spatial radiation interference to the board components, and reduce external radiation (improve spurious and EMI radiation indexes). At the same time, the 200V - 500V surge voltage, 8KV contact discharge, various noises in the car or various noises on the motorcycle in the external cables 74 and external connectors 69 on the first surface layer will not be coupled to the BUCK power module 43, but will be coupled to at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, and will not cause interference to the BUCK power module 43. The switching noise radiation generated in the BUCK power module 43 will not be coupled to the external cables 74 and external connectors 69 on the first surface layer, resulting in excessive radiation and conduction.

[0086] F. If the BUCK power module 43 on the second surface layer overlaps vertically with the Bluetooth module, GPS module, LTE module, audio codce module, etc. on the first surface layer, the switching noise in the BUCK power module 43 will be coupled to the Bluetooth module, GPS module, and LTE module on the first surface layer, resulting in poor performance indexes of the Bluetooth module, GPS module, LTE module, and audio codce module. Therefore, the best solution is to place the BUCK power module 43 on the second surface layer in the projection area of the external cables 74 and external connectors 10 on the second surface layer.

[0087] G. Such as Figure 8 、 Figure 4As shown, the BUCK chip 105 internally integrates an upper MOSFET (not shown in the figure) and a lower MOSFET (or a freewheeling diode, not shown in the figure). The upper MOSFET integrated in the BUCK chip 105 is connected to the input capacitor 104, while the lower MOSFET integrated in the BUCK chip 105 is connected to at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer through the ground pin 42 of the BUCK chip 105 and the ground via 45. The connection position of the upper MOSFET and the lower MOSFET integrated in the BUCK chip 105 leads out a pin and is connected to one end of the inductor 106, and the other end of the inductor 106 is connected to the output capacitor 107. When the upper MOSFET integrated in the BUCK chip 105 is turned on, a loop is formed from the input capacitor 104 to the upper MOSFET integrated in the BUCK chip 105, the inductor 106, and the output capacitor 107, generating a low-frequency pulsed magnetic field B1; when the upper MOSFET integrated in the BUCK chip 105 is turned off and the lower MOSFET is turned on, the energy stored in the inductor 106 passes through the lower MOSFET, the ground pin 42 of the BUCK chip 105, the ground via 45 to at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, the load, and the output capacitor 107 to the inductor 106 to form a loop, generating a low-frequency pulsed magnetic field B2; the low-frequency pulsed magnetic field B1 and the low-frequency pulsed magnetic field B2 are restricted between the second surface layer and at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. With the external shielding cover 14 of the BUCK power module 43, the low-frequency pulsed magnetic field B1 and the low-frequency pulsed magnetic field B2 hardly leak to the outside; low-frequency pulsed electric fields e1, e2, e3, and e4 are respectively formed between the input capacitor 104, the BUCK chip 105, the inductor 106, the output capacitor 107 and at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. Due to the existence of at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, the low-frequency pulsed electric fields e1, e2, e3, and e4 are not coupled to the external cable 74 and the external connector 69, and the generated noise radiation will not be coupled to the external cable 74 and the external connector 69 to cause excessive EMI radiation, conduction, and spurious emissions.Due to the addition of the shielding cover 14 to the BUCK power module 43, the low-frequency pulsed magnetic field and low-frequency pulsed electric field generated inside the BUCK power module 43 are suppressed inside the shielding cover 14 and will not interfere with other components on the board (such as the Bluetooth antenna, Bluetooth module, GPS module, etc. set beside the BUCK power module 43).

[0088] H. The output capacitor 107 of the BUCK power module 43 generates a stepped-down and stabilized power supply, which is output to supply power to the entire board.

[0089] As previously introduced, an external cable 74 and an external connector 69 are provided at the A end of the first surface layer above the substrate 73, and the BUCK power module 51 is preferably arranged in the projection area of the external cable 74 and the external connector 69 on the second surface layer.

[0090] As Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 As shown, a second surface layer power copper foil 72 is led out from the positive electrode pad of the output capacitor 107 of the BUCK power supply 51 on the second surface layer, and a power via 79 is provided at a position where the power copper foil 72 is close to the positive electrode pad of the output capacitor 107. The power copper foil 86 is led out from the first inner layer of the power via 79. The power copper foil 86 passes through the projection of the first surface layer GPS antenna 82 and the R232 module 87 / a certain functional module 89 on the second surface layer on the first inner layer, that is, although the power copper foil 86 overlaps with the first surface layer GPS antenna 82 and the R232 module 87 / a certain functional module 89 on the second surface layer in the direction perpendicular to the substrate (Y direction), since the first surface layer first ground copper foil G1 is provided between the power copper foil 86 on the first inner layer and the first surface layer GPS antenna 82, they are separated by the first ground copper foil G1 on the L1 layer, and they are not directly adjacent to each other and there is no mutual interference; a second inner layer second ground copper foil G3 is provided between the power copper foil 86 on the first inner layer and the R232 module 87 / a certain functional module 89 on the second surface layer, and they are separated by the second ground copper foil G3 on the second inner layer, and they are not directly adjacent to each other and there is no mutual interference.

[0091] The power copper foil 86 on the first inner layer is led to an area outside the projection of the GPS antenna 82 to provide power vias 78 (referring to multiple power vias), and the layer is changed to the second surface layer power copper foil 37 through the power vias 78. The second surface layer power copper foil 37 is connected to the second surface layer power trace branches 6, power trace branches 5, power trace branches 71, magnetic beads 81, and power trace branches 22.

[0092] The power trace branch 6 is connected to the capacitor 10 on the second surface layer and the input terminal of the low dropout linear regulator 19. The output terminal of the low dropout linear regulator 19 on the second surface layer and the positive pad of the capacitor 16 are connected to the GPS module on the second surface layer through the power trace 18 on the second surface layer. The power trace branch 5 is connected to the capacitor 68 on the second surface layer and the input terminal of the low dropout linear regulator 13 on the second surface layer. The output terminal of the low dropout linear regulator 13 on the second surface layer and the capacitor 69 are connected to the MCU module 102 on the second surface layer through the power trace 15. The power copper foil 37 on the second surface layer is connected to one end of the magnetic bead 76. The other end of the magnetic bead 76, the positive pad of the large capacitor 97 on the second surface layer, and the positive pad of the small capacitor 98 are connected to the audio power amplifier module 30 on the second surface layer through the power trace 75 on the second surface layer. The power copper foil 37 is connected to one end of the magnetic bead 81. The other end of the magnetic bead 81, the positive pad of the large capacitor 95, and the positive pad of the small capacitor 96 are connected to the wifi module 101 through the power trace 77 on the second surface layer. The power trace branch 22 is connected to the capacitor 21 on the second surface layer and the input terminal of the low dropout linear regulator 24 on the second surface layer. The output terminal of the low dropout linear regulator 24 on the second surface layer and the capacitor 27 are connected to the Bluetooth module 70 on the second surface layer through the power trace 26.

[0093] The setting idea is that when the BUCK power module 51 cannot be close to each load terminal for various reasons, various loads (such as GPS module 31, MCU module 102, LTE module 32, audio power amplifier module 30, wifi module 101, Bluetooth module 70), power conversion switches (such as MOSEFT power switch 20), power converters (such as low-dropout linear regulators 19, 13, 24, etc.), and beads / inductors / resistors (such as beads 76, 81, etc.) are concentrated and close together. In this way, the power supply copper foil 86 led out from the BUCK power module 51 can be led to the second surface layer (or the first surface layer). On the second surface layer (or the first surface layer), a power supply copper foil 78 is used to connect the input ends of the power converters (on the second surface layer or the first surface layer), the input ends of the power conversion switches (on the second surface layer or the first surface layer), and one end of the beads / inductors / resistors (on the second surface layer or the first surface layer). There is no need to punch power vias to change layers to connect the power supply traces of each load. In this way, it is ensured that the entire power supply system from the power supply copper foil 78 to the load (such as the LTE module) does not need to punch power vias to change layers (saving the voltage drop problem caused by power vias and the problem of power vias occupying the precious space of the high-density substrate). Nor is it like in the prior art where multiple independent power supply traces are led out from the output end of the BUCK power module 51 to the load end (not only do multiple power supply traces occupy PCB trace space, but multiple independent power supply traces punching holes and changing layers occupy a large amount of space). This greatly saves the substrate trace space and at the same time reduces the problems of excessive via distributed inductance, large voltage drop, large power supply ripple, mutual interference problems, cross-segmentation return problems, and EMI radiation problems caused by multiple independent power supply traces punching holes and changing layers; multiple independent power supply traces adjacent to the pads of multiple pins of the connector cause mutual interference problems, cross-segmentation return problems, EMI radiation problems, electrostatic coupling problems, and surge coupling problems.

[0094] At the same time, on the second surface layer (or the first surface layer), a ground copper foil (such as the second ground copper foil G3 is set on the second inner layer) is set for the power supply copper foil 78, power converters, power conversion switches, beads / inductors / resistors, or loads (such as the LTE module) projected on the adjacent layer. In this way, it is ensured that there is a complete second ground copper foil G3 on the adjacent layer of the entire power supply system from the power supply copper foil 78 to the load (such as the LTE module) to provide the shortest return path for the power supply copper foil 78 to the load (such as the LTE module).

[0095] Taking the LTE module 32 + MOSFET power switch 20 and power supply copper foil 37 set on the first surface layer (it can also be set on the second surface layer) as an example for illustration.

[0096] Among them, Figure 8 、 Figure 9 is the partial cross-sectional view along the Figure 3 position of the MOSFET power switch A9 - A10 inFigure 10 , Figure 11 is the partial cross-sectional view along the position of the MOSFET power switch A7 - A8 in Figure 3 . Figure 12 The cross-sectional view in the X - X direction (at the position of A1 - A2) of the layer-changing position between the top-layer power copper foil and the first inner-layer power copper foil is given; Figure 13 The cross-sectional view in the Z - Z direction of the layer-changing position between the top-layer power copper foil and the first inner-layer power copper foil is given. Figure 12 , Figure 13 is Figure 3 the cross-sectional views at different angles along the positions of the power via 76 and the ground via 110 in

[0097] Such as Figure 8 , Figure 9As shown, the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 are oriented in the Z direction. The MOSFET power switch 20 projects a third ground copper foil G2 on the first inner layer; the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the first surface layer and the third ground copper foil G2 on the first inner layer form a pulsed electric field e31, which is confined to a very narrow space between the first surface layer and the first inner layer; a current i6 is generated in the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the first surface layer, and a magnetic field B6 is formed between the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the first surface layer and the third ground copper foil G2 on the first inner layer. The MOSFET power switch 20 projects signal traces 671, 541, 531 along the X direction of the substrate on the second inner layer; the signal traces 671, 541, 531 on the second inner layer and the third ground copper foil G2 on the first inner layer form pulsed electric fields e30, e32, e33 respectively, which are confined to a very narrow space between the first inner layer and the second inner layer. The pulsed electric fields e30, e32, e33 and the pulsed electric field e31 are separated by the third ground copper foil G2 on the first inner layer, and they are not in the same space. Therefore, there is no coupling interference between the pulsed electric fields of the signal traces 671, 541, 531 on the second inner layer and the MOSFET power switch 20, the power copper foil 37, and the power copper foil 63 on the first surface layer. The source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the first surface layer and the third ground copper foil G2 on the first inner layer form a planar capacitor. The ESL of the PCB planar capacitor is very small and can filter out noise up to several GHz, so as to reduce the noise radiation interference to the external space of the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63, etc., and at the same time reduce the external EMI radiation, conduction, and radio frequency spurs. As Figure 9As shown in the figure, taking the example of the PCB planar capacitor C formed by the source pin 68 of the MOSFET power switch 20 on the first surface layer, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer, L is the series equivalent inductance of the PCB planar capacitor C, and R is the series equivalent resistance of the PCB planar capacitor C. As shown in Table 2, between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer is PP (semi-cured sheet, a sheet-shaped bonding material synthesized by resin and carrier, that is, glass fiber epoxy resin material, abbreviated as FR-4 medium), and the dielectric constant of the FR-4 medium is 3.5 to 4.5. For the planar capacitor C formed between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer, the following is the calculation formula for the PCB planar capacitor C:

[0098] C = ε×ε0×S / d

[0099] In the formula:

[0100] The planar capacitor C, unit F.

[0101] ε is the dielectric constant of the PP (semi-cured sheet, a sheet-shaped bonding material synthesized by resin and carrier, that is, glass fiber epoxy resin material, abbreviated as FR-4 medium) between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer. Usually, the dielectric constant of the FR-4 medium is 3.5 to 4.5.

[0102] ε0 is the dielectric constant of vacuum: 8.86×10-12 F / m.

[0103] S is the area, which is the overlapping area between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer. Since it is required that the projections of the source pin 68 of the MOSFET power switch 20 on the first surface layer, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the third ground copper foil G2 on the first inner layer all fall within the range of the third ground copper foil G2 on the first inner layer, only the areas of the source pin 68 of the MOSFET power switch 20 on the first surface layer, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 need to be calculated.

[0104] d is the distance between the plates, which is the distance between the source pin 68 of the MOSFET power switch 20 on the first surface layer, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer (i.e., the PP thickness, generally 3 mil to 8 mil). The unit of the distance between the plates is m.

[0105] The distance between the source pin 68 of the MOSFET power switch 20 on the first surface layer, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer is between 3 mil and 8 mil (recommended to be 4 mil). The reflux area is very small, and the noise generated in the power copper foil 37 and the power copper foil 63 radiated externally is very small. At the same time, the power copper foil 37, the power copper foil 63 and the signal traces 671, 541, 531 will not generate mutual pulse electric field and magnetic field interference because they are not in the same space and are separated by the third ground copper foil G2 on the first inner layer.

[0106] The projections of the MOSFET power switch 20 on the second surface layer are provided with signal traces 67, 54, 53 along the Z direction. The signal traces 67, 54, 53 on the second surface layer and the third ground copper foil G2 on the first inner layer form pulsed electric fields e34, e35, e36. The signal traces 67, 54, 53 on the second surface layer and the third ground copper foil G2 on the first inner layer form pulsed magnetic fields B1, B2, B3. The signal traces 67, 54, 53 on the second surface layer and the signal traces 671, 541, 531 on the second inner layer are staggered by 90 degrees from each other. Therefore, the mutual pulsed electric field and pulsed magnetic field coupling between them is relatively small and will not affect their normal operation. The pulsed magnetic field and pulsed electric field generated by the signal traces 67, 54, 53 on the second surface layer and the source pin 68 of the MOSFET power switch 20, the power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the first surface layer are not in the same space. Therefore, there is no interference problem between them. Therefore, this stacked structure can accommodate two layers of signal traces (such as the signal traces 67, 54, 53 on the second surface layer and 671, 541, 531 on the second inner layer) and one layer of power trace (such as the power copper foils 37, 63), and power devices (such as the MOSFET power switch 20, the large capacitors 12 / 52, and the small capacitors 63 / 64) at the same position. Without increasing the number of substrate layers or the area, the layout and wiring density of the substrate 73 space is greatly increased, thus taking into account both the performance of the product and the cost of the substrate.

[0107] As Figure 10 , Figure 11 shown, VCC power is generated from the "+" pole pad of the output capacitor 107 and the power copper foil 72 in the BUCK power module 51, passes through the power vias 79 to change layers to the first inner layer power copper foil 86 to the power via 78, and then changes layers to the first surface layer (or the second surface layer) power copper foil 37 and is sent to the MOSFET power switch 20. A cross-sectional view along the positions of the power pins 33 / 39 of the LTE module 32, the large capacitor 52, the small capacitor 64, the power copper foil 63, and the MOSFET power switch 20, that is, the cross-sectional view at the A7 - A8 position. The MOSFET power switch 20, the small capacitor 64, the large capacitor 52, and the power pins 33 / 39 of the LTE module 32 are electrically connected through the power copper foil 63, and the third ground copper foil G2 is provided on their adjacent layers. A ground via 110 is provided near the power via 78. The ground via 110 is used to provide a return path for the ground copper foil of different layers when the first surface layer power copper foil 37 changes layers to the first inner layer power copper foil 86 through the power via 78. The distance between the ground via 110 and the power via 78 cannot exceed 20 mm. The closer the distance between the ground via 110 and the power via 78, the shorter the return path generated by the ground copper foils of the two different layers when the first surface layer power copper foil 37 changes layers to the first inner layer power copper foil 86 through the power via 78. AsFigure 10 、 Figure 11 、 Figure 12 、 Figure 13As shown, when the LTE module 32 receives and transmits wireless signals, the VCC power supply is generated from the "+" pole of the output capacitor 107 in the BUCK power module 51 and the power copper foil 72, and is changed to the first inner-layer power copper foil 86 through the power via 79 and then to the power via 78, and then changed to the first surface layer (or the second surface layer) power copper foil 37 and sent to the power pins 33 / 39 of the MOSFET power switch 20, the small capacitor 64, the large capacitor 52, and the LTE module 32 to supply power, generating a current i6 and a low-frequency pulsed magnetic field B6, and then flowing back to the first ground copper foil G1 on the first surface layer (not shown in the figure), the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer (not shown in the figure), and the ground copper foil G4 on the second surface layer (not shown in the figure) through the ground pins 35 / 36 of the LTE module 32 and the ground via 2.Since the third ground copper foil G2 of the first inner layer is the main return path of the entire LTE power supply, the current i6 passing through the power pins 33 / 39 of the MOSFET power switch 20, small capacitor 64, large capacitor 52, power copper foil 63, and LTE module 32 will flow along the ground pins 35 / 36 of the LTE module 32, ground vias 2, the third ground copper foil G2 of the first inner layer, the negative pad of the small capacitor 64, the negative pad of the large capacitor 52, and the third ground copper foil G2 of the first inner layer back to the ground via 110. Then, it is switched to the third ground copper foil G2 of the first inner layer and the second ground copper foil G3 of the second inner layer through the ground via 110. From the "+" pad and power copper foil 72 of the output capacitor 107 in the BUCK power module 51, power via 79, the first inner layer power copper foil 86, power via 78, the first surface layer power copper foil 37, MOSFET power switch 20, the power pins 33 / 39 of the LTE module 32, large capacitor 52, small capacitor 64, power copper foil 63, the power pins 33 / 39 of the LTE module 32, and the ground pins 35 / 36 of the LTE module 32. The entire LTE power supply line (including the "+" pad and power copper foil 72 of the output capacitor 107 in the BUCK power module 51, power via 79, the first inner layer power copper foil 86, power via 78, the first surface layer power copper foil 37, MOSFET power switch 20, the power pins 33 / 39 of the LTE module 32, large capacitor 52, small capacitor 64, power copper foil 63, the power pins 33 / 39 of the LTE module 32, and the ground pins 35 / 36 of the LTE module 32) is surrounded by a complete ground plane and ground wires, without being adjacent to other signal traces or power traces. There are no problems of adjacent interference or cross-ground segmentation. At the same time, the distance between the LTE power supply line and the ground copper foil of the adjacent layer is very close (for example, the PP thickness from the first surface layer to the first inner layer is only 3 mil to 8 mil), resulting in a very small return path, very little noise generated by the power line itself (the larger the return path, the greater the noise generated by the power line itself), very little pulse magnetic field generated, very little pulse electric field generated, and the external EMI radiation can be ignored, and there is no interference to other signal traces and power traces on the board. Therefore, this kind of layer stack, layout of power devices, power copper foil, and structure setting of loads (such as wifi and LTE modules) is scientific and reasonable. The power line and the ground copper foils of each layer form a planar capacitor, and the planar capacitor can filter out the noise above GHz, without worrying about the excessive EMI radiation and spurious of the product.

[0108] An LTE antenna radiator and a clearance area 99 are provided on the second surface layer at the B end of the board edge below the substrate 73 (B end). The LTE module 32 + MOSFET power switch 20 is arranged at a position close to the LTE antenna radiator and the clearance area 99 (close to the right side of the board edge), which is convenient for the LTE module 32 to lead out radio frequency traces (marked in the figure) and be electrically connected to the LTE antenna radiator. The MOSFET power switch 20 uses a PMOSFET. The source pin 68 of the MOSFET power switch 20 is connected to the positive pad of the large-capacity capacitor 34 through the power copper foil 37, and the large-capacity capacitor 34 is used for energy storage and discharge; the drain pin 68 of the MOSFET power switch 20 is connected to the positive pads of the large-capacity capacitor 12 / the positive pad of the large-capacity capacitor 52 / the positive pad of the small capacitor 63 / the positive pad of the small capacitor 64 through the power copper foil 63. The positive pads of the large-capacity capacitor 12 / the positive pad of the large-capacity capacitor 52 / the positive pad of the small capacitor 63 / the positive pad of the small capacitor 64 are respectively connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2; the positive pads of the large-capacity capacitor 12 (not marked in the figure) and the positive pad of the small capacitor 63 (not marked in the figure) are vertically placed towards the B end of the substrate and connected to the power copper foil 63; the positive pads of the large-capacity capacitor 12 (not marked in the figure) and the positive pad of the small capacitor 63 (not marked in the figure) are vertically placed towards the A end of the substrate, and the positive pads of the large-capacity capacitor 12 and the small capacitor 63 are respectively connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2. The positive pads of the large-capacity capacitor 52 (not marked in the figure) and the positive pad of the small capacitor 64 (not marked in the figure) are vertically placed towards the A end of the substrate and connected to the power copper foil 63; the positive pads of the large-capacity capacitor 52 (not marked in the figure) and the positive pad of the small capacitor 64 (not marked in the figure) are placed towards the B end of the substrate, and the positive pads of the large-capacity capacitor 52 and the small capacitor 64 are respectively connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2. The large-capacity capacitor 52 and the large-capacity capacitor 12 are used to provide low-frequency dynamic current response for the LTE module 32 when receiving / transmitting signals in the operating frequency range of 700 MHz to 2.7 G, while the small capacitor 64 and the small capacitor 63 provide high-frequency bypass for the LTE module 32 in the operating frequency range of 700 MHz to 2.7 G to filter out high-frequency noise generated by the LTE module 32. The grounding pins 35 and 36 of the LTE module 32 are connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2, forming a loop with the positive pads of the large-capacity capacitor 12 / the large-capacity capacitor 52 / the small capacitor 63 / the small capacitor 64 (connected to the ground copper foil of each layer of the substrate 73), providing a low-impedance return path for the low-frequency energy storage and discharge and high-frequency filtering of the large-capacity capacitor 12 / the large-capacity capacitor 52 / the small capacitor 63 / the small capacitor 64. The MOSFET power switch 20 is a power switch used to control the power-on sequence of the power pins 33 and 39 of the LTE module 32.

[0109] The MOSFET power switch 20, large-value capacitors 12 / 52, and small capacitors 63 / 64 are close to the power pins 33 and 36 of the LTE module 32. The length of the power trace 63 between the large-value capacitors 12 / 52 and small capacitors 63 / 64 and the power pins 33 and 36 of the LTE module 32 is less than 30 mm. Otherwise, it will affect the low-frequency dynamic discharge of the large-value capacitors 12 / 52 and the power supply noise suppression of the small capacitors 63 / 64 for the LTE module. The length of the MOSFET power switch 20 is less than 80 mm.

[0110] The GPS module 31 (load) + differential pressure linear regulator 19 is set near the B7 - B8 position and within the second-layer projection area of the GPS antenna, near the right edge of the board. While the conventional Figure 1 scheme is to set the LDO low-dropout linear regulator 3 at the output capacitor position of the BUCK power module. This is the difference point. A capacitor 10 is set at the input pin of the differential pressure linear regulator 19, and a capacitor 16 is set at the output pin. The capacitor 10 + differential pressure linear regulator 3 + capacitor 16 are close to the GPS module 31 (load). The distances between the capacitor 16 and capacitor 10 and the differential pressure linear regulator 19 should not exceed 30 mm. The length of the power trace 18 between the capacitor 16 + differential pressure linear regulator 19 + capacitor 16 and the GPS module 31 (load) is less than 20 mm to avoid affecting the suppression of ripple and noise. Since the input voltage of the differential pressure linear regulator 19 is about 3.3V - 4.5V, and the output voltage is about 3.0V - 3.3V, the voltage drop of the power trace 18 between the output of the differential pressure linear regulator 19 and the GPS module 31 (load) will affect the normal operation of the GPS module 31. Therefore, the closer the differential pressure linear regulator 19 is to the GPS module 31, the smaller the voltage drop of the backend power supply voltage obtained by the GPS module 31 (load), and the smaller the ripple and noise. The front-end voltage drop generated by the length of the power trace 6 of the input of the differential pressure linear regulator 19 + capacitor 10 has a very small impact on the GPS module 31 (load). Therefore, the capacitor 10 + differential pressure linear regulator 19 + capacitor 16 can be far from the BUCK power module 51, but not far from the GPS module 31 (load).

[0111] The positive electrode pads of the input capacitor 10 and the output capacitor 16 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2; the positive electrode pad of the input capacitor 10 is connected to the input pin of the low-dropout linear regulator 19 through the power trace branch 6, and the positive electrode pad of the output capacitor 16 is connected to the output pin of the low-dropout linear regulator 19 and the GPS module 31 through the power trace 18. Since the low-dropout linear regulator 19 is connected in series between the power trace branch 6 and the GPS module 31, the currents of the input pin and the output pin of the low-dropout linear regulator 19 are basically equal, and a current i3 is generated in the power trace branch 6 and the power trace 18. The power trace branch 6 is electrically connected to the power copper foil 37.

[0112] The MCU module 102 (load) + the low-dropout linear regulator 13 are arranged between the GPS module 31 and the LTE module 32. The low-dropout linear regulator 13 + the input capacitor 68 + the output capacitor 69 are close to the MCU module 102 (load): the input capacitor 68 and the output capacitor 69 are respectively close to the low-dropout linear regulator 13, and the distance shall not exceed 30 mm to avoid affecting the suppression of ripple and noise. Since the input voltage of the low-dropout linear regulator 13 is about 3.3V - 4.5V, and the output voltage of the low-dropout linear regulator 13 is about 3.0V - 3.3V, the voltage drop of the power trace 15 between the output end of the low-dropout linear regulator 13 and the MCU module 102 (load) will affect the normal operation of the MCU module 102. Therefore, the closer the low-dropout linear regulator 13 is to the MCU module 102, the smaller the voltage drop of the power supply voltage obtained by the MCU module 102 (load) at the back end, and the smaller the ripple and noise; while the influence of the front-end voltage drop generated by the length of the power trace 6 of the input end of the low-dropout linear regulator 13 + the capacitor 10 on the MCU module 102 (load) is very small. Therefore, the capacitor 68 + the low-dropout linear regulator 13 + the capacitor 69 can be far away from the BUCK power module 51, but cannot be far away from the MCU module 102 (load). The positive electrode pads of the input capacitor 68 and the output capacitor 69 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2; the positive electrode pad of the input capacitor 68 is connected to the input pin of the low-dropout linear regulator 13 through the power trace branch 5, and the positive electrode pad of the output capacitor 69 is connected to the output pin of the low-dropout linear regulator 13 and the MCU module 102 through the power trace 15. Since the low-dropout linear regulator 13 is connected in series between the power trace branch 5 and the MCU module 102, the currents of the input pin and the output pin of the low-dropout linear regulator 13 are basically equal, and a current i4 is generated in the power trace branch 5 and the power trace 15. The power trace branch 5 is electrically connected to the power copper foil 37;

[0113] A Bluetooth module 70, an input capacitor 21 + a low dropout linear regulator 24 + an output capacitor 27 are arranged on the left side (in the X direction of the substrate) of the low dropout linear regulator 19. The Bluetooth module 70 is close to the right edge of the board, which is convenient for arranging a Bluetooth antenna (not shown in the figure) on the right edge of the board. The input capacitor 21 + the low dropout linear regulator 24 + the output capacitor 27 are arranged on the left side of the Bluetooth module 70. The positive pads of the input capacitor 21 and the positive pad of the output capacitor 27 are respectively close to the input pin and the output pin of the low dropout linear regulator 24, and the distance shall not exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. Since the input voltage of the low dropout linear regulator 24 is about 3.3 V to 4.5 V, and the output voltage of the low dropout linear regulator 24 is about 3.0 V to 3.3 V, the voltage drop of the power supply trace 26 between the output of the low dropout linear regulator 24 and the Bluetooth module 70 (load) will affect the normal operation of the Bluetooth module 70. Therefore, the closer the low dropout linear regulator 24 is to the Bluetooth module 70, the smaller the voltage drop of the backend power supply voltage obtained by the Bluetooth module 70 (load), and the smaller the ripple and noise. The influence of the front-end voltage drop generated by the length of the power supply trace 22 of the input of the low dropout linear regulator 24 + the capacitor 21 on the Bluetooth module 70 (load) is very small. Therefore, the capacitor 21 + the low dropout linear regulator 24 + the capacitor 69 can be far away from the BUCK power module 51, but cannot be far away from the Bluetooth module 70 (load). The positive pads of the input capacitor 21 and the positive pad of the output capacitor 27 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2. The positive pad of the input capacitor 21 is connected to the input pin of the low dropout linear regulator 24 through a power supply trace branch 22, and the positive pad of the output capacitor 27 is connected to the output pin of the low dropout linear regulator 24 and the Bluetooth module 70 through a power supply trace 26. Since the low dropout linear regulator 24 is connected in series between the power supply trace branch 22 and the Bluetooth module 70, the currents of the input pin and the output pin of the low dropout linear regulator 24 are basically equal, and a current i6 is generated in the power supply trace branch 22 and the power supply trace 26. The power supply trace branch 22 is electrically connected to the power copper foil 37;

[0114] A Wi-Fi module 101, a bead 81 + a large capacitor 95 + a small capacitor 96 are arranged on the left side (in the X direction of the substrate) of the low-dropout linear regulator 13. The Wi-Fi module 101 is close to the right edge of the board, which is convenient for arranging a Wi-Fi antenna (not shown in the figure) on the right edge of the board. The bead 81 + the large capacitor 95 + the small capacitor 96 are arranged on the left side of the Wi-Fi module 101. One pin of the bead 81 is connected to the power copper foil 37, and the other pin of the bead 81 is connected to the positive pads of the large capacitor 95 and the small capacitor 96 through the power trace 77. The positive pads of the large capacitor 95 and the small capacitor 96 are connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2; and the positive pads of the large capacitor 95 and the small capacitor 96 are respectively close to the Wi-Fi module 101, and the distance shall not exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. The bead 81 + the large capacitor 95 + the small capacitor 96 can be far away from the BUCK power module 51, but cannot be far away from the Wi-Fi module 101 (load). The current injected into the Wi-Fi module 101 from the power copper foil 37, the bead 81, and the power trace 77 is i5. The Wi-Fi module 101 belongs to a high-frequency and large-current dynamic flip load: Wi-Fi 2.4G operates at 2.4 GHz to 2.5 GHz, and Wi-Fi 5G operates at 5.15 GHz to 5.825 GHz. The power copper foil 37 and the bead 81 are required to have sufficient current-carrying capacity, and at the same time, the large capacitor 95 meets the dynamic response of the Wi-Fi module 101 during high-frequency and large-current dynamic flipping. The Wi-Fi module 101 is internally connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2. At the same time, a reverse return current i51 is generated on the ground copper foil of any layer of the substrate 73. The return current i51 will also pass through the positive pads of the small capacitor 96 and the large capacitor 95 and the nearby ground vias 2, and finally reach the ground copper foil of any layer of the substrate 73 (including the third ground copper foil G2 of the first inner layer adjacent to the first surface layer Wi-Fi module 101 and the power trace 77).

[0115] An audio power amplifier module 30, a magnetic bead 76 + a large capacitor 97 + a small capacitor 98 are arranged on the left side (substrate X direction) of the MOFET transistor (power switch) 20. The audio power amplifier module 30 is close to the right board edge, which is convenient for arranging a speaker socket (not shown in the figure) on the right board edge and connecting it to a speaker cable (not shown in the figure). The magnetic bead 76 + the large capacitor 97 + the small capacitor 98 are arranged on the left side of the audio power amplifier module 30. One pin of the magnetic bead 76 is connected to the power copper foil 75 through the power trace branch 71, and the other pin of the magnetic bead 76 is connected to the positive electrode pads of the large capacitor 97 and the small capacitor 98 through the power trace 77. The positive electrode pads of the large capacitor 97 and the small capacitor 98 are connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2; and the positive electrode pads of the large capacitor 97 and the small capacitor 98 are respectively close to the audio power amplifier module 30, and the distance shall not exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. The magnetic bead 76 + the large capacitor 97 + the small capacitor 98 can be far away from the BUCK power supply module 51, but cannot be far away from the audio power amplifier module 30 (load). The current injected into the audio power amplifier module 30 from the power copper foil 75, the magnetic bead 76, and the power trace 77 is i4. The audio power amplifier module 30 is a load with low frequency and large current dynamic inversion, and its operating frequency is 20 Hz to 20 kHz. The power trace branch 71, the power copper foil 75, and the magnetic bead 76 are required to have sufficient current-carrying capacity, and at the same time, the large capacitor 97 meets the dynamic response of the audio power amplifier module 30 during low-frequency and large-current dynamic inversion.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A substrate, characterized in that: The invention comprises a first surface layer, an external cable is arranged on the first surface layer, and the external cable is used to connect an external device; the first surface layer comprises a first end and a second end opposite to each other along a first direction, and a third end and a fourth end opposite to each other along a second direction, in the first direction, the external cable is arranged close to the first end of the first surface layer, the external cable comprises a plurality of cable lines, the plurality of cable lines extend along the first direction and are arranged at intervals along the second direction, one of the plurality of cable lines is a grounding cable line, and the grounding cable line is arranged close to the third end; the first surface layer is also provided with a first grounding copper foil connected to the grounding cable line; A first inner layer, the first inner layer is adjacent to the first surface layer, the first inner layer is provided with a power copper foil, the power copper foil is electrically connected to a BUCK power module, and the power copper foil is used to supply power to the electronic components on the substrate; In a direction perpendicular to the substrate, the projection of the power copper foil is located within the projection range of the ground cable and the first ground copper foil.

2. The substrate according to claim 1, characterized in that It also includes a second surface layer, which is arranged opposite to the first surface layer in a direction perpendicular to the substrate; the BUCK power supply module is arranged on the second surface layer, and the BUCK power supply module is electrically connected to the power supply copper foil through a power supply via.

3. The substrate according to claim 2, characterized in that It also includes a second inner layer, which is adjacent to the second surface layer, and the second inner layer is provided with a second ground copper foil; other elements are also provided on the second surface layer, and in a direction perpendicular to the substrate, the projection of the other elements is located within the projection range of the power copper foil, and the projection of the other elements and the projection of the power copper foil are both located within the projection range of the second ground copper foil.

4. The substrate according to claim 3, characterized in that The other components include power supply wiring, signal wiring or R232 module.

5. The substrate according to claim 3, characterized in that The first inner layer is also provided with a third ground copper foil, which is located on the side of the power copper foil facing the fourth end; in the direction perpendicular to the substrate, except for the grounding cable line, the projections of multiple cables are all located within the projection range of the third ground copper foil.

6. The substrate according to claim 5, characterized in that The first inner layer is further provided with a grounding element, which is located on a side of the power copper foil facing the third end, and the power copper foil is electrically connected to the first ground copper foil and the second ground copper foil.

7. The substrate according to claim 6, characterized in that The grounding element includes a ground copper foil or a ground wire.

8. The substrate according to claim 7, characterized in that The grounding element is a ground wire, a plurality of ground vias are arranged on the ground wire, and the ground wire is electrically connected to the first ground copper foil and the second ground copper foil through the plurality of ground vias.

9. The substrate according to claim 1, characterized in that An external connector is also provided on the first surface layer, and the external cable is connected to the external connector.

10. An electronic device, characterized in that: Comprising a substrate as claimed in any one of claims 1 to 9.

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