Embedded flash memory below 110nm and preparation method thereof

Abstract

The invention relates to an embedded flash memory below 110nm and a preparation method thereof, the embedded flash memory below 110nm comprises a substrate, a storage array area and a peripheral logic area, the storage array area and the peripheral logic area are arranged on the substrate, the storage array area comprises at least one storage unit, and the storage unit comprises a common source electrode located in the substrate, a common source electrode located in the substrate, and a common source electrode located in the substrate, the common line is positioned above the common source electrode and is connected with the common source electrode; the pair of stacked grids are located on the two sides of the common line respectively, and each stacked grid comprises a floating grid and a control grid vertically stacked on the floating grid; a pair of select gates located beside the non-common line sides of the two stacked gates, respectively; the peripheral logic region comprises at least one logic transistor, and the logic transistor comprises a logic grid electrode; wherein the height of the control grid electrode in the storage unit is the same as that of the logic grid electrode of the logic transistor. The embedded flash memory is good and stable in performance and good in reliability, and the preparation method is simple, convenient and low in cost.

Description

Technical Field

[0001] The present invention relates to an embedded flash memory below 110 nm and a manufacturing method thereof, and particularly to an embedded flash memory below 90 nm and a manufacturing method thereof. Background Art

[0002] In currently widely used electronic products such as microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., embedded flash memories, abbreviated as eFlash, are used. Compared with the traditional EEPROM solution, eFlash has the advantages of fast read / write speed, small area, low power consumption, etc., and has played an increasingly important role in current application scenarios such as the Internet of Things (IoT) and automotive electronics.

[0003] In the solutions of embedded flash memories, there are mainly traditional floating-gate-based structures and charge-trapping structures. In the charge-trapping structure, charges are "trapped" in the insulating storage medium through the charge "trapping" mechanism. The main applications of this solution are silicon-oxide-nitride-oxide-silicon (SONOS), for example, silicon oxide - silicon nitride - silicon oxide are deposited on a silicon substrate in sequence. The process manufacturing is relatively simple, but due to the characteristics of the nitride itself, the reliability is poor, and it can generally only be used in consumer products. For high-end applications, an embedded flash memory with a floating-gate structure is still required.

[0004] In the embedded flash memory with a floating-gate structure, the most widely used structure at present is the ESF3 structure of Silicon Storage Technology (SST) in the United States. This structure uses three layers of gates, including: an erase gate (EG), a control gate (CG), and a floating gate (FG). Programming is performed by a self-source-side injection method, and erasing is performed by a gate-to-gate method. It can achieve more than 300,000 times of repeated read / write, and has good reliability and application scenarios. However, the difficulty of the ESF3 structure lies in the complex process manufacturing. The erase gate needs to wrap the floating gate to achieve sufficient erasing efficiency and reduce the erasing voltage. At the same time, three different gates need to be formed, and it is difficult to control the process uniformity, and the process mass production window is small.

[0005] Another commonly used embedded flash memory structure is the dual-transistor (2T) structure of NXP Semiconductors in the Netherlands. There are two select gates (SGs) and two stacked gates in the storage unit, and the storage unit structure is symmetric about the left and right mirror images. In the stacked gates, the control gate (CG) is stacked on the floating gate (FG). Compared with the ESF3 of SST Company, its structure and manufacturing are simpler. Programming injects electrons by the Fowler-Nordheim method, which requires a high voltage. In this way, the area of the pumping circuit in the peripheral logic area is relatively large, and the high voltage will also affect the reliability of the flash memory device.

[0006] The storage devices in the embedded flash memory need to be compatible with the logic process. The gate height of the storage devices in the embedded flash memory also needs to be compatible with that of the logic devices. Currently, in the 2T - structured embedded flash memory fabricated at 110 nm and above nodes in China, the gate height of the peripheral logic devices is about 2000 Å (angstroms), the CG height of the storage devices is about 1200 Å, the FG height is about 800 Å, and the SG height is about 2000 Å. As the industry's requirement for reducing the size of the embedded flash memory becomes higher and higher, the gate heights of the logic devices and the storage devices also need to be reduced accordingly. In the process of 110 nm and below, such as in the process of 90 nm and below, the gate height of the peripheral standard logic transistors in the embedded flash memory is reduced from the previous 2000 Å to about 1000 Å. To ensure that the storage device has a sufficient coupling ratio, the FG height cannot be lower than 750 Å; if the existing preparation method for 110 nm and above nodes is adopted, then the CG height is less than 300 Å. In the subsequent ion implantation (IMP) process, the implanted ions are likely to penetrate the CG and be implanted into the ONO, affecting the reliability of the flash memory. Therefore, there is a need in the industry for a smaller - sized embedded flash memory with good performance and its new preparation method. Summary of the Invention

[0007] The present invention provides an embedded flash memory below 110 nm and a preparation method thereof. The embedded flash memory has good and stable performance, good reliability, and the preparation method is simple, convenient and low - cost.

[0008] The first aspect of the present invention relates to an embedded flash memory below 110 nm, comprising: a substrate, a storage array region and a peripheral logic region on the substrate, the storage array region containing at least one storage unit, and the storage unit comprising: a common source electrode located in the substrate, a common line located above and connected to the common source electrode; a pair of stacked gates located on both sides of the common line, each stacked gate including a floating gate and a control gate vertically stacked above it; a pair of select gates respectively located beside the non - common - line sides of the two stacked gates; the peripheral logic region containing at least one logic transistor, and the logic transistor comprising a logic gate; the control gate in the storage unit has the same height as the logic gate of the logic transistor.

[0009] In a preferred embodiment, the select gate has the same or substantially the same height as the stacked gate, the select gate includes an upper part and a lower part, and there is a dielectric layer between the control gate and the floating gate in the stacked gate; The height of the selection gate is substantially the same as that of the stacked gate, which means that there is no dielectric layer between the upper and lower parts of the selection gate, resulting in its height being slightly lower than that of the stacked gate; the height difference is the height of the dielectric layer in the stacked gate. More preferably, the structures and heights of the selection gate and the stacked gate are the same; the heights of the upper and lower parts of the selection gate are respectively the same as those of the control gate and the floating gate, and there is also a dielectric layer between the upper and lower parts of the selection gate, with the same height as that in the stacked gate; the lower part of the selection gate is electrically connected above the dielectric layer.

[0010] In another preferred embodiment, the memory array includes rows and columns, and the arrangement directions of the memory cells in the array are the same; the connection direction of the same parts of the two selection gates in the memory cell is the column direction, and the upper parts of the corresponding selection gates and the control gates of the memory cells in each row are connected along that row to form a strip; the corresponding floating gates of the memory cells in each row are not connected and are disconnected at the gaps between adjacent memory cells; or the connection direction of the same parts of the two selection gates in the memory cell is the row direction, and the upper parts of the corresponding selection gates and the control gates of the memory cells in each column are connected along that column to form a strip; the corresponding floating gates of the memory cells in each column are not connected and are disconnected at the gaps between adjacent memory cells.

[0011] More preferably: in the storage cell, the selection gate and the stacked gate have the same structure and height; there is a dielectric layer between the control gate and the floating gate in the stacked gate; the heights of the upper and lower parts of the selection gate are respectively the same as those of the control gate and the floating gate, and there is also a dielectric layer between the upper and lower parts of the selection gate, with the same height as that in the stacked gate; in the storage array, the connection direction of the same parts of the two selection gates in the storage cell is the column direction, and for each row, the upper and lower parts of the selection gates corresponding to each storage cell in the row, and the dielectric layer in the middle, are respectively connected along the row to form a strip; in each row, in the dielectric layer between the upper and lower part strips of the selection gates aligned vertically, there is at least one through hole, the bottom of the through hole is electrically connected to the surface of the lower part strip of the selection gate, and the top exposes the top surface of the dielectric layer, so that the lower part strip of the selection gate is electrically conducted to above the dielectric layer; preferably, in each row, along the row, every 16 - 32 storage cells, there is a through hole in the dielectric layer between the upper and lower part strips of the selection gates aligned vertically; or in the storage array, the connection direction of the same parts of the two selection gates in the storage cell is the row direction, and for each column, the upper and lower parts of the selection gates corresponding to each storage cell in the column, and the dielectric layer in the middle, are respectively connected along the column to form a strip; in each column, in the dielectric layer between the upper and lower part strips of the selection gates aligned vertically, there is at least one through hole, the bottom of the through hole is electrically connected to the surface of the lower part strip of the selection gate, and the top exposes the top surface of the dielectric layer, so that the lower part strip of the selection gate is electrically conducted to above the dielectric layer; preferably, in each column, along the column, every 16 - 32 storage cells, there is a through hole in the dielectric layer between the upper and lower part strips of the selection gates aligned vertically.

[0012] Even more preferably: in the storage array, the connection direction of the same parts of the two selection gates in the storage cell is the column direction, and in each row, at the position corresponding to the through hole in the lower dielectric layer in the upper part strip of the selection gate, there is also a through hole, which is electrically insulated from the upper part strip of the selection gate around it, the bottom is connected and internally electrically connected to the through hole in the lower dielectric layer, and the top exposes the top surface of the upper part strip of the selection gate; or in the storage array, the connection direction of the same parts of the two selection gates in the storage cell is the row direction, and in each column, at the position corresponding to the through hole in the lower dielectric layer in the upper part strip of the selection gate, there is also a through hole, which is electrically insulated from the upper part strip of the selection gate around it, the bottom is connected and internally electrically connected to the through hole in the lower dielectric layer, and the top exposes the top surface of the upper part strip of the selection gate.

[0013] In another preferred embodiment, the embedded flash memory below 110nm of the present invention is an embedded flash memory device of 90nm and below.

[0014] The second aspect of the present invention relates to a method for manufacturing the embedded flash memory below 110 nm as described above, comprising the following steps: The control gate in the storage unit and the logic gate in the logic transistor are formed in such a way that in the same deposition step, a layer of gate material is simultaneously deposited at predetermined positions in the storage array region and the peripheral logic region, and then different photomasks are respectively used to etch the gate material deposited on the array region and the peripheral logic region.

[0015] In a preferred embodiment, the method further comprises the following steps: Before forming the control gate and the logic gate, there is a deposited material formed on the substrate surface in the logic region along with the preparation of the storage units in the storage array, and the deposited material is removed by etching.

[0016] In another preferred embodiment, the select gate comprises upper and lower parts, and there is a dielectric layer between the control gate and the floating gate of the stacked gate; the method further comprises the following steps: When the select gate and the stacked gate have the same height, there is a dielectric layer between the upper and lower parts of the select gate, and the select gate and the stacked gate are formed together through the same preparation steps; or when the select gate and the stacked gate have substantially the same height, there is no dielectric layer between the upper and lower parts of the select gate, and the select gate and the stacked gate are formed together through substantially the same preparation steps, the difference being that the deposition and formation process of the dielectric layer in the stacked gate is not included in the preparation of the select gate.

[0017] More preferably: The select gate and the stacked gate in the storage unit have the same structure and height, the heights of the upper and lower parts of the select gate are respectively the same as those of the control gate and the floating gate, there is a dielectric layer between the upper and lower parts of the select gate, and the height is the same as that in the stacked gate, and the lower part of the select gate is electrically connected to above the dielectric layer; The storage array includes rows and columns, and the arrangement directions of the storage units in the array are the same; The method sequentially comprises the following steps: (1) On the substrate, a layer of gate oxide material and a layer of lower gate material are respectively deposited successively; then a photomask is used to etch away the deposited lower gate layer at the gap between adjacent storage units in the predetermined array region, at the position between the floating gates corresponding to the predetermined adjacent storage units, and to etch away the deposited lower gate layer in the region of the predetermined logic region; and no etching is performed at the position between the lower parts of the select gates corresponding to the predetermined adjacent storage units. When the connection direction of the same parts of the two select gates in the storage unit is the column direction, the etching between adjacent storage units in the array region is: along the row direction, at the position between the floating gates corresponding to the predetermined adjacent storage units in the region of each row of storage units in the predetermined row, perform etching; or When the connection direction of the same parts of the two select gates in the memory cell is the row direction, the etching between adjacent memory cells in the array region is as follows: along the column direction, in the region of each predetermined column of memory cells, at the position between the floating gates corresponding to the predetermined adjacent memory cells, etching is performed; (2) A dielectric oxide material layer is simultaneously deposited on the lower gate layer in the array region and on the gate oxide layer in the logic region; then, using a photomask, vias are etched in the dielectric layer deposited in the array region, and the dielectric layer deposited in the logic region is etched away; Etching vias in the dielectric layer deposited in the array region includes: When the connection direction of the same parts of the two select gates in the memory cell is the column direction, in the region of each predetermined row of memory cells, in the dielectric layer above the region of the lower part of the predetermined select gate, at least one via is etched, the bottom of the via contacts the surface of the lower gate layer, and the top exposes the top surface of the dielectric layer; When the connection direction of the same parts of the two select gates in the memory cell is the row direction, in the region of each predetermined column of memory cells, in the dielectric layer above the region of the lower part of the predetermined select gate, at least one via is etched, the bottom of the via contacts the surface of the lower gate layer, and the top exposes the top surface of the dielectric layer; (3) An upper gate material layer is simultaneously deposited on the dielectric layer in the array region and on the gate oxide layer in the logic region; then, using a photomask in the memory array region, in the regions other than the predetermined select gate and control gate, etching is performed downward simultaneously to the gate oxide layer, removing the upper and lower gate layers and the dielectric layer therebetween in these regions, and simultaneously forming strips of the upper part of the select gate, strips of the lower part of the select gate, strips of the control gate, and floating gates; then, using a photomask in the logic region, in the regions other than the predetermined logic gate, the upper gate material layer is etched away to form a logic gate.

[0018] More preferably, etching vias in the dielectric layer deposited in the array region includes: when the connection direction of the same parts of the two select gates in the memory cell is the column direction, in the region of each predetermined row of memory cells, at positions along each row at intervals of every predetermined 16 - 32 memory cells, in the dielectric layer above the region of the lower part of the predetermined select gate, at least one via is etched; or when the connection direction of the same parts of the two select gates in the memory cell is the row direction, in the region of each predetermined column of memory cells, at positions along each column at intervals of every predetermined 16 - 32 memory cells, in the dielectric layer above the region of the lower part of the predetermined select gate, at least one via is etched.

[0019] More preferably, the operations of etching to form the upper part strips of the select gate, the lower part strips of the select gate, the control gate strips, and the floating gate in the array region are specifically as follows: When the connection direction of the same positions of the two select gates in the memory cell is the column direction, along the row direction, in the region of each row of memory cells as predetermined, two upper part strips of the select gate, two lower part strips of the select gate, two control gate strips, and the floating gate are etched and formed in each row; or when the connection direction of the same positions of the two select gates in the memory cell is the row direction, along the column direction, in the region of each column of memory cells as predetermined, two upper part strips of the select gate, two lower part strips of the select gate, two control gate strips, and the floating gate are etched and formed in each column.

[0020] In yet another preferred embodiment, it further includes the following steps: Before step (1), a well for the memory cells in the memory array is formed in the substrate; and between step (2) and step (3), a well for the logic transistors in the peripheral logic region is formed, then the gate oxide layer deposited and formed in step (1) is removed on the substrate surface of the logic region, and then the gate oxide layer of the logic region is regrown. Brief Description of the Drawings

[0021] The same reference numerals in the drawings indicate the same or similar elements.

[0022] Figure 1 is a partial top view of a specific embodiment of the embedded flash memory of the present invention.

[0023] Figure 2 is Figure 1 a schematic diagram of the substrate in the flash memory shown along the B - B sectional line before the formation of the memory cell and the logic device starts.

[0024] Figure 3 is at Figure 2 a schematic diagram of forming an N well of the memory array in the substrate shown.

[0025] Figure 4 is at Figure 3 a schematic diagram of successively depositing and forming a layer of gate oxide material and a layer of lower gate material on the substrate shown.

[0026] Figure 5a is at Figure 4 a schematic diagram before etching to form the partition PC between the floating gates of adjacent cells in each row of the memory cells in the predetermined memory array region of the structure shown.

[0027] Figure 5b-5c are respectively Figure 1 top views of a row of memory cells in the flash memory shown before and after etching to form the partition PC between the floating gates of adjacent memory cells.

[0028] Figure 5d It is a schematic diagram after etching to form a partition PC between floating gates of adjacent cells in each row of memory cells in the lower gate layer within a predetermined storage array area of the structure shown, and after etching away the lower gate layer within a predetermined logic area. Figure 4 It is a schematic diagram after etching to form a partition PC between floating gates of adjacent cells in each row of memory cells in the lower gate layer within a predetermined storage array area of the structure shown, and after etching away the lower gate layer within a predetermined logic area.

[0029] Figure 6 It is Figure 5d a schematic diagram of depositing a dielectric layer on the lower gate material in the storage array area of the structure shown and on the gate oxide layer in the logic area.

[0030] Figure 7a It is Figure 6 a schematic diagram of etching away the deposited dielectric layer in the logic area of the structure shown.

[0031] Figure 7b It is Figure 1 a top view of a row of memory cells in the flash memory shown during the step of etching to form vias in the dielectric layer.

[0032] Figure 8a It is a schematic diagram of respectively forming P-wells and N-wells of logic devices in the low-voltage (LV) and high-voltage (HV) logic areas in the substrate of the structure shown in 7a.

[0033] Figure 8b It is Figure 8a a schematic diagram of removing the remaining gate oxide layer that was previously formed together with the storage array in the low-voltage and high-voltage logic areas of the structure shown.

[0034] Figure 9 It is Figure 8b a schematic diagram of respectively forming a low-voltage gate oxide layer and a high-voltage gate oxide layer in the low-voltage and high-voltage logic areas of the structure shown.

[0035] Figure 10 It is Figure 9 a schematic diagram of depositing a layer of upper gate material on the dielectric layer in the storage array area of the structure shown and on the gate oxide layer in the logic area.

[0036] Figure 11a-11b They are respectively Figure 1 schematic diagrams of the structure of a memory cell in the flash memory shown along the C-C section line before and after etching to form the gate.

[0037] Figure 11c-11d They are respectively Figure 1 schematic diagrams of the structure of a low-voltage logic device in the flash memory shown along the D-D section line before and after etching to form the low-voltage logic gate.

[0038] Figure 11e-11f They are respectively Figure 1Schematic diagrams before and after etching to form a high-voltage logic gate of the structure of the high-voltage logic device in the flash memory shown along the E-E cross-sectional line.

[0039] Figure 12a-12b Respectively are Figure 1 Schematic diagrams of the structure of a memory cell in the flash memory shown along the C-C cross-sectional line during the steps of sequentially forming the isolation wall outside the gate, source / drain ion implantation, and removing the gate oxide layer above the source / drain.

[0040] Figure 13 Is Figure 1 Circuit schematic diagram of the 2×2 memory array of the flash memory shown.

[0041] Figure 14 Is Figure 13 Bias signals to which two memory cells in the first row of the flash memory array shown are connected during different operations. Detailed implementation manners

[0042] The relevant definitions in this application of the present invention are described as follows.

[0043] The height described herein refers to the dimension in the direction vertically upward from the surface of the substrate of the memory array.

[0044] The up and down described herein refer to the up and down relationship presented in the direction perpendicular to the surface of the substrate of the memory array.

[0045] The height of the select gate and the stacked gate being substantially the same means that there is no dielectric layer between the upper and lower parts of the select gate, resulting in its height being slightly lower than that of the stacked gate; the height difference is the height of the dielectric layer in the stacked gate.

[0046] The "corresponding gates of the memory cells in each row / or each column" described herein refer to the gates with the same orientation in each memory cell in that row / or that column, and these gates can be directly connected into a straight line along the direction of that row / or that column. The gates can be: the select gate, the control gate, the floating gate, the upper part of the select gate, or the lower part of the select gate.

[0047] The embedded flash memory device described in this application of the present invention is a small-sized embedded flash memory, preferably an embedded flash memory of 110 nm or less, more preferably 90 nm or less.

[0048] The embedded flash memory device of this application of the present invention includes: a memory array area composed of memory cells, and a logic area composed of standard logic devices (or standard logic transistors) on its periphery.

[0049] The peripheral logic region may include a low-voltage region and / or a high-voltage region. The low-voltage region may contain multiple low-voltage standard logic devices (or logic transistors), and the types of these low-voltage logic transistors may be different, depending on their uses, and the types of wells they are located in will also be different accordingly. Similarly, the high-voltage region may contain multiple high-voltage standard logic devices (or logic transistors), and the types of these high-voltage logic transistors may be different, depending on their uses, and the types of wells they are located in will also be different accordingly.

[0050] The gates of all logic devices (or logic transistors) in the logic region have the same height, and they are formed by the same deposition step followed by etching.

[0051] In the memory array region, each memory cell is the same. The overall structure of each memory cell is left-right mirror symmetric.

[0052] Each memory cell includes: a common source located in the substrate; a common line (COM) located on the substrate, directly above and connected to the common source; a pair of stacked gates located on the substrate, arranged in left-right mirror symmetry on both sides of the common line, where each stacked gate includes a control gate (CG) and a floating gate (FG) stacked vertically; two select gates (SG), respectively located on the side of the stacked gate opposite to the common line, aligned with the stacked gate, and arranged in left-right mirror symmetry along the common line. On the side of the two select gates that is not adjacent to the stacked gate, there is a drain in the substrate below each.

[0053] The control gate of the memory cell of the present invention has the same height as the logic gate of the logic transistor. This avoids the defects caused by the overly thin control gate of the memory cell in small-sized flash memories, can ensure the reliability of the memory cell, and the memory cell has good and stable performance. The control gate in the memory cell and the logic gate in the logic transistor are formed in such a way that in the same deposition step, a layer of gate material is deposited simultaneously at predetermined positions in the memory array region and the peripheral logic region, and then different photomasks are used to etch the gate material layers deposited on the array region and the peripheral logic region respectively.

[0054] In the present invention, it is preferred that the select gate of the memory cell has the same or substantially the same height as the stacked gate. This can make the structure of the memory cell simple, easy to fabricate, and have reliable and stable performance. More preferably, the select gate and the stacked gate have exactly the same height, and most preferably, the select gate and the stacked gate have the same structure and height. This is easy to control and achieve consistent and precise etching during the fabrication process, and avoid leakage caused by minor over-etching, which affects reliability. The select gate includes two parts, upper and lower.

[0055] In a preferred embodiment, in the stacked gate, there is a dielectric layer between the control gate and the floating gate; the upper and lower parts of the select gate have the same height as the control gate and the floating gate respectively, and there is also a dielectric layer between the upper and lower parts of the select gate, with the same height as the dielectric layer in the stacked gate; the lower part of the select gate is electrically connected to above the dielectric layer. In this case, the select gate and the stacked gate are formed together through the same manufacturing steps.

[0056] In the case where the heights of the select gate and the stacked gate in the storage cell are substantially the same, in the stacked gate, there is a dielectric layer between the control gate and the floating gate; the select gate is divided into upper and lower parts, which are formed through two different deposition steps respectively, but there is no dielectric layer between the upper and lower parts and they are directly connected as a whole. In this case, the select gate and the stacked gate are formed together through substantially the same manufacturing steps, with the difference that the manufacturing steps of the select gate do not include the deposition and formation process of the dielectric layer in the stacked gate.

[0057] The storage array according to the present invention includes rows and columns, and preferably, the arrangement directions of the storage cells in the array are the same.

[0058] Assuming that the connection direction of the same parts of the two select gates in the storage cell is the column direction, preferably: for each row, the upper parts of the select gates corresponding to the storage cells in each row and the control gates are connected to form a strip along that row; the floating gates corresponding to the storage cells in each row are not connected and are disconnected at the gap between two adjacent storage cells.

[0059] In the case where there is no dielectric layer in the select gate, more preferably: for each row, the upper parts of the select gates corresponding to the storage cells in each row are connected to form a strip along that row, while the lower parts of the select gates corresponding to the storage cells in each row are not connected and are disconnected at the gap between two adjacent storage cells, similar to the floating gate. However, in each storage cell, the lower part and the upper part in each select gate are connected as a whole.

[0060] In the case where there is a dielectric layer in the select gate, more preferably: for each row, the upper and lower parts of the select gates corresponding to the storage cells in each row are connected to form a strip along that row, and the strip of the lower part of the select gate can be electrically connected to above the dielectric layer. More preferably: in each row, in the dielectric layer between the upper and lower part strips of the select gates that are aligned vertically, there is at least one through hole, the bottom of which is electrically connected to the surface of the strip of the lower part of the select gate, and the top of which exposes the top surface of the dielectric layer, so that the strip of the lower part of the select gate can be electrically connected to above the dielectric layer; still more preferably: in each row, along that row, there is one through hole in the dielectric layer between the upper and lower part strips of the select gates that are aligned vertically every 8 - 64, more preferably every 16 - 32 storage cells; Or Assume that the connection direction of the same part of the two select gates in the memory cell is the row direction. Preferably, for each column, the upper parts of the select gates corresponding to each memory cell and the control gates are respectively connected along the column to form a strip; the floating gates corresponding to each memory cell in each column are not connected and are disconnected at the gap between two adjacent memory cells.

[0061] In the case where there is no dielectric layer in the select gate, more preferably, for each column, the upper parts of the select gates corresponding to each memory cell are connected along the column to form a strip, while the lower parts of the select gates corresponding to each memory cell in each column are not connected and are disconnected at the gap between two adjacent memory cells, similar to the floating gate. However, in each memory cell, the lower part and the upper part in each select gate are integrally connected.

[0062] In the case where there is a dielectric layer in the select gate, more preferably, for each column, the upper part and the lower part of the select gate corresponding to each memory cell are respectively connected along the column to form a strip; and the strip of the lower part of the select gate can be electrically conducted to above the dielectric layer. More preferably, in each column, in the dielectric layer between the upper and lower strips of the select gate aligned vertically, there is at least one through hole, the bottom of which is electrically connected to the surface of the strip of the lower part of the select gate, and the top exposes the top surface of the dielectric layer, so that the strip of the lower part of the select gate can be electrically conducted to above the dielectric layer; still more preferably, in each column, along the column, every 8 - 64, more preferably 16 - 32 memory cells, there is a through hole in the dielectric layer between the upper and lower strips of the select gate aligned vertically.

[0063] In the memory array of the present invention, in the case where there is a through hole in the dielectric layer between the upper and lower strips of the select gate, preferably, in the strip of the upper part of the select gate, at the position corresponding to each through hole in the lower dielectric layer, there is also a through hole, which is electrically insulated from the strip of the upper part of the surrounding select gate, the bottom is penetrated and internally electrically connected to the corresponding through hole in the lower dielectric layer, and the top exposes the top surface of the strip of the upper part of the select gate, so that the through hole in the dielectric layer extends to the top surface of the strip of the upper part of the select gate.

[0064] In the memory array of the present invention, the common source of the memory cell is connected to the common line (COM), the control gate is connected to the control line (CG'), and the drain of the select gate is connected to the bit line (BL); in the case where there is no dielectric layer in the select gate, the upper and lower parts of the select gate are integrated and connected to the word line (WL). In the case where there is a dielectric layer in the select gate, when there is no via hole in the upper strip of the select gate but there is a via hole in the dielectric layer, the lower strip of the select gate is electrically connected to the upper strip of the select gate through the via hole in the upper dielectric layer and is connected to the word line (WL); or when there are via holes in both the upper strip of the select gate and the dielectric layer, and the via holes penetrate up and down and are electrically connected inside the center, it is preferred that the lower strip of the select gate is connected to the word line (WL) through the inside of the upper strip and the via hole in the dielectric layer above it, and the upper strip of the select gate is not connected to the word line. In this case, it is preferred that there is a ring of electrically insulating isolation walls on the inner surface of the via hole in the upper strip of the select gate and the via hole in the dielectric layer below it, and there is a metal wire in the center of the inside of the via hole. The metal wire in the center of the inside of the via hole is electrically insulated from the upper strip of the select gate outside the via hole by the isolation wall on the inner surface of the via hole.

[0065] In the memory array of the present invention, when the connection direction of the same part of the two select gates in the memory cell is the column direction, the bit lines (BL) of the memory cells in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of the memory cells in each row are respectively connected.

[0066] In the case where the connection direction of the same part of the two select gates in the memory cell is the row direction, the bit lines (BL) of the memory cells in each row are connected, and the word lines (WL), common lines (COM), and control lines (CG') of the memory cells in each column are respectively connected.

[0067] The programming channel of the embedded flash memory of the present invention is from the channel region near the common source of the memory cell to the floating gate, and the erasure channel is from the floating gate to the channel region in the underlying substrate. These are conventional simple channels in the industry and do not require additional components to form new channels, such as an erase gate or a floating gate side bulge, etc. Therefore, the structure of the memory cell of the present invention is simple, and the programming and erasure operations are simple and easy to implement.

[0068] In the memory array of the present invention, all memory cells can be erased simultaneously, and programming is bit-selectable.

[0069] The present invention also relates to a method for manufacturing the above small-size embedded flash memory, which sequentially includes the following steps.

[0070] A. Provide a substrate and form a well for the memory cell: A substrate is provided, the surface of which includes active regions and isolation regions arranged in parallel and adjacent to each other. Memory cells and logic devices are subsequently formed in the active regions. A well of the memory array is formed at a position below a predetermined region of the memory array in the substrate, and all the memory cells in the memory array share one well.

[0071] B. Depositing a gate oxide and a lower gate material and performing etching: On the substrate, a layer of gate oxide (abbreviated as gate oxide layer) is first deposited, and then a layer of lower gate material is deposited on the gate oxide layer. This is the first deposited gate material layer, also referred to as the lower gate material layer or the lower gate layer. The growth height of the gate oxide layer is preferably 80 - 95 Å (angstroms). The growth height of the lower gate layer is preferably 750 - 1000 Å, and more preferably 800 - 900 Å. If the height of the lower gate layer is too low, it will affect the device performance. For example, the coupling efficiency of the memory cells will decrease. If it is too high, the flash memory manufacturing process cannot be used.

[0072] Then, using a photomask (also known as a lithography mask), in the gap between adjacent memory cells in the predetermined array region, and at the position between the corresponding floating gates of the predetermined adjacent memory cells, the deposited lower gate layer is etched away to form a partition between the floating gates of adjacent cells, and the deposited lower gate layer is etched away in the region of the predetermined logic region.

[0073] In the case where there is no dielectric layer in the select gate of the memory cell, in the gap between the predetermined adjacent memory cells, at the position between the lower parts of the corresponding select gates of the predetermined adjacent memory cells, the deposited lower gate layer is also etched away to form a partition between the lower parts of the select gates of adjacent cells; in the case where there is a dielectric layer in the select gate of the memory cell, no etching is performed at the position between the lower parts of the corresponding select gates of adjacent memory cells.

[0074] In the case where the connection direction of the same parts of the two select gates in the memory cell is the column direction, the etching between adjacent memory cells in the array region is as follows: along the row direction, in the region of each row of memory cells in the predetermined area, at the position between the corresponding floating gates of the predetermined adjacent memory cells, etching is performed. In the case where there is no dielectric layer in the select gate of the memory cell, at the same time, at the position between the lower parts of the corresponding select gates of the predetermined adjacent memory cells, etching is performed. Or In the case where the connection direction of the same parts of the two select gates in the memory cell is the row direction, the etching between adjacent memory cells in the array region is as follows: along the column direction, in the region of each column of memory cells in the predetermined area, at the position between the corresponding floating gates of the predetermined adjacent memory cells, etching is performed. In the case where there is no dielectric layer in the select gate of the memory cell, at the same time, at the position between the lower parts of the corresponding select gates of the predetermined adjacent memory cells, etching is performed.

[0075] C. Depositing a dielectric oxide and performing etching: A dielectric oxide material (hereinafter referred to as the dielectric layer) is simultaneously deposited on the lower gate layer in the entire array region and on the gate oxide layer in the logic region; in the case where there is no dielectric layer in the select gate of the memory cell, the dielectric oxide material is not deposited in the predetermined select gate region.

[0076] Then, using a photomask, the dielectric layer deposited in the logic region is etched away, and in the case where there is a dielectric layer in the select gate of the memory cell, a via hole is etched in the dielectric layer already deposited above the predetermined select gate region in the array region at the same time.

[0077] Etching a via hole in the dielectric layer deposited in the array region includes: In the case where the connection direction of the same parts of the two select gates in the memory cell is the column direction, in the predetermined memory cell region of each row, at least one via hole is etched in the dielectric layer above the predetermined region at the lower part of the select gate, preferably at a position every predetermined 8 - 64, more preferably 16 - 32 memory cells along this row, a via hole is etched in the dielectric layer above the predetermined region at the lower part of the select gate; the bottom of the via hole contacts the surface of the lower gate layer, and the top exposes the top surface of the dielectric layer; In the case where the connection direction of the same parts of the two select gates in the memory cell is the row direction, in the predetermined memory cell region of each column, at least one via hole is etched in the dielectric layer above the predetermined region at the lower part of the select gate, preferably at a position every predetermined 8 - 64, more preferably 16 - 32 memory cells along this column, a via hole is etched in the dielectric layer above the predetermined region at the lower part of the select gate. The bottom of the via hole contacts the surface of the lower gate layer, and the top exposes the top surface of the dielectric layer.

[0078] A smaller number of via holes is beneficial to reducing the area of the memory array. If the number of via holes is too small, the voltage will drop due to the too long WL current flow.

[0079] D. Forming the well of the logic device and the logic gate oxide layer in the logic region: In the predetermined logic region, the well of the logic device is formed. At this time, forming the well of the logic device can avoid going through the above preparation steps and being affected by them, so as to keep the performance of the logic device well stable, for example, keeping the ion distribution in the well unchanged.

[0080] The logic region includes a low-voltage and / or high-voltage logic region. The low-voltage region may contain multiple low-voltage standard logic devices (or logic transistors). According to their respective uses, the types of these low-voltage logic transistors and the types of their wells are also different, which will form multiple wells of different types in the low-voltage region. Therefore, it is necessary to form their respective wells according to the types of each logic transistor to be used. The high-voltage logic region is similar to the low-voltage logic region.

[0081] Next, remove the gate oxide layer formed together with the memory array remaining in the logic region, and regrow the gate oxide layer in the logic region. There is a certain gap between the regrown gate oxide layer in the logic region and the gate oxide layer in the memory array region, aiming to ensure insulation between the memory array region and the logic region. The gate oxide layer in the low-voltage logic region is thinner, and the gate oxide layer in the high-voltage logic region is thicker, depending on the applicable voltage for their intended uses.

[0082] E. Deposit the upper gate material and etch to form each gate: On top of the gate oxide layer in the entire array region and the logic region, deposit a layer of upper gate material at the same time, which is also called the upper gate material layer or the upper gate layer.

[0083] Next, in the memory array region, use a photomask to cover the regions of the predetermined select gates and control gates, and outside these regions, etch downward to the gate oxide layer at the same time to remove the upper and lower gate layers and the dielectric layer in the middle, thereby forming the upper part strips of the select gates, the lower part of the select gates (in the case where the select gate has no dielectric layer) or the lower part strips of the select gates (in the case where the select gate has a dielectric layer), the strips of the control gates, and the floating gates at the same time.

[0084] That is: when the connection direction of the same parts of the two select gates in the memory cell is the column direction, along the row direction, in the region of each row of memory cells predetermined, etch to form two upper part strips of the select gates, the lower part of the select gates (in the case where the select gate has no dielectric layer) or two lower part strips of the select gates (in the case where the select gate has a dielectric layer), two strips of the control gates, and the floating gate in each row; or When the connection direction of the same parts of the two select gates in the memory cell is the row direction, along the column direction, in the region of each column of memory cells predetermined, etch to form two upper part strips of the select gates, the lower part of the select gates (in the case where the select gate has no dielectric layer) or two lower part strips of the select gates (in the case where the select gate has a dielectric layer), two strips of the control gates, and the floating gate in each column.

[0085] Then, in the logic region, the regions of the predetermined logic gates are shielded by a photomask, and outside these regions, the upper gate material layer is etched away to form the logic gates. Meanwhile, when there is a dielectric layer in the select gate of the memory cell, it is preferred that: in the upper partial strips of the select gate formed in the memory array region, at the positions corresponding to the vias in the underlying dielectric layer, etching is performed to form vias in the upper partial strips of the select gate, the bottom of which communicates with the via in the underlying dielectric layer and the two are electrically connected internally, and the top exposes the surface of the upper partial strips of the select gate.

[0086] F. Forming source and drain Next, on the two side surfaces of each gate formed by etching, an isolation wall is formed with an isolation dielectric material to play an electrical insulation role. Meanwhile, when there is a via in the upper partial strips of the select gate, an isolation wall is also formed on the inner surfaces of the via and the via in the underlying dielectric layer that communicates with it. When there is no via in the upper partial strips of the select gate, no isolation wall is formed on the inner surface of the via in the dielectric layer.

[0087] Then, ions are implanted into the active regions on the substrate surface outside the isolation walls of each gate to form the source and drain on both sides of the select gate and the stacked gate in the memory cell, and the source and drain of the logic transistor. In the memory cell, the ion implantation region formed in the underlying substrate between the two stacked gates is the common source; the ion implantation region formed in the underlying substrate outside the select gate (the side not adjacent to the stacked gate) is the drain of the select gate.

[0088] Subsequently, the gate oxide layer remaining on the surface of the active region above each source and drain is removed with an acid. Above the common source of the memory cell and between the two stacked gates, a self-aligned silicide is formed to constitute a common line (COM) that connects the common source in the underlying substrate, and the drain below the outside (the side not adjacent to the stacked gate) of the select gate of the memory cell is connected to the bit line (BL). When there is no dielectric layer in the select gate of the memory cell, the upper and lower parts of the select gate are integrated and connected to the word line (WL).

[0089] In the case where there is a dielectric layer in the select gate, when there are no vias in the upper partial strip of the select gate, the lower partial strip of the select gate is electrically connected to the upper partial strip of the select gate through the vias in the dielectric layer above it and is connected to the word line (WL). When there are vias in the upper partial strip of the select gate, the bottom of the via communicates with the via in the lower dielectric layer, and there is an isolation wall on the inner surfaces of both. At the inner center of the via, tungsten metal is etched and filled through a mask to form a wire. The bottom of the wire is electrically connected to the lower partial strip of the select gate, and the top exposes the top surface of the upper partial strip of the select gate, connecting to the word line (WL), so that the lower partial strip of the select gate is connected to the word line (WL), while the upper partial strip of the select gate is not connected to the word line (WL). When etching inside the via, a mask is used and the isolation wall on the inner surface of the via is not etched away.

[0090] The materials of each part in the memory cell and the logic transistor are all conventional materials in this industry. The material of the common line is preferably self-aligned silicide, and the material of the gate is preferably polysilicon. The materials of the dielectric layer and the isolation wall are conventional materials well-known in this industry.

[0091] Next, the embedded flash memory below 110 nm of the present invention will be described in detail with reference to the accompanying drawings, but the scope of the present invention is not limited to the specific embodiments shown in the drawings.

[0092] Figure 1 It is a partial top view of a specific embodiment of a 90 nm embedded flash memory of the present invention. Only a partial memory array composed of 8 memory cells in the flash memory and the peripheral local low-voltage and high-voltage logic regions are shown in the figure. Among them, 4 independent low-voltage standard logic transistors are shown in the low-voltage logic region; 4 high-voltage standard logic transistors are shown in the high-voltage logic region, where two of them are in series. The memory array in this flash memory and the peripheral low-voltage and high-voltage logic regions share a substrate.

[0093] Figure 1 All the memory cells in the shown flash memory are the same. The devices in the memory cell are of PMOS type. All the memory cells share an N-well ( Figure 1 (not shown) and are built in the substrate. Figure 1 The 4 low-voltage logic transistors in the shown low-voltage logic region are the same and are all of NMOS type, sharing a P-well; the 4 high-voltage logic transistors in the high-voltage logic region are the same and are all of PMOS type, sharing an N-well. The P-well and N-well of the logic devices in the logic region are also built in the above-mentioned substrate ( Figure 1 (not shown). The gate heights of all the logic devices (or logic transistors) in the logic region (including the low-voltage and high-voltage logic regions) are the same. They are formed by simultaneously depositing and then etching with the same gate material in the same deposition step.

[0094] Figure 1Among them, the memory cells and the peripheral logic transistors are both built within the active regions (AAs) on the substrate surface. On the substrate surface, the active regions and the shallow trench isolation regions (STIs) are arranged alternately in parallel and adjacent to each other.

[0095] Figure 1 In the shown memory array, all the memory cells are arranged and oriented in the same way. Among them, the connecting direction of the same parts of the two select gates in the memory cell is the column direction, and the odd and even columns are separated by the shallow trench isolation regions (STIs). In the illustrated array, there are 4 memory cells in each row and 2 memory cells in each column.

[0096] The structure of the shown memory cell is as Figure 12b shown. Figure 12b It is Figure 1 the structure of a memory cell along the C-C section line in the shown flash memory. It includes: a P common source in the substrate; a common line (COM) located directly above the common source and connected to the common source at the bottom; a pair of stacked gates located on the substrate, arranged symmetrically left and right on both sides of the common line, and each stacked gate includes a control gate (CG) and a floating gate (FG) stacked vertically, and the dielectric layer (DL) in the middle; a pair of select gates (SG), separated on the side of the stacked gate opposite to the common line, aligned with the stacked gate, and arranged symmetrically left and right along the common line. On the side of the two select gates not adjacent to the stacked gate, there is a drain in the underlying substrate respectively. Each select gate includes an upper and a lower part, and the dielectric layer (DL) in the middle. The common source of the memory cell is connected to the common line (COM), the control gate is connected to the control line (CG’) ( Figure 12b not shown in

[0097] the drain of the select gate is connected to the bit line (BL); the lower part of the select gate is connected to the word line (WL).

[0098] The height of the control gate in the memory cell is the same as the height of the logic gate in the logic transistor. They are formed by simultaneously depositing the same gate material in the same deposition step and then etching them separately.

[0099] The materials of each part in the memory cell and the logic transistor are all conventional materials in this industry. For example, the material of the common line is self-aligned polysilicide, and the material of the gate is polysilicon.

[0100] In the shown memory array, the upper part, lower part, and control gate of the select gate corresponding to all memory cells in each row span the isolation region (STI) between adjacent columns along this row and are respectively connected into a strip, and these strips are parallel to each other. However, the floating gates corresponding to each memory cell in each row are not connected. There is a partition (PC) formed by etching between the floating gates of two adjacent cells in each row, and they are disconnected by the PC, as Figure 1 shown.

[0101] There are vias in the dielectric layer between the upper and lower part strips of the select gate aligned vertically in each row. Along this row, there is one via in the dielectric layer between the upper and lower part strips of the select gate every 16 memory cells, and the bottom is electrically connected to the lower part strip of the select gate. In the upper part strip of the select gate in this row, there is also a via at the position corresponding to the via in the lower dielectric layer. The top exposes the surface of the upper part strip of the select gate, and the bottom communicates with the via in the lower dielectric layer. There is an isolation wall on the inner surface of the above two vias, and there is a metal wire in the center inside. The wire is electrically connected to the surface of the lower part strip of the select gate below, and is connected to the word line (WL) above. Thus, the lower part strip of the select gate in each row can be connected to the upper word line (WL), but the upper part of the select gate is not connected to the word line (WL).

[0102] The bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG’) of each memory cell in each row are respectively connected. As Figure 13 shown.

[0103] Figures 2-10 (Except Figure 5b-5c and Figure 7b ) are respectively Figure 1 Schematic diagrams of the structures of a part of the memory cells and logic devices in the shown flash memory along the B-B section line during the manufacturing process (steps before etching to form the gate). Figures 11a-12b Respectively show the formation steps of the gates of the memory cells and logic devices, as well as the formation steps of the source and drain. Below, in combination with these drawings, the manufacturing process of Figure 1 the shown flash memory will be described in detail.

[0104] A. Provide a substrate and form the well of the memory cell: Figure 2 is Figure 1Schematic diagram of the substrate in the flash memory shown along the B-B cross-section line before device formation. Active regions (AA) and shallow trench isolation regions (STI) are arranged alternately adjacent to each other on the substrate surface. Memory cells and logic devices are subsequently formed in the active regions. As Figure 3 shown, first, an N-well of the memory array is formed at a position below a predetermined region of the memory array in the substrate.

[0105] B. Depositing gate oxide and lower gate material and performing etching: As Figure 4 shown, on the substrate surface, a layer of gate oxide material is simultaneously deposited in the predetermined memory array region and logic region. Then, a layer of lower gate material is further deposited on the entire gate oxide layer. The thickness of the gate oxide layer is about 85 Å, and the thickness of the floating gate is about 800 Å.

[0106] Then, using a photomask, in the predetermined region of each row of memory cells, at the gap between two adjacent predetermined memory cells, the predetermined part of the partition PC between the corresponding floating gates of two adjacent memory cells is etched to remove the deposited lower gate layer, forming the partition PC between the floating gates of adjacent cells; and the deposited lower gate layer is etched away in the predetermined logic region (including low-voltage and high-voltage logic regions).

[0107] Figure 5a And 5d are respectively Figure 1 schematic diagrams of a part of the memory device and logic device in the flash memory shown along the B-B cross-section line before and after etching to form the partition PC between the floating gates in each row. Figure 5a shows the structure of the photomask placed on the deposited lower gate layer along the B-B cross-section line before etching, where the predetermined PC region to be etched is exposed.

[0108] Figure 5b-5c are respectively Figure 1 top views of a row of memory cells in the flash memory shown during the step of etching to form the partition between the floating gates of adjacent cells, and only the predetermined regions of 4 memory cells in this row are shown in the figure. Figure 5b shows that before etching, a photomask (also called a lithography mask) is placed on the deposited lower gate layer in the memory array region. The photomask covers most of the lower gate layer, and only the predetermined PC region to be etched away is exposed. Then etching is performed to remove the exposed lower gate material, forming the partition PC between the floating gates of adjacent cells in this row, as Figure 5c shown. The partition PC formed by such etching includes the partitions between the two floating gates of each memory cell in this row and the corresponding floating gates of adjacent cells.

[0109] C. Depositing dielectric oxide and performing etching: AsFigure 6 As shown, a layer of dielectric oxide material, i.e., the dielectric layer, is simultaneously deposited on the lower gate layer of the storage array and the gate oxide layer of the logic region.

[0110] Then, as Figure 7a shown, the dielectric layer deposited in the logic region is removed by photomask etching. Meanwhile, in the array region, in the region of each row of storage cells as predetermined, at positions every 16 storage cells as predetermined along the row, a via hole is etched and formed in the dielectric layer above the lower part of the predetermined select gate. The bottom of the via hole contacts the surface of the lower gate layer, and the top exposes the top surface of the dielectric layer. Figure 7a The via hole is not shown in Figure 7b and is shown in Figure 7b is Figure 1 a top view of a row of storage cells in the flash memory shown after the via holes are etched and formed in the dielectric layer. Only the predetermined regions of 4 storage cells in the row are shown in the figure, and a via hole is formed in each of the two predetermined lower parts of the select gates in the row.

[0111] D. Form the wells of the logic devices in the logic region and the logic gate oxide layer: As Figure 8a shown, in the predetermined logic region, the wells of the logic devices are formed. The low-voltage (LV) standard logic devices in the low-voltage logic region are NMOS transistors, and their wells are P-wells. The high-voltage (HV) standard logic devices in the high-voltage logic region are PMOS transistors, and their wells are N-wells.

[0112] Then, as Figure 8b shown, the gate oxide layer that was previously formed together with the storage array and remains in the logic region is removed; and the gate oxide layer in the logic region is regrown, as Figure 9 shown. There is a certain gap between the regrown gate oxide layer in the logic region and the gate oxide layer in the storage array region. The gate oxide layer thicknesses in the low-voltage and high-voltage logic regions are different. The gate oxide layer in the low-voltage logic region is thinner, about 25 Å, and the gate oxide layer in the high-voltage logic region is thicker, about 65 Å. In this way, the voltage of the low-voltage logic devices is about 1.1 V, and the voltage of the high-voltage logic devices is about 2.5 V. Additionally, a thicker gate oxide layer, about 120 Å, can also be formed in the high-voltage logic region to obtain high-voltage logic devices with 5 V.

[0113] E. Deposit the upper gate material and etch to form each gate: As Figure 10 shown, a layer of upper gate material is simultaneously deposited on the dielectric layer in the storage array region and on the gate oxide layer in the logic region.

[0114] Then, in the storage array region, in the region of each row of memory cells, a photomask is used to shield the predetermined portions of the select gate and the control gate, and in the regions other than these portions, etching is performed downward simultaneously to the gate oxide layer to remove the upper and lower gate layers and the dielectric layer therebetween at these portions, thereby simultaneously forming strips of the upper part of the select gate, strips of the lower part of the select gate, strips of the control gate, and floating gates in each row. In each row, there are two strips of the upper and lower parts of the select gate and two strips of the control gate, which are arranged in parallel along the row direction, as shown in Figure 1 the storage array in

[0115] Figure 11a-11b Respectively, they are Figure 1 the structure of a memory cell in the flash memory shown in Figure 11a along the C-C cross-sectional line in the column direction, and schematic diagrams of the steps before and after etching to form the gate. Figure 11b It shows the portions shielded by the photomask in the memory cell, that is, the portions where the select gate and the control gate are to be formed.

[0116] In the etched select gate upper part strips, at the positions corresponding to the vias in the underlying dielectric layer, etching is performed to form vias in the select gate upper part strips. Its bottom is in communication with the vias in the underlying dielectric layer, extending the vias in the underlying dielectric layer and exposing the surface of the select gate upper part strips. Figure 11c-11d Respectively, they show Figure 1 the structure of the low-voltage logic device in the flash memory shown in Figure 11e-11f along the D-D cross-sectional line, and the steps before and after etching to form the low-voltage logic gate. Figure 1 Respectively, they show Figure 11c and Figure 11e the structure of the high-voltage logic device in the flash memory shown in

[0117] along the E-E cross-sectional line, and the steps before and after etching to form the high-voltage logic gate.

[0118] F. Forming source and drain: On the two side surfaces of each gate formed by etching, an isolation wall is formed with an isolation dielectric material to play an insulating role. At the same time, an isolation wall is also formed on the inner surface of the vias formed in the select gate upper part strips and the dielectric layer.

[0119] Then, in the active region on the substrate surface outside the isolation walls of each gate, ions are implanted into the substrate to form P-type source / drain regions on both sides of the select gate and the stacked gate in the memory cell (as Figure 12a shown), and the source / drain regions of the logic transistors.

[0120] In the memory cell, the ion implantation region formed in the underlying substrate between the two stacked gates serves as the common source; the ion implantation region formed in the underlying substrate outside the select gate (the side not adjacent to the stacked gate) serves as the drain of the select gate.

[0121] Subsequently, the gate oxide layer remaining above each ion implantation region is removed with acid. A self-aligned silicide is formed above the common source of the memory cell and in the middle of the two stacked gates to form a common line (COM), connecting the common source in the underlying substrate; the drain below the outside (the side not adjacent to the stacked gate) of the select gate of the memory cell is connected to the bit line (BL).

[0122] In the inner center of the through holes in the upper partial strip and the dielectric layer of the above-mentioned select gate, tungsten metal is etched and filled to form a wire. The bottom of this wire is electrically connected to the lower partial strip of the select gate, and the top is connected to the word line (WL), enabling the lower part of the select gate to be connected to the word line (WL), while the upper partial strip of the select gate is not connected to the word line (WL). When etching inside the through holes, a photomask is used to not etch away the isolation walls on the inner surface of the through holes.

[0123] The use and operation process of the above 90nm embedded flash memory are as follows.

[0124] Figure 13 is Figure 1 a circuit schematic diagram of a 2×2 memory array of the flash memory shown. During the operation process, half of a memory cell is used as a unit to participate in programming, reading, and erasing. In Figure 13 the circuit diagram of the memory array shown, the upper row includes 2 memory cells, where one memory cell includes a first half-cell part 100 and a second half-cell part 110, and the other memory cell includes a third half-cell part 120 and a fourth half-cell part 130. Taking these 4 half-cell parts as examples below, namely: the first half-cell part 100, the second half-cell part 110, the third half-cell part 120, and the fourth half-cell part 130, the operation process is described. The structure of each memory cell is as Figure 12b shown.

[0125] Figure 14 is the bias signal connected by the 4 half-cell parts (i.e., the first half-cell part 100, the second half-cell part 110, the third half-cell part 120, and the fourth half-cell part 130) in the above 2 memory cells during different operations.

[0126] The first half-cell portion 100 is selected for individual programming. During programming, electrons are injected into the floating gate from the channel region in the substrate near the common source. The first half-cell portion 100 is programmed by driving its BL to 4.5V, WL to 0V, CG to 2.5 - 4.5V, COM to 0V, and N-well to 3.5V.

[0127] In the first half-cell portion 100, the potential of the word line WL is lower than that of the bit line BL and the N-well, and the potential obtained by the floating gate FG coupling from the control gate CG is also lower than that of the N-well. Thus, an inversion channel is formed between the bit line diffusion region and the common source region in the substrate. The voltage difference between the bit line diffusion region and the source region is 4.5V, forming a strong lateral electric field from the bit line diffusion region to the common source region. Therefore, holes are accelerated from one side of the channel to the other, resulting in impact ionization at the depletion region of the common source. The hot electrons generated by impact ionization are attracted by the forward-biased floating gate and injected into the floating gate. Therefore, the number of electrons in the floating gate increases during programming.

[0128] The potential of the word line WL of the second half-cell portion 110 is 7V, higher than that of the bit line BL and the N-well, and the channel is turned off. Although there is a potential difference between the bit line diffusion region and the source region, hole movement and impact ionization cannot occur. Therefore, it cannot be programmed.

[0129] The potentials of the bit line diffusion regions and the source regions of the third half-cell portion 120 and the fourth half-cell portion 130 are both 0, and no potential difference and lateral electric field are formed. Programming does not occur.

[0130] In the erase operation, under the action of a high voltage between the floating gate and the substrate below it, electrons tunnel from the floating gate of the selected unit half to the channel region in the substrate below it in the selected portion of the memory cell.

[0131] The erase bias signals of the first half-cell portion 100 and the third half-cell portion 120 are the same. Its bit line BL is floating, and the potential of the word line WL is the same as that of the N-well. The potential of the control gate CG is much lower than that of the common source region and the N-well connected to the common line, and the potential obtained by the floating gate FG coupling from the control gate CG is also much lower than that of the source region and the N-well. Since the voltage between the floating gate and the N-well is greater than 10V, a high electric field is formed, sufficient to cause the electrons trapped in the floating gate to tunnel to the channel. The tunneling mechanism is direct tunneling and / or Fowler - Nordheim tunneling.

[0132] The erase bias signals of the second half-cell portion 110 and the fourth half-cell portion 130 are the same. The potential of its control gate CG is 0, and the potential obtained by the floating gate FG coupling is also 0. Since the voltage difference between the floating gate and the N-well is small, the electrons in the floating gate cannot be induced to tunnel to the channel in the substrate.

[0133] In addition, the erasure bias signals of the above four half-cell parts can be set to be the same, so that the four half-cell parts are erased simultaneously.

[0134] In a read operation, data in a column of memory cells can be read out simultaneously. The bit lines BL of the first half-cell part 100, the second half-cell part 110, the third half-cell part 120, and the fourth half-cell part 130 are selected, and the half part of the memory cell to be read is selected according to whether the word line WL is turned on or off.

[0135] The potential of the word line WL of the first half-cell part 100 and the second half-cell part 110 is lower than that of the bit line BL and the N-well. The potential coupled from the control gate CG to the floating gate FG is 0, which is also lower than the bit line and the N-well. Thus, an inversion channel is formed between the bit line diffusion region in the substrate and the common source region. Moreover, there is a potential difference of 2v between the bit line diffusion region and the common source region, forming a lateral electric field. Therefore, a read current is generated.

[0136] The potentials of the bit line diffusion regions and the common source regions of the third half-cell part 120 and the fourth half-cell part 130 are both 0, and no lateral electric field is formed. Therefore, no read current is generated.

[0137] Although the present invention has been described in detail only for the current preferred embodiments, as is known to those of ordinary skill in the art, other changes and modifications can be made without departing from the scope of the present invention defined by the claims.

Claims

1. An embedded flash memory with a size of less than 110 nm, comprising: A substrate, and a storage array area and a peripheral logic area on the substrate, wherein the storage array area includes at least one storage unit, and the storage unit includes: a common source located in the substrate, a common line located above the common source and connected to the common source; a pair of stacked gates, respectively located on both sides of the common line, each stacked gate includes a floating gate and a control gate vertically stacked thereon; a pair of selection gates, respectively located next to the non-common line side of the two stacked gates; the peripheral logic area includes at least one logic transistor, and the logic transistor includes a logic gate; it is characterized in that: the control gate in the storage unit is at the same height as the logic gate of the logic transistor.

2. The embedded flash memory of less than 110 nm as claimed in claim 1, characterized in that: The selection gate has the same or substantially the same height as the stacked gate, the selection gate includes an upper and a lower part, and a dielectric layer is provided between the control gate and the floating gate in the stacked gate; The heights of the selection gate and the stacked gate are substantially the same, which means that there is no dielectric layer between the upper and lower parts of the selection gate, resulting in its height being slightly lower than that of the stacked gate; the height difference is the height of the dielectric layer in the stacked gate.

3. The embedded flash memory of less than 110 nm as claimed in claim 2, characterized in that: The structure and height of the selection gate and the stacked gate are the same; the heights of the upper and lower parts of the selection gate are the same as those of the control gate and the floating gate, respectively, and there is also a dielectric layer between the upper and lower parts of the selection gate, the height of which is the same as that of the stacked gate; the lower part of the selection gate is electrically connected to the top of the dielectric layer.

4. The embedded flash memory of less than 110 nm as claimed in claim 2, characterized in that: The storage array comprises rows and columns, and the arrangement direction of each storage unit in the array is the same; The connection direction of the same parts of the two selection gates in the memory cells is the column direction, and the corresponding upper parts of the selection gates and the control gates of the memory cells in each row are connected along the row to form a strip; the corresponding floating gates of the memory cells in each row are not connected and are disconnected at the gap between two adjacent memory cells; or The connection direction of the same parts of the two selection gates in the memory cell is the row direction, and the corresponding upper parts of the selection gates and the control gates of the memory cells in each column are connected along the column to form a strip; the corresponding floating gates of the memory cells in each column are not connected and are disconnected at the gap between two adjacent memory cells; The corresponding gates of each storage unit in each row or column refer to the gates with the same orientation in each storage unit in the row or column. These gates can be connected into a straight line along the row or column. The gates can be a selection gate, an upper part of a selection gate, a lower part of a selection gate, a control gate, or a floating gate.

5. The embedded flash memory of less than 110 nm as claimed in claim 4, characterized in that: In the memory cell, the structure and height of the selection gate and the stacked gate are the same; the heights of the upper and lower parts of the selection gate are the same as those of the control gate and the floating gate, respectively, and there is also a dielectric layer between the upper and lower parts of the selection gate, the height of which is the same as that of the stacked gate; In the memory array, the connection direction of the same parts of the two selection gates in the memory cells is the column direction, and the upper and lower parts of the selection gates corresponding to the memory cells in each row and the dielectric layer therebetween are connected along the row to form a strip; in each row, there is at least one through hole in the dielectric layer between the upper and lower strips of the selection gates aligned up and down, the bottom of which is electrically connected to the surface of the lower strip of the selection gate and the top of which is exposed to the top surface of the dielectric layer, so that the lower strip of the selection gate is electrically connected to the top of the dielectric layer; or In the memory array, the connection direction of the same parts of the two selection gates in the memory cell is the row direction, and the upper and lower parts of the selection gates corresponding to the memory cells in each column, and the dielectric layer in between, are connected along the column to form a strip; in each column, there is at least one through hole in the dielectric layer between the upper and lower strips of the selection gates aligned up and down, the bottom of which is electrically connected to the surface of the lower strip of the selection gate, and the top of which exposes the top surface of the dielectric layer, so that the lower strip of the selection gate is electrically connected to the top of the dielectric layer.

6. The embedded flash memory of less than 110 nm as claimed in claim 5, characterized in that: In the memory array, the connection direction of the same parts of the two selection gates in the memory cell is the column direction, and in each row, there is also a through hole at the position of the upper partial strip of the selection gate corresponding to the through hole in the lower dielectric layer, the through hole is electrically insulated from the upper partial strip of the selection gate surrounding it, the bottom is connected with the through hole in the lower dielectric layer and is electrically connected internally, and the top exposes the top surface of the upper partial strip of the selection gate; or In the memory array, the connection direction of the same parts of the two selection gates in the memory cell is the row direction. In each column, there is also a through hole at the position of the through hole in the lower dielectric layer in the upper partial strip of the selection gate. The through hole is electrically insulated from the upper partial strip of the selection gate surrounding it, and the bottom is connected with the through hole in the lower dielectric layer and is electrically connected internally, and the top surface of the upper partial strip of the selection gate is exposed at the top.

7. The embedded flash memory of less than 110 nm as claimed in claim 5, characterized in that: In the memory array, the connection direction of the same parts of the two selection gates in the memory cells is the column direction, and in each row, there is a through hole in the dielectric layer between the upper and lower partial strips of the selection gates aligned up and down every 16-32 memory cells along the row; or In the memory array, the connection direction of the same parts of the two selection gates in the memory cell is the row direction. In each column, there is a through hole in the dielectric layer between the upper and lower partial strips of the aligned selection gates every 16-32 memory cells along the column.

8. The embedded flash memory of less than 110 nm as claimed in any one of claims 1 to 7, characterized in that: It is an embedded flash device at 90nm and below.

9. A method for preparing an embedded flash memory having a size of less than 110 nm, wherein the embedded flash memory is an embedded flash memory having a size of less than 110 nm as claimed in any one of claims 1 to 8; characterized in that: It includes the following steps: The control gate in the storage unit and the logic gate in the logic transistor are formed in such a way that in the same deposition step, a layer of gate material is deposited simultaneously at predetermined positions in the storage array area and the peripheral logic area, and then different masks are used to etch the gate materials deposited on the storage array area and the peripheral logic area respectively.

10. The method for preparing an embedded flash memory below 110 nm as claimed in claim 9, characterized in that: The method further comprises the steps of: Before forming the control gate and the logic gate, on the surface of the substrate in the peripheral logic region, there is a deposited material formed when preparing the memory cells in the memory array, and the deposited material is removed by etching.

11. The method for preparing an embedded flash memory having a thickness of less than 110 nm as claimed in claim 9 or 10, characterized in that: The selection gate comprises an upper and a lower part, and a dielectric layer is provided between the control gate and the floating gate of the stacked gate; the method further comprises the following steps: In the case where the selection gate and the stacked gate have the same height, there is a dielectric layer between the upper and lower parts of the selection gate, and the selection gate and the stacked gate are formed together through the same preparation steps; or In the case where there is no dielectric layer between the upper and lower parts of the selection gate, the height of the selection gate and the stacked gate are basically the same, that is, the height of the selection gate is slightly lower than that of the stacked gate, and the height difference is the height of the dielectric layer in the stacked gate; at this time, the selection gate and the stacked gate are formed together through basically the same preparation steps, and the basically the same preparation steps mean that the preparation steps of the selection gate are smaller than the preparation steps of the stacked gate, and only the deposition process of the dielectric layer in the stacked gate is missing.

12. The method for preparing an embedded flash memory below 110 nm as claimed in claim 11, characterized in that: The structure and height of the selection gate and the stacked gate in the memory cell are the same, the heights of the upper and lower parts of the selection gate are the same as those of the control gate and the floating gate, respectively, there is a dielectric layer between the upper and lower parts of the selection gate, the height of which is the same as that of the stacked gate, and the lower part of the selection gate is electrically connected to the upper part of the dielectric layer; The storage array comprises rows and columns, and the arrangement direction of each storage unit in the array is the same; The method comprises the following steps in sequence: (1) On the substrate, a layer of gate oxide material and a layer of lower gate material are deposited in sequence; then, using a photomask, the deposited lower gate material layer is etched away at the gaps between adjacent memory cells in a predetermined memory array area and at the locations between the floating gates corresponding to the predetermined adjacent memory cells, and the deposited lower gate material layer is etched away at the predetermined peripheral logic area; and the locations between the lower portions of the select gates corresponding to the predetermined adjacent memory cells are not etched; In the case where the connection direction of the same part of the two selection gates in the memory cell is the column direction, the etching and removing of the deposited lower gate material layer at the gap between the adjacent memory cells in the predetermined memory array area and at the part between the floating gates corresponding to the predetermined adjacent memory cells is: etching along the row direction, in the area of ​​each predetermined row of memory cells, at the part between the floating gates corresponding to the predetermined adjacent memory cells; or In the case where the connection direction of the same part of the two selection gates in the memory cell is the row direction, the etching and removing of the deposited lower gate material layer at the gap between the adjacent memory cells in the predetermined memory array area and at the part between the floating gates corresponding to the predetermined adjacent memory cells is: etching is performed along the column direction, in the area of ​​each predetermined column of memory cells, at the part between the floating gates corresponding to the predetermined adjacent memory cells; (2) depositing a dielectric layer on the lower gate layer in the memory array region and on the gate oxide layer in the peripheral logic region at the same time; then using a photomask, etching to form a through hole in the dielectric layer deposited in the memory array region, and etching away the dielectric layer deposited in the peripheral logic region; The step of etching a through hole in a dielectric layer deposited in a storage array region comprises: In the case where the connection direction of the same part of the two selection gates in the memory cell is in the column direction, in the predetermined memory cell area of ​​each row, at least one through hole is etched in the dielectric layer above the area of ​​the predetermined lower part of the selection gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer; In the case where the connection direction of the same parts of the two selection gates in the memory cell is in the row direction, in the predetermined memory cell region of each column, at least one through hole is etched in the dielectric layer above the region of the predetermined lower part of the selection gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer; (3) depositing a layer of upper gate material on the dielectric layer in the memory array area and on the gate oxide layer in the peripheral logic area; then, using a photomask in the memory array area, etching downward to the gate oxide layer in areas other than the predetermined selection gate and control gate, removing the upper and lower gate material layers and the dielectric layer therebetween in these areas, and simultaneously forming a stripe on the upper part of the selection gate, a stripe on the lower part of the selection gate, a stripe on the control gate, and a floating gate; then, using a photomask in the peripheral logic area, etching away the upper gate material layer in areas other than the predetermined logic gate to form a logic gate.

13. The method for preparing an embedded flash memory below 110 nm as claimed in claim 12, characterized in that: The step of etching a through hole in a dielectric layer deposited in a storage array region comprises: In the case where the connection direction of the same parts of the two selection gates in the memory cell is in the column direction, in each predetermined row of memory cell regions, at every predetermined position of 16-32 memory cells along the row, at least one through hole is etched in the dielectric layer above the region of the predetermined lower part of the selection gate; When the connection direction of the same parts of the two selection gates in the memory cell is in the row direction, in each predetermined column of memory cell areas, at least one through hole is etched in the dielectric layer above the area of ​​the predetermined lower part of the selection gate at every predetermined position of 16-32 memory cells along the column.

14. The method for preparing an embedded flash memory below 110 nm as claimed in claim 12, characterized in that: The operation of etching in the memory array region to form a select gate upper portion strip, a select gate lower portion strip, a control gate strip, and a floating gate is specifically: In the case where the connection direction of the same part of the two selection gates in the memory cell is the column direction, two selection gate upper partial strips, two selection gate lower partial strips, two control gate strips, and a floating gate are formed in each row in the predetermined area of ​​each row of memory cells along the row direction; or When the connection direction of the same part of the two selection gates in the memory cell is the row direction, along the column direction, in the predetermined area of ​​each column of memory cells, two upper partial strips of the selection gate, two lower partial strips of the selection gate, two control gate strips, and a floating gate are etched to form in each column.

15. The method for preparing an embedded flash memory with a thickness of less than 110 nm according to any one of claims 12 to 14, characterized in that: It also includes the following steps: Prior to step (1), forming a well of a memory cell in a memory array in the substrate; and Between step (2) and step (3), a well of a logic transistor in the peripheral logic region is formed, and then the gate oxide layer deposited in step (1) is removed from the substrate surface of the peripheral logic region, and then the gate oxide layer of the logic region is regrown.

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