Photonic glass layer substrate with embedded optical structure for communicating with optoelectronic integrated circuits

Abstract

Embodiments described herein relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnects between electrical, optoelectronic and photonic devices. One or more optical silicon photonic devices described herein may be used on a single package substrate in conjunction with one or more optoelectronic integrated circuits (optoelectronic chips) to form co-packaged optical and electrical devices. The methods described herein enable mass production of electrical, optoelectronic, and optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to silicon electronic and photonic integrated circuits and co-packaged optical and electrical devices. More specifically, the present disclosure relates to an apparatus for co-packaging optical silicon photonics and electrical devices, and a method of fabricating an optical structure for an optical silicon photonics device. Background Art

[0002] As the network requirements for data traffic continue to increase, network companies that previously used conventional copper cables for communication have found more efficient solutions that can be deployed on a large scale. Today, fiber optic technology dominates the long-distance communication space. Network companies have gradually transitioned to using fiber optics to transmit data over increasingly shorter distances, even within device clusters and from device to device or device to chip. By using fiber optics, data is transmitted as photons at the speed of light and can be transmitted at a range of data rates, including at ultra-high frequencies, thereby allowing for higher data volume transmission.

[0003] As the network requirements for data traffic increase, there are also increasing requirements for data rates in electronic systems and communication. When the semiconductor industry balances the growing operating speed of integrated circuits and the challenge of chip solutions that can address the increasing network requirements for data traffic, one area for improvement that can help the semiconductor industry is to increase the interconnect speed with higher physical density and lower power usage and dissipation. The typical electrical interconnect solution between transistors on a conventional integrated circuit is still for electrons to travel through metal. The problems with using metal for communication and data transmission are generally density, timing, and resistive heating attributed to electron transfer. Such sources of performance degradation and loss have motivated a reduction in the use and length of metal interconnects and wires in communication and data transmission input / output (I / O) technologies. One way to minimize the use of metal interconnects is to co-package multiple chips and modules with optical components in a single or nearby packaging substrate that includes multiple integrated circuit and optical circuit devices tightly assembled together. Such multi-chip modules have been studied, but a large portion of the high-performance interconnects rely on metal interconnects to transfer data back and forth between chips, packages, substrates, and printed circuit boards.

[0004] Another way to minimize metal wiring and other metallization schemes for electronic transport in high-speed device communication systems is integration with optical device and communication system technologies, which has proven to be more advantageous for communication and data transfer than metal, due to higher density and data rates combined with lower length dependence and power usage and dissipation. Additionally, there is a trend to integrate optical components on a silicon (Si) substrate for fabricating large-scale photonic integrated circuits and packaging those photonic integrated circuits so that they can coexist with microelectronic chips. Due to the inherent material properties of silicon, optical communication technologies typically involve different materials and manufacturing processes compared to conventional silicon chip-based electronic communication technologies. However, silicon photonics technology has combined optical communication technology with electronics technology based on a shared material platform. As an example, in an optical transceiver for data center interconnect (DCI) applications, the received optical signal can be converted into an electrical signal capable of being processed by an integrated circuit, or the processed electrical signal can be converted into an optical signal to be transmitted via an optical fiber using a photonic integrated circuit.

[0005] Accordingly, there is a need in the art for improved co-packaged optical photon and electrical device technologies and manufacturing methods. SUMMARY OF THE INVENTION

[0006] Embodiments of the present disclosure generally relate to photonic integrated interconnect substrates and methods for forming optical structures on those substrates for devices, including interconnection of electronic circuits within at most chip components and between multi-chip components at different distances from each other.

[0007] In one embodiment, there is provided an optoelectronic device assembly having a substrate having a chip mounting area and an optical fiber connector area, the chip mounting area being configured to receive a photonic transceiver chip (providing electrical-to-optical and optical-to-electrical conversion and other functions), and the optical fiber connector area being configured to couple to an optical fiber connector. The substrate further includes a plurality of optical structures between the photonic transceiver chip and the optical fiber connector, wherein each of the plurality of optical structures is operable to transmit light between a first end and a second end of each of the plurality of optical structures, the first end being configured to receive light transmitted from a plurality of waveguides of the optical transceiver chip or light to be received by the waveguides of the optical transceiver chip, and the second end being configured to receive light transmitted from a plurality of optical fibers of the optical fiber connector or light to be received by the optical fibers of the optical fiber connector coupled to the substrate.

[0008] In another embodiment, a co-packaged electronic and photonic device is provided. The co-packaged electronic and photonic device includes a packaging substrate, one or more electrical or optoelectronic integrated circuits mounted on the packaging substrate, and one or more electronic and photonic devices mounted on the packaging substrate, wherein each of the one or more electronic and photonic devices is connected to one or more of the electrical or optoelectronic integrated circuits. Each of the one or more electronic and photonic devices also includes a support substrate having an optical transceiver chip mounting area configured to receive an optical transceiver chip and a fiber optic connector area configured to couple to a fiber optic connector. The support substrate of the one or more electronic and photonic devices also includes a plurality of optical structures formed within the support substrate and operable to transmit light between a first end and a second end of the support substrate.

[0009] In some embodiments, a method for fabricating an electronic and photonic device is provided. The method includes depositing a patterned layer over a surface of a substrate including a photon glass layer having a first refractive index and having openings formed therein, with portions of the surface of the substrate exposed in the openings. Subsequently, portions of the substrate exposed within the openings of the patterned layer are removed to form a plurality of structures in the substrate separated by a plurality of trenches. The method then continues by removing the patterned layer and depositing a fill layer over the plurality of structures and into the plurality of trenches to form a plurality of optical structures, the fill layer having a second refractive index different from the first refractive index. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0010] In one aspect of the above method, the method includes forming a chip mounting area on a surface of the photon glass layer at a first edge of the substrate, wherein the chip mounting area is operable to connect a photonic or electronic integrated circuit to the photon glass layer substrate.

[0011] In another aspect of the above method, the method includes forming a fiber optic connector on a surface of the photon glass layer at a second edge of the substrate, wherein the fiber optic connector is operable to connect a fiber optic cable to the photon glass layer substrate.

[0012] In one aspect of the above method, the method includes depositing a patterned layer over a surface of the substrate. Depositing the patterned layer includes depositing a patterned hard mask or forming a patterned photoresist over the substrate.

[0013] In another aspect of the above method, depositing a patterned layer over the surface of the substrate includes depositing a hard mask over the surface of the substrate, forming a patterned photoresist on the hard mask, the patterned photoresist having openings formed therein, wherein portions of the hard mask are exposed in these openings, and removing the exposed portions of the hard mask to expose portions of the surface of the substrate.

[0014] In one aspect of the above method, depositing a fill layer includes depositing one or more high refractive index materials, the high refractive index materials including one or more of amorphous silicon, crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials having suitable optical properties.

[0015] In another embodiment, a method for manufacturing electronic and photonic devices is provided. The method includes depositing a patterned layer over the surface of a substrate including a photon glass layer, the photon glass layer having a first refractive index, and the patterned layer having openings formed therein, portions of the surface of the substrate being exposed in these openings. Subsequently, the method continues by performing an ion implantation process on the exposed portions of the substrate to implant a plurality of dopant ions into the surface of the exposed portions of the substrate. The exposed portions of the substrate including the plurality of dopant ions define a plurality of optical structures having a second refractive index different from the first refractive index. Each of the plurality of optical structures also includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0016] In one aspect of the above method, depositing a patterned layer includes depositing a patterned hard mask or forming a patterned photoresist over the substrate.

[0017] In another aspect of the above method, each of the waveguides of the plurality of optical structures includes a first end extending from a first edge of the substrate, the first ends of these waveguides having a cross-sectional dimension with a height dimension of approximately 1 micron.

[0018] In yet another aspect of the above method, each of the waveguides of the plurality of optical structures includes a second end extending from a second edge of the substrate, the second ends of these waveguides having a cross-sectional dimension with a height dimension of approximately 1 micron. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To understand in detail the manner in which the above features of the present disclosure are realized, reference may be made to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, and other equivalent embodiments may be recognized.

[0020] Figure 1 Perspective view of at least a portion of a co-packaged substrate having one or more electrical and photonic devices formed thereon, according to one embodiment.

[0021] Figure 2A And Figure 2B Top view of a photonic engine, according to one embodiment.

[0022] Figures 3A to 3E Schematic cross-sectional view of a portion of one or more optical silicon photonic devices, according to one embodiment.

[0023] Figures 4A to 4G Schematic cross-sectional view of a portion of one or more optical silicon photonic devices, according to one embodiment.

[0024] Figures 5A to 5E Schematic cross-sectional view of a portion of one or more optical silicon photonic devices, according to one embodiment.

[0025] Figure 6 Flowchart illustrating operations of a method for fabricating an optical device on a photonic glass layer substrate, according to one embodiment.

[0026] Figure 7 Flowchart illustrating operations of a method for fabricating an optical device on a photonic glass layer substrate, according to one embodiment.

[0027] Figure 8 Flowchart illustrating operations of a method for fabricating an optical device on a photonic glass layer substrate, according to one embodiment.

[0028] Figure 9 Is according to one embodiment by using Figure 10 Schematic cross-sectional view of a portion of a photonic engine formed by using section line C-C in

[0029] Figure 10 Is according to one embodiment by using Figure 2A Schematic cross-sectional view of a portion of a photonic engine formed by using section line B-B in

[0030] Figure 11 Is according to one embodiment by using Figure 2A Schematic alternative cross-sectional view of a portion of a photonic engine formed by using section line B-B in

[0031] Figure 12 Is according to one embodiment by using Figure 2A Schematic cross-sectional view of a portion of a pluggable connector formed by using section line B-B in

[0032] For purposes of promoting understanding, identical element symbols have been used to indicate identical elements common to the various figures where possible. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. Detailed Description

[0033] The embodiments described herein relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnections between electrical, optoelectronic, and photonic devices. One or more optical silicon photon devices described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single package substrate to form co-packaged optical and electrical devices. The methods described herein enable the mass fabrication of electrical, optoelectronic, and optical silicon photon devices having multiple optical structures, such as waveguides, formed on or integrated with a photon glass layer substrate.

[0034] One embodiment of the co-packaged optical and electrical devices described herein includes a package substrate formed with one or more optical silicon photon devices and one or more optoelectronic chips. The one or more optical silicon photon devices are connected to the one or more optoelectronic chips and provide an interface to operably connect the optoelectronic chips to an external network optical fiber connection inserted into the optical silicon photon devices. The methods described herein provide a scalable process for fabricating optical silicon photon devices having optical structures of different sizes, materials, and properties formed on or integrated with a photon glass layer substrate. The fabrication of the optical silicon photon devices described herein can also be configured based on varying the electro-optic photon circuits and network optical fiber connection properties that the optical silicon photon devices can use.

[0035] As used herein, the term "about" refers to a variation of + / - 10% from a nominal value. It is understood that such variation can be included in any value provided herein.

[0036] In various embodiments of the present disclosure, a layer or other material is referred to as being deposited. It is understood that the deposition of such materials can be performed using any conventional method used in semiconductor fabrication, such as, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, selective deposition of any of the foregoing, combinations of the foregoing, and any other suitable method. It is understood that when a method operation is described herein as depositing materials at two or more separate locations, the depositions can occur simultaneously, or the materials can be deposited in separate sub-operations.

[0037] In various embodiments of the present disclosure, a layer or other material is said to be etched. It should be understood that the etching of these materials can be performed using any conventional methods used in semiconductor manufacturing, such as but not limited to reactive ion etching (RIE), dry etching, wet etching, or laser ablation, combinations of the above methods, and any other suitable methods of removing materials. It should be understood that when a method operation is described herein as etching two or more types of materials, the etching can occur simultaneously with the same etching process, or the etching can be performed in separate sub-operations using different etching processes. For example, an operation of etching a metal and a dielectric includes a first etching sub-operation using a first etching process for etching the metal, and the operation further includes a second etching sub-operation using a second etching process for etching the dielectric.

[0038] Figure 1 Perspective view of a portion of an exemplary co-packaged optical and electrical device 100, the optical and electrical device including an electrical or optoelectronic chip 102 connected to a photonic integrated interconnect unit 103 via a plurality of optical waveguides or electrical trace interconnects 104, where all of the foregoing are formed on or disposed on a package substrate 101. In one embodiment, the electrical or optoelectronic chip 102 can include any high-density chip having a high input / output (I / O) pin count. In one example, the high-density chip has an I / O pin count between 100 and 2000 or up to and greater than 2000 I / O pins. Examples of the electrical or optoelectronic chip 102 include but are not limited to data center SWITCH chips, artificial intelligence (AI) chips, and the like.

[0039] The photonic integrated interconnect unit 103 includes a fiber optic connector area that is configured to couple to a fiber optic connector 112 for removably connecting a fiber optic cable 120 to the photonic integrated interconnect unit 103. In one embodiment, the fiber optic cable 120 can be inserted into the fiber optic connector 112 to operably connect the fiber optic cable 120 to the co-packaged optical and electrical device 100. In one embodiment, the photonic integrated interconnect unit 103 is configured to connect a fiber optic cable 120 that includes but is not limited to a single-mode fiber optic cable having a 9-micron core diameter. The fiber optic connector 112 can further include a plurality of optical fibers 112A ( Figure 10 ) to operably connect a fiber optic cable 120 having 1 to 74 cores, 74 to 148 cores, and up to and greater than 148 cores to the photonic integrated interconnect unit 103.

[0040] In one embodiment, the photonic integrated interconnect unit 103 in the group of co-packaged electrical and optical devices 100 is configured to transmit signals between an electrical or optoelectronic chip 102 and an optical fiber cable 120 connected to the photonic integrated interconnect unit 103. The photonic integrated interconnect unit 103 includes a photonic glass layer (PGL) substrate 106, and a plurality of optical structures 110 integrated with or formed on the PGL substrate 106 1 -110 N and an optical transceiver integrated circuit (SiPho chip) 108 mounted on the PGL substrate 106 and coupled to the plurality of optical structures 110 at a first interface 107 1 -110 N and an optical fiber connector 112 connected to both the PGL substrate 106 and the plurality of optical structures 110 at a second interface 109 1 -110 N Both.

[0041] In one embodiment, the SiPho chip 108 in the photonic integrated interconnect unit 103 operates to convert an electrical signal into an optical signal and vice versa. The plurality of optical structures 110 in the photonic integrated interconnect unit 103 1 -110 N operate to transmit optical signals between the SiPho chip 108 and the optical fiber connector 112, and the optical waveguide or electrical trace interconnect 104 operates to transmit electrical or optical signals between the photonic integrated interconnect unit 103 (specifically, the SiPho chip 108) and the electrical or optoelectronic chip 102. The optical waveguide or electrical trace interconnect 104 may include metal traces formed within the package substrate 101, which in some embodiments may include metal traces formed in a printed circuit board (PCB) substrate or metal traces formed within a plurality of redistribution layers (e.g., dielectric-containing layers) formed on a solid substrate (e.g., a silicon or glass core substrate).

[0042] The photon engine 103 may further include one or more electronic PHY chips 111 coupled to the SiPho chip 108, optionally. The electronic PHY chips 111 are generally used to assist the operations performed by the optical chip. In one embodiment, the electronic PHY chips 111 are operably connected to the SiPho chip 108 to assist the SiPho chip 108 with various electrical functions. As shown, the electronic PHY chips 111 may be mounted on top of the SiPho chip 108 and thus directly connected to the SiPho chip 108. Alternatively, the electronic PHY chips 111 may be embedded in the PGL substrate 106 and connected to the SiPho chip 108 via the PGL substrate 106 (commonly referred to herein as the substrate 106). Additionally, the electronic PHY chips 111 may be mounted on or embedded in the package substrate 101 and connected to the SiPho chip 108 via the electrical interconnect 104.

[0043] Figure 2A and Figure 2B is a top view of the photon engine 103 according to one embodiment. In some embodiments, as Figure 2A shown, the photon engine 103 includes a SiPho chip 108 mounted near one end of the PGL substrate 106, an optical fiber connector 112 connected to the opposite end of the PGL substrate 106 from the SiPho chip 108, and a plurality of optical structures 110 extending between the SiPho chip 108 and the optical fiber connector 112 1 -110 N . In one embodiment, each of the plurality of optical structures 110 1 -110 N includes a light transmission region for transmitting light in either direction between a first interface 107 and a second interface 109. The light transmitted via the optical structure may be received from one or more of the plurality of waveguides 108A ( Figure 2B ) of the SiPho chip 108, or from one or more of the plurality of optical fibers within the optical fiber connector 112, with which a light signal source communicates during use. The SiPho chip 108 is typically configured to receive (e.g., detect) the light transmitted through the optical structures 1101-110N and also to emit (e.g., transmit) light to the optical structures 110 1 -110 N in an attempt to communicate with an external device connected via the optical fiber connector 112. The SiPho chip 108 may be configured to transmit light to the optical structures 110 1 -110 NIn the case where the optical transmitter is located outside the PGL substrate 106, light passes through the optical structure 110 1 -110 N and is transmitted to the SiPho chip 108, and then modulated by the SiPho chip 108 to generate a transmission signal provided to the optical structure 110 1 -110 N .

[0044] In some embodiments that can be combined with other embodiments described herein, a plurality of optical structures 110 1 -110 N are formed on the PGL substrate 106 (e.g., directly or indirectly) or integrated with the PGL substrate. Each of the plurality of optical structures 110 1 -110 N in the photon engine 103 can be formed by one of the various methods described herein.

[0045] In one embodiment that can be combined with other embodiments described herein, the light transmission regions within each of the plurality of 110 1 -110 N can have the same cross-sectional dimensions, such as height and width. In another embodiment that can be combined with other embodiments described herein, the light transmission region within at least one of the plurality of optical structures 110 1 -110 N can have at least one cross-sectional dimension different from that of the other optical structures 110 within the PGL substrate 106, such as one of height and width. In one embodiment that can be combined with other embodiments described herein, the light transmission regions within each of the plurality of optical structures 110 1 -110 N can have the same refractive index. In another embodiment that can be combined with other embodiments described herein, when compared with the remaining optical structures 110 1 -110 N within the PGL substrate 106, the light transmission region within at least one of the plurality of optical structures 110 1 -110 N can have a different refractive index or a plurality of different refractive indices or a gradient of refractive indices or other refractive index variation structures.

[0046] In one aspect, the optical structure 110 1 -110 NThe number depends on the number of waveguides 108A to be connected in the SiPho chip 108, which may also correspond to the number of fiber optic connections to be connected to the optoelectronic chip 102. In one embodiment, the optoelectronic chip 102 may include seventy-two (72) fiber optic connections such that seventy-two (72) corresponding interconnects 104 extend from the optoelectronic chip 102 and connect to seventy-two (72) corresponding optical fibers and waveguides 108A in the SiPho chip 108 of the photon engine 103. In order to properly connect the SiPho chip 108 to the fiber optic connector 112 via the plurality of optical structures 110 1 -110 N in the photon glass layer substrate 106, seventy-two (72) corresponding optical structures 110 are formed on the PGL substrate 106 or these optical structures are integrated with the PGL substrate 106. In this example, as shown in Figure 2A and Figure 2B , N will be equal to 72, and thus the optical structures 110 are spaced apart from one edge of the PGL substrate 106 to the other edge of the PGL substrate in the X-Y plane. In this example, the optical structures 110 1 are located Figure 2A near the topmost edge, and the optical structures 110 72 will be located closest to Figure 2A the bottommost edge. As discussed further below, the optical structures 110 1 -110 N are spaced apart and separated by a material having optical properties (such as refractive index (n)) different from those of the light-transmitting portions of the optical structures 110 1 -110 N .

[0047] The plurality of optical structures 110 1 -110 N are typically resized and configured to properly connect to the plurality of waveguides 108A within the SiPho chip 108. In one embodiment, the plurality of waveguides 108A ( Figure 2B ) at the output of the SiPho chip 108 or at the portion communicating with the optical structures have a core with a height dimension of approximately 1 micrometer (μm) in cross-sectional size. In one configuration, the output of the SiPho chip 108 has a square or rectangular cross-section having at least one dimension with a length equal to approximately 1 μm. For example, the square cross-section of the waveguide 108A may have a core with a height and width of 1 μm. Thus, the light transmitted to and from the SiPho chip 108 will be transmitted through the 1-micrometer waveguide 108A.

[0048] In contrast, the light transmitted to and from the fiber optic cable 120 through the fiber optic connector 112 can have different form factors, such as a core cross-sectional dimension of approximately 9 μm in size. For example, the fiber optic connector 112 can have a square, rectangular, or circular cross-section with a core height dimension of approximately 9 μm in size. Thus, in some embodiments, each of the plurality of optical structures 110 1 -110 N is formed such that the light propagating through the plurality of optical structures 110 between the SiPho chip 108 and the fiber optic cable 120 1 -110 N is correspondingly expanded or compressed depending on the propagation direction of the optical signal. In one example, the plurality of optical structures 110 extending from the second interface 109 adjacent to the 9 mm fiber in the fiber optic connector 112 1 -110 N have transmission regions whose cross-sectional areas vary at different portions of each structure to facilitate coupling to the plurality of 1 μm waveguides 108A in the SiPho chip 108. In one embodiment, the plurality of optical structures 110 1 -110 N taper from a 9 μm-sized core size along at least a portion of their length until they approach a 1 μm-sized core size near the first interface 107, where it is assumed that the varying-sized core size is related to the dimensions of the sides of the optical structure 110 having a square or rectangular cross-sectional shape. In some embodiments, the tapered optical structure 110 has a cross-sectional area ratio that can be greater than 1:1 and less than approximately 1:100, or less than 1:81, when measured at one end of the optical structure 110 compared to the other end. In another embodiment, the plurality of optical structures 110 extending from the second interface 109 adjacent to the fiber optic connector 112 1 -110 N have a varying refractive index along at least a portion of their length from the second interface 109 to the first interface 107 to facilitate coupling between the optical components within the SiPho chip 108 and the fiber optic connector 112 having different cross-sectional dimensions.

[0049] In another aspect, the photon engine 103 is configured such that the transmission loss of the optical signal between the first interface 107 and the second interface 109 is approximately or less than 3 dB, including the loss attributable to the transmission of the optical signal through the plurality of optical structures 110 1 -110 N themselves. In one embodiment, the transmission loss can depend to a large extent on the coupling at the first interface 107 between the SiPho chip 108 and the plurality of optical structures 110 1 -110 N AsFigure 2B As shown, in one embodiment, the SiPho chip 108 is mounted on the coupling surface 208 at the chip mounting area 204 of the PGL substrate 106. When mounted on the chip mounting area 204, a plurality of waveguides 108A disposed on the side surface 108B of the SiPho chip 108 are aligned with a plurality of optical structures 110 found at the first interface 107 1 -110 N aligned.

[0050] In some embodiments that can be combined with other embodiments described herein, the PGL substrate 106 further includes one or more fiducial marks 206 to assist in the alignment and mounting of the SiPho chip 108 on the chip mounting area 204. The one or more fiducial marks 206 are used to guide and assist in aligning the position of the SiPho chip 108 along the X-Y plane of the PGL substrate 106 to ensure that the mounting of the SiPho chip 108 is correctly aligned with one or more electrical contacts (e.g., vias 1006 ( Figure 10 )) and the optical structure portion of the PGL substrate. Thus, in one embodiment, the error tolerance (to be further discussed below) for coupling or hybridizing the SiPho chip 108 with the plurality of optical structures 110 1 -110 N together can be in the range of 0.1 micrometer to 2 micrometers to ensure optimized connection for minimum signal loss. In one embodiment, the misalignment of the center of the waveguide 108A with the optical structure 110 1 -110 N is maintained such that the lateral misalignment in the Y direction (i.e., the top-to-bottom direction in Figure 2B ) is less than 1 to 2 micrometers. In some embodiments, the misalignment of the center of the waveguide 108A with the optical structure 110 1 -110 N is also maintained such that the vertical misalignment in the Z direction ( Figure 10 or Figure 11 ) is less than 1 to 2 micrometers. In one embodiment, the variability of the vertical misalignment can depend on the variability of the compression of a plurality of solder balls 1010 or other electrical contacts used to electrically couple the SiPho chip 108 to a plurality of vias 1006 ( Figures 10 to 11 ) formed in a portion of the PGL substrate 106.

[0051] Figure 6 For illustration, a portion 300 of the PGL substrate 106 used in manufacturing (as shown in Figures 3A to 3E ), such as the optical structure 110 1 -110 NFlowchart of operations of an exemplary method 600 for a portion of. Method 600 includes operations 602 to 618. In one embodiment, method 600 is a single substrate process or a batch process for multiple substrates involved in simultaneous manufacturing. At operation 602, as Figure 3A shown, the cladding layer 303 is disposed on the surface of the support substrate 301. The cladding layer 303 can be disposed on the surface using a liquid material casting process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition (PECVD) process, a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition process, or an evaporation process. In one embodiment, the cladding layer 303 is made of a material having a refractive index relatively lower than that of the core material layer 302 formed in subsequent operations. In some embodiments, the cladding layer 303 has a refractive index between 1.3 and 1.5. In some embodiments, the cladding layer 303 used in operation 602 can be formed of one or more low refractive index materials, including Si 3 N 4 , SiO 2 , doped SiO 2 , low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials.

[0052] At operation 604, as Figure 3A shown, the core material layer 302 is disposed on the surfaces of the cladding layer 303 and the support substrate 301. The core material layer 302 can be disposed on the surface of the cladding layer 303 using a liquid material casting process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, or an evaporation process. In some embodiments, the support substrate 301 includes a material selected from the group consisting of silicon dioxide (SiO 2 ), boron trioxide (B 2 O 3 ), and aluminum oxide (Al 2 O 3 ).

[0053] Depending on the embodiment, the core material layer 302 can be a low refractive index material or a high refractive index material. The material used to form the core material layer 302 has a refractive index different from that of the material used to form the cladding layer 303. In some embodiments, the core material layer 302 has a refractive index between 1.4 and 1.5. In another embodiment, the material used to form the core material layer 302 has a refractive index higher than that of the material used to form the cladding layer 303. Generally, the refractive index of the core material layer 302 is different from that of the cladding layer 303 and is also different from that of the encapsulation layer 314 discussed further below. In one example, the core material layer 302 has a refractive index between 1.45 and 1.50, while the cladding layer 303 and the encapsulation layer 314 have a refractive index between 1.40 and 1.44.

[0054] In one embodiment that can be combined with other embodiments described herein, the core material layer 302 can be formed of one or more materials including, but not limited to, silicon carbide (SiC), silicon oxycarbide (SiOC), titanium dioxide (TiO 2 ), silicon dioxide (SiO 2 ), vanadium(IV) oxide (VO x ), aluminum oxide (Al 2 O 3 ), aluminum-doped zinc oxide (AZO), indium tin oxide (ITO), tin dioxide (SnO 2 ), zinc oxide (ZnO), tantalum pentoxide (Ta 2 O 5 ), silicon nitride (Si 3 N 4 ), zirconium dioxide (ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), cadmium stannate (Cd 2 SnO 4 ), silicon mononitride (SiN), silicon oxynitride (SiON), barium titanate (BaTiOs), diamond like carbon (DLC), hafnium(IV) oxide (HfO 2 ), lithium niobate (LiNbO 3 ), materials containing silicon carbon nitride (SiCN) or other materials suitable for forming optical structures.

[0055] At operation 606, the patterned layer 305 is disposed on the core material layer 302. The patterned layer 305 defines an exposed negative portion of the core material layer 302 that, when removed, corresponds to the structural pattern that will enable the formation of the optical structure 110 in subsequent operations.

[0056] In one embodiment, as shown in Figure 3B and Figure 3C and described in further detail in Operations 608 through 612 below, disposing the patterned layer 305 on the core material layer 302 may include disposing a hard mask 304 on the core material layer 302, disposing a patterned photoresist 306 on the hard mask 302, the patterned photoresist 306 defining an exposed portion of the hard mask 304, and removing the exposed portion of the hard mask 304 to form a patterned hard mask 304 corresponding to the patterned photoresist 306.

[0057] In another embodiment, disposing the patterned layer 305 on the core material layer 302 in Operation 606 may include: forming a patterned photoresist on the core material layer 302 by disposing a photoresist layer on the core material layer 302 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines an exposed negative portion of the core material layer 302. The patterned photoresist will allow selective etching of the core material layer 302 below the patterned photoresist because the patterned photoresist protects certain regions of the core material layer 302 from unwanted etching in subsequent processes. In such embodiments, Method 600 continues with Operation 614 below to remove the negative structural portion 312 of the core material layer 302 defined by the patterned layer 305.

[0058] In Operation 608, as shown in Figure 3B the hard mask 304 is disposed on the core material layer 302. The hard mask 304 may be disposed on the core material layer 302 using a liquid material pouring process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, or an evaporation process. The hard mask 304 may include, but is not limited to, materials selected from the group consisting of chromium (Cr), silver (Ag), Si 3 N 4 SiO 2 , TiN, and carbon (C)-containing materials.

[0059] At Operation 610, as shown in Figure 3BAs shown, the patterned photoresist 306 is disposed on the core material layer 302 and, when present, also on the hard mask 304. The patterned photoresist 306 allows selective etching of the material below the patterned photoresist 306 because the patterned photoresist 306 protects certain areas from unwanted etching in subsequent processes. In one example, the patterned photoresist 306 is formed by disposing a photoresist material on the hard mask 304 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist 306 defines the exposed portion 310 of the hard mask 304 (i.e., the opening of the hard mask 304). The exposed portion 310 corresponds to the pattern 308 that will be used to form the optical structure 110. The patterned photoresist 306 can be disposed on the hard mask 304 or the core material layer 302 using a spin coating process. The photoresist material 306 can include, but is not limited to, materials containing photosensitive polymers.

[0060] At operation 612, as Figure 3C shown, the exposed portion 310 of the hard mask 304 is removed. Removing the hard mask portion 310 exposes the negative structure portion 312 of the core material layer 302. The negative structure portion 312 corresponds to the structural pattern 308 that will enable the formation of the optical structure 110 in subsequent operations. In one embodiment, the exposed portion 310 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of openings in the hard mask 304.

[0061] At operation 614, as Figure 3C shown, the negative structure portion 312 of the core material layer 302 is removed to form a plurality of optical structures 110. In one embodiment, which can be combined with other embodiments described herein, the negative structure portion 312 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of trenches 316 in the core material layer 302. In one embodiment, the removal of the exposed portion 310 in operation 612 and the etching of the negative structure portion 312 in operation 614 can be performed simultaneously or sequentially. In one aspect, the hard mask 304 has a lower etching rate than the material of the core material layer 302.

[0062] At operation 616, the patterned layer 305 is removed. Removing the patterned layer 305 includes removing the hard mask and / or the photoresist layer. In Figure 3D the example shown, removing the patterned layer 305 includes removing the hard mask 304 and the patterned photoresist 306. Removing the hard mask 304 can include ion etching, reactive ion etching, or selective wet chemical etching. Removing the patterned photoresist 306 can include using the ashing process or etching process described herein.

[0063] At operation 618, as Figure 3EAs shown, the encapsulation layer is disposed on the cladding layer 303 and the plurality of optical structures 110. The encapsulation layer 314 can be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 314 is made of a material having a refractive index relatively lower than that of the core material layer 302. In some embodiments, the refractive index of the encapsulation layer 314 is between 1.3 and 1.5, such as between 1.40 and 1.44. In some embodiments, more than one encapsulation layer having more than one refractive index can be used.

[0064] In one embodiment that can be combined with other embodiments herein, the encapsulation layer 314 can be formed of one or more low refractive index materials, including Si 3 N 4 , SiO 2 , doped SiO 2 , low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials. The materials used to form the encapsulation layer 314 have a refractive index different from that of the materials used to form the core material layer 302. In one embodiment, the refractive index of the materials used to form the encapsulation layer 314 is lower than that of the materials used to form the core material layer 302. The low refractive index materials discussed herein are contrasted with "high" refractive index materials such as amorphous silicon and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials having suitable optical properties. It is contemplated that materials and combinations of materials can be used to form the cladding layer 303, the encapsulation layer 314, and / or the core material layer 302 discussed herein, and these materials can be selected based on the target optical properties of the optical device fabricated in method 600.

[0065] In another embodiment that can be combined with other embodiments herein, the encapsulation layer 314 can be formed to include a sandwich layer (not shown) extending above the top surface of the encapsulation layer 314. The sandwich layer can be used to separate the encapsulation layer 314 and the optical structures 110 formed by the core material layer 302 from additional optical structures of a second optical structure material layer (not shown). Thus, additional different optical layer optical structures can be formed and layered on top of the portion 300 shown in Figure 3E without directly contacting the optical structures 110 or the encapsulation layer 314. Further, the lower the refractive index of the material used for encapsulation, the lower the aspect ratio of the constituent nanostructures (patterned features) of each optical structure. In one embodiment, lower aspect ratio features result in thinner optical layers, as well as faster and cleaner etching. Thus, the systems and methods herein result in a more efficient manufacturing process in terms of time, cost, and complexity.

[0066] Although herein Figures 3A to 3EThe optical structure 110 shown in the figure is illustrated as having a cross-section that is approximately square or rectangular, but it is contemplated that in other examples, the optical structure may include tapered sidewalls and thus form a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top of the opening than at the bottom.

[0067] Accordingly, method 600 can be used to form the optical structure 110 by using a negative patterning process 1 -110 N , and these optical structures include the remaining portion of the core material layer 302. As Figure 3E shown, the PGL substrate 106 includes seven optical structures (i.e., the optical structure 110 1 -110 7 ), which are disposed on the support substrate 301, and each optical structure is encapsulated and separated by at least a portion of the encapsulation layer 314.

[0068] Figure 7 FIG. is used to illustrate a flowchart of the operations of another exemplary method 700 for manufacturing a portion 400 of the PGL substrate 106 (as Figures 4A to 3E shown), such as a portion of the optical structure 110 1 -110 N . Method 700 includes operations 702 to 718. Method 700 begins with operation 702, in which a patterned layer 405 is disposed on a support substrate 401. The patterned layer 405 defines an exposed negative portion of the support substrate 401, which, when removed, corresponds to a structural pattern that will enable the formation of the optical structure 110 in subsequent operations.

[0069] In one embodiment, as Figure 4B and Figure 4C shown and further described in detail in operations 704 to 708 below, disposing the patterned layer 405 on the support substrate 401 may include disposing a hard mask 402 on the support substrate 401, disposing a patterned photoresist 404 on the hard mask 402, the patterned photoresist 404 defining an exposed portion of the hard mask 402, and removing the exposed portion of the hard mask 402 to form a patterned hard mask 402 corresponding to the patterned photoresist 404.

[0070] In another embodiment, disposing the patterned layer 405 on the support substrate 401 in operation 702 may include directly disposing a patterned photoresist on the support substrate 401, or disposing a photoresist layer on the support substrate 401 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines an exposed negative portion of the support substrate 401. The patterned photoresist will allow selective etching of the support substrate 401 under the patterned photoresist, as the patterned photoresist protects certain regions of the support substrate 401 from unwanted etching in subsequent processes. In this embodiment, method 600 proceeds to operation 710 below to remove the negative structural portion 410 of the support substrate 401 defined by the patterned layer 405.

[0071] At operation 704, as Figure 4A shown, the hard mask 402 is disposed on the support substrate 401. The hard mask 402 can be disposed on the support substrate 401 using a liquid material pouring process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, or an evaporation process. The hard mask 304 can include, but is not limited to, materials selected from the group consisting of chromium (Cr), silver (Ag), Si 3 N 4 , SiO 2 , TiN, and carbon (C)-containing materials. In some embodiments, the support substrate 401 includes a material selected from the group consisting of silicon dioxide (SiO 2 ), boron trioxide (B 2 O 3 ), and aluminum oxide (Al 2 O 3 ).

[0072] At operation 706, the patterned photoresist 404 is disposed on the support substrate 401 and, when present, also on the hard mask 402, as Figure 4BAs shown in [reference], the patterned photoresist 404 allows for selective etching of the material beneath the patterned photoresist 404, as the patterned photoresist 404 protects certain areas from unwanted etching during subsequent processes. In one example, the patterned photoresist 404 is formed by depositing a photoresist material on the hard mask 402 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist 404 defines the exposed portion 408 of the hard mask 402 (i.e., the opening of the hard mask 402). The exposed portion 408 corresponds to the structure pattern 406 to result in the formation of multiple optical structures 110. In one example, the patterned photoresist 404 can be deposited on the hard mask 402 using a spin coating process. The photoresist material 404 can include, but is not limited to, materials containing photosensitive polymers.

[0073] At operation 708, as Figure 4C shown in [reference], the exposed portion 408 of the hard mask 402 is removed. Removing the exposed portion 408 exposes the negative structure portion 410 of the support substrate 401. The negative structure portion 410 corresponds to the structure pattern 406 to result in the formation of the optical structures 110. In one embodiment, the exposed portion 408 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form multiple openings in the hard mask 402.

[0074] At operation 710, as Figure 4C shown in [reference], the negative structure portion 410 of the support structure 401 is removed to form the patterned structure 406. In one embodiment that can be combined with other embodiments described herein, the negative structure portion 410 of the support substrate 401 can be removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form multiple trenches 412 in the support substrate 401. In one embodiment, the removal of the exposed portion 408 in operation 708 and the etching of the portion of the support substrate 401 in operation 712 can be performed simultaneously or sequentially. In one aspect, the hard mask 402 has a lower etching rate than the material of the support substrate 401.

[0075] At operation 712, the patterned layer 405 is removed. Removing the patterned layer 405 can include removing the hard mask and / or the photoresist layer. In Figure 4D the example shown in [reference], removing the patterned layer 405 includes removing the hard mask 402 and the patterned photoresist 404, leaving the support substrate 401 with multiple patterned structures 406, each patterned structure 406 separated by multiple trenches 412. In one embodiment, removing the hard mask 402 can include ion etching, reactive ion etching, or selective wet chemical etching. Removing the patterned photoresist 404 can include a conventional ashing process or an etching process.

[0076] At operation 714, as Figure 4EAs shown, the filling layer 418 is disposed on the support substrate 401 and the patterned structure 406 formed therein. The filling layer 418 may include, but is not limited to, materials selected from the group consisting of Si 3 N 4 , SiO 2 , low refractive index fluoropolymers, hydrogels, and materials containing photoresist materials. The filling layer 418 may be disposed on the support substrate 401 and disposed into the plurality of trenches 412 by one or more of PVD, CVD, FCVD, and spin coating processes. The flowable nature of the filling layer 418 allows the filling layer 418 to also flow into each of the plurality of trenches 412.

[0077] In one embodiment, the filling layer 418 is formed of a material having a refractive index different from that of the PGL substrate 106 in the support substrate 401. In some embodiments, the filling layer 418 has a refractive index between 1.4 and 1.5. In another embodiment, the filling layer 418 is formed of a material having a refractive index greater than that of the support substrate 401. In certain embodiments, the filling layer 418 may be formed of a high refractive index material such as amorphous silicon and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials having suitable optical properties. It is contemplated that materials and combinations of materials may be used to form the filling layer 302 discussed herein, and these materials may be selected based on the target optical properties of the optical device fabricated in method 700. In one example, the filling layer 418 has a refractive index between 1.45 and 1.50, while the support substrate 401 has a smaller refractive index between 1.40 and 1.44.

[0078] At operation 716, as Figure 4F shown, the excess filling layer portion 418A is removed so that the height of the filling layer 418 within the plurality of trenches 412 is approximately the same as the height of the patterned structure 406 of the support substrate 401. According to one embodiment, the excess filling layer 418A may be removed using a chemical mechanical polishing (CMP) process. The removal of the excess filling layer 418 forms a plurality of optical structures 110 separated by the patterned structure 406 in the substrate 401.

[0079] Although the optical structures 110 shown herein Figures 4A to 4F are illustrated as having a generally square or rectangular cross-section, it is contemplated that in other examples, the optical structures may include tapered sidewalls and thus form a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top of the opening than at the bottom.

[0080] At operation 718, as Figure 4GAs shown, the encapsulation layer 420 is optionally disposed on the support substrate 401 and the plurality of optical structures 110. The encapsulation layer 420 can be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 420 is made of a low refractive index material compared to the refractive index of the filling layer 418. In some embodiments, the refractive index of the encapsulation layer 420 is between 1.3 and 1.9, such as between 1.40 and 1.44.

[0081] Thus, the method 700 can be used to form the optical structures 110 by using a negative patterning process 1 -110 N , which optical structures include the remaining portion of the filling layer 418. As Figure 4F and Figure 4G shown, the PGL substrate 106 includes seven optical structures (i.e., the optical structures 110 1 -110 7 ), which optical structures include portions of the filling layer 418 disposed within the support substrate 401 and thus separated by portions of the support substrate 401.

[0082] Figure 8 FIG. is an icon for manufacturing a part 500 of the PGL substrate 106 (as Figures 5A to 5E shown), such as an exemplary method 800 of operations for a part of the optical structure 110 1 -110 N . The method 800 includes operations 802 to 808. The method 800 provides for depositing a species of a refractive index changing material into a portion of the support substrate 501 via an ion implantation process. Ion implantation is a surface modification technique that can change the optical properties of a portion of the surface layer of the support substrate 501. Ion implantation allows precise control of the dopant composition and penetration depth by selecting the species and energy of the doping ions. In some embodiments, the support substrate 501 includes a material selected from the group consisting of silicon dioxide (SiO 2 ), boron trioxide (B 2 O 3 ), and aluminum trioxide (Al 2 O 3 ).

[0083] At operation 802, as Figure 5AAs shown, the patterned layer 502 is disposed on the support substrate 501. The patterned layer 502 defines an exposed substrate portion 504 of the support substrate 501 (i.e., the opening of the patterned layer 304). The patterned layer 502 is configured to allow selective ion implantation of dopant ions into the support substrate 501 disposed below the patterned layer 502 because portions of the patterned layer 502 can act as a mask to impede the dopant ions from reaching selected portions of the support substrate 501 below the patterned layer 502.

[0084] The patterned layer 502 can be a patterned photoresist or a patterned hard mask. In one embodiment, the patterned layer 502 can be a patterned photoresist formed of a material including, but not limited to, a polymeric material such as formed from a phenolic resin, an epoxy resin, or an acrylic resin. The patterned photoresist must be thick enough to reliably absorb the ions at these sites. Thus, it is generally necessary to appropriately select the resist film thickness when adjusting the ion energy of the implantation process. In one example, the patterned layer 502 can be formed by disposing a photoresist material on the substrate 501 and performing a lithography process to pattern and develop the photoresist material. In another embodiment, the patterned layer 502 can be a patterned hard mask. The hard mask can include, but is not limited to, materials selected from the group consisting of chromium (Cr), silver (Ag), Si 3 N 4 , SiO 2 , TiN, and carbon (C)-containing materials.

[0085] At operation 804, as Figure 5BAs shown, an ion implantation process is performed on the support substrate 501. In the ion implantation process, dopant ions are accelerated and implanted into the support substrate 501 through the openings in the patterned layer 502. The dopant ions will include a dopant material that will change the refractive index of the implanted region located within the openings in the patterned layer 502, and may include at least one of Al, P, F, Cl, P, or the gases N, Ar, or Kr. As described herein, the dopant ions provided in the ion implantation process are generated by a plasma formed by applying a high voltage radio frequency (RF) to the processing region of the plasma processing chamber. Subsequently, the ions dissociated from the plasma are biased towards the surface of the substrate 106 and implanted to a certain desired depth from the substrate surface. Once implanted, the dopant ions combine with portions of the material in the support substrate 501 and cause a change in the refractive index in these portions of the PGL substrate 106. In one embodiment, when the ion implantation process is performed within method 800, the support substrate 501 is placed on the substrate support pedestal of the plasma processing chamber, and gas flows into the interior of the plasma processing chamber and is ignited to generate a plasma. Subsequently, a bias is applied to the support substrate 501 to accelerate the dopant ions generated in the plasma towards the surface of the support substrate 501. As a result of the bias of the plasma and the support substrate 501, the dopant ions generated in the plasma are implanted into the support substrate 501 to form a part of the support substrate 501. An example of an ion implantation device is the Varian VIISTA® Trident available from Applied Materials, Inc. of Santa Clara, California.

[0086] In one embodiment, as Figure 5C shown, the ion implantation process employed in operation 804 modifies the exposed substrate portion 504 of the support substrate 501 to form a plurality of optical structures 110. On the other hand, the substrate region 512 protected by the patterned layer 502 is not modified by the ion implantation process. In one aspect, the modification by ion implantation depends on the ions (light ions or heavy ions) implanted in the PGL substrate 106. The ions implanted into the exposed portion 504 of the PGL substrate 106 can be modified to have an increase in refractive index or a decrease in refractive index. In one embodiment, the optical structures 110 formed by the ion implantation process include a refractive index higher than that of the PGL support substrate 501 and the protection region 512.

[0087] At operation 806, as Figure 5EAs shown, the patterned layer 502 is removed to form a substrate 106 that includes a support substrate 501 having alternating optical structures 110 and substrate regions 512 formed therein. Removing the patterned layer 502 may include removing a patterned hard mask or a patterned photoresist. Removing the patterned hard mask may include ion etching, reactive ion etching, or selective wet chemical etching. Removing the patterned photoresist may include using an ashing process or an etching process as described herein.

[0088] In some embodiments, it may be desirable to perform an annealing process on the PGL substrate of the substrate 501 to activate dopant species and remove any damage generated in the optical structures 110 during the implantation process and / or to better distribute the refractive index-altering dopant material implanted during operation 804 of method 800.

[0089] Although in this document Figures 5A to 5E the optical structures 110 shown are iconically depicted as having a generally square or rectangular cross-section, it is contemplated that in other examples, the optical structures may include tapered sidewalls and thus form a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top of the opening than at the bottom.

[0090] At operation 808, as Figure 5E shown, an encapsulation layer 520 is optionally disposed over the substrate 501 and the plurality of optical structures 110. The encapsulation layer 520 may be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 520 is made of a low refractive index material having a refractive index lower than that of the implanted portion of the support substrate 501. In some embodiments, the refractive index of the encapsulation layer 520 is between 1.3 and 1.9, such as between 1.40 and 1.44.

[0091] Thus, method 800 can be used to form optical structures 110 1 -110 N , which include the implanted portions of the support substrate 501. As Figure 5E shown, the PGL substrate 106 includes seven optical structures (i.e., optical structures 110 1 -110 7 ), which include exposed portions 504 formed within the support substrate 401.

[0092] Figure 9 Is a schematic cross-sectional view of a portion of a photon engine 103 mounted on a package substrate 101 formed along section line C-C according to one embodiment. As Figure 10 shown, Figure 9As shown, the photon engine 103 includes the bottom surface 106A of a photon glass layer substrate 106 disposed on the top surface 101A of a package substrate 101, where a plurality of optical structures 110 1 -110 N extend through the PGL substrate 106. In the illustrated embodiment, the plurality of optical structures 110 1 -110 N each are aligned in the X-Z plane of the PGL substrate 106. Although Figure 9 iconically the plurality of optical structures 110 1 -110 N are formed in a single column in a plane across the PGL substrate 106, other arrangements of the plurality of optical structures 110 1 -110 N may also be formed in the PGL substrate 106. For example, more than a single column of optical structures may be formed and vertically stacked. The stacked columns of optical structures may be formed by one or more processes described herein, such as the method Figures 3A to 8 described. The arrangement of the plurality of optical structures 110 1 -110 N is not intended to limit the scope of the disclosure provided herein.

[0093] Figure 10 FIG. is a schematic cross-sectional side view of a portion of a photon engine 103 mounted on a package substrate 101 formed by using cross-section line B-B in Figure 2A . As shown, the package substrate 101 includes a plurality of circuit traces 1002 that extend from a plurality of corresponding interconnect pads 1004 integrally formed in the top surface 101A of the package substrate 101. In one embodiment, the plurality of circuit traces 1002 form an interconnect 104 that electrically connects the photon engine 103 in contact with the plurality of interconnect pads 1004 to an electrical or optoelectronic chip 102. Alternatively, the plurality of circuit traces 1002 may electrically connect the photon engine 103 in contact with the plurality of interconnect pads 1004 to other integrated circuits disposed on the package substrate 101.

[0094] In some embodiments, a plurality of vias 1006 extend through a portion of the PGL substrate between the coupling surface 208 and the bottom surface 106A of the PGL substrate 106. When the photon engine 103 is mounted to the package substrate 101, in one embodiment, the plurality of vias 1006 are aligned with and placed in electrical contact with corresponding interconnect pads 1004 that are exposed on the top surface 101A of the package substrate 101 and are electrically connected to the photon engine 103 via a plurality of circuit traces 1002 formed in the package substrate 101. In another embodiment, the plurality of vias 1006 alternatively connect the photon engine 103 to one or more other integrated circuits (chips) embedded in or on the package substrate 101.

[0095] As Figure 10 shown, the SiPho chip 108 may be actively or passively mounted on the coupling surface 208 of the PGL substrate 106, wherein the side surface 108B of the SiPho chip 108 is "butt-coupled" to the end face 106B of the PGL substrate at the first interface 107. When the SiPho chip 108 is butt-coupled to the end face 106B of the PGL substrate 106, the ends of the waveguides 108A in the SiPho chip 108 are also butt-coupled to the corresponding ends of the optical structures 110 formed in the PGL substrate 106, such as the optical structure 110 3 . The coupling of the plurality of waveguides 108A to the plurality of optical structures 110 at the fourth interface 1008 may affect the loss of optical signals between the SiPho chip 108 and the PGL substrate 106. Therefore, in order to minimize the coupling loss, one or more of the above-mentioned fiducial marks 206 ( Figure 2B ) are used during the mounting of the SiPho chip 108 to assist in aligning and precisely placing the SiPho chip 108, thereby optimizing the butt-coupling of the plurality of waveguides 108A to the plurality of optical structures 110 1 -110 N at the fourth interface 1008 and minimizing the coupling loss.

[0096] To connect the SiPho chip 108 to the PGL substrate 106, the SiPho chip 108 further includes a plurality of solder connections 1012 that contact a plurality of solder balls 1010, where the plurality of solder balls 1010 are positioned between each of the plurality of solder connections 1012 and an end of a plurality of vias 1006 on the coupling surface 208. The plurality of solder balls 1010 electrically connect the SiPho chip 108 to the plurality of vias 1006 formed in the photon glass layer substrate 106. In one embodiment, a plurality of solder balls or other interconnect bumps, posts, or interconnect materials 1010 including planar hybrid bonding technology may be used to connect the plurality of solder connections 1012 to the plurality of vias 1006 that extend through the PGL substrate 106 to the substrate 101. In the illustrated embodiment, the plurality of solder balls 1010 and the plurality of vias 1006 connect the plurality of solder connections 1012 to a plurality of interconnect pads 1004 in the substrate 101, thereby electrically connecting the SiPho chip 108 to a plurality of circuit traces 1002 in the package substrate 101 that are connected to the plurality of interconnect pads 1004.

[0097] In one embodiment, the coupling surface 208 of the PGL substrate 106 may further include a plurality of recesses (not shown) for supporting each of the plurality of solder balls 1010 that connect the plurality of solder connections 1012 in the SiPho chip 108 and the plurality of vias 1006 in the PGL substrate 106. The plurality of recesses may be formed to allow the plurality of solder balls 1010 to expand when flattened such that the contact surface of the plurality of solder balls 1010 may be substantially flush with the coupling surface 208. The flattening of the plurality of solder balls 1010 on the coupling surface 208 helps to ensure the uniformity of mounting the SiPho chip 108 on the PGL substrate 106 and increases the contact reliability of the solder balls 1010 when contacting the solder connections 1012 in the SiPho chip 108.

[0098] Figure 10 Also included is a cross-sectional view of a portion of an optical fiber connector 112 according to one embodiment, the portion being coupled to a portion of the PGL substrate 106 at the interface 109. In the configuration, the optical fiber connector 112 may be removably connected to a portion of the photon engine 103 to allow the transmission of optical signals to and reception of optical signals from the optical structure 110 by using a "butt-coupling" connection configuration.

[0099] Figure 11 is a schematic cross-sectional side view of a portion of a photon engine 103 mounted on a package substrate 101 according to an alternative embodiment. In the illustrated embodiment, the SiPho chip 108 may be passively mounted on the photon glass layer substrate 106 in a second chip mounting region 1106 of the photon glass layer substrate 106. The second chip mounting region 1106 of the PGL substrate 106 further includes a plurality of optical structures 1101 -110 N The coupling portion 1102 of each of them, which extends along the coupling surface 1104 of the PGL substrate. When the SiPho chip 108 is mounted on the second chip mounting area 1106, a part of a plurality of waveguides 108A in the SiPho chip 108 is evanescently coupled to the surface of the corresponding coupling portion 1102 of each of the plurality of sub-optical structures 110 1 -110 N in the PGL substrate 106. Evanescent coupling is achieved when two optical waveguides are positioned closely together such that the evanescent field generated by one waveguide reaches the other waveguide before any substantial attenuation of the evanescent field is experienced. The evanescent coupling of the plurality of waveguides 108A to the plurality of optical structures 110 allows optical signals to be transmitted between the coupled waveguides.

[0100] In one embodiment, the evanescent coupling of the waveguides can be formed as a directional coupler, where the evanescent mode of one waveguide overlaps with the mode of a second waveguide. When the evanescent modes of the waveguides overlap, the evanescent fields generated by the respective waveguides also overlap such that the evanescent field generated by one waveguide can excite a wave in the other waveguide. Thus, in one aspect, the coupling strength between the plurality of waveguides 108A and the plurality of optical structures 110 can be sensitive to the distance between the waveguides 108A and the optical structures 110 and / or the length of the coupling portion 1102. Accordingly, the coupling portion 1102 of the waveguide 108A and the corresponding contact portion are sized and formed to optimize the coupling and minimize the coupling loss.

[0101] Mounting the SiPho chip 108 on the substrate 106 in the chip mounting area 1106 of the substrate 106 further includes connecting a plurality of solder connections 1012 in the SiPho chip 108 to a plurality of vias 1006 in the PGL substrate 106 using a plurality of solder balls 1010. The plurality of solder balls 1010 can be positioned on the coupling surface 208 adjacent to the plurality of optical structures 110 1 -110 N of the coupling portion 1102 and aligned between each respective solder connection 1012 and via 1006. The plurality of solder balls 1010 can be sized such that when the plurality of solder balls 1010 are flattened due to contact with the SiPho chip 108 mounted on the PGL substrate 106, the plurality of solder balls 1010 are flattened to the same level as the plurality of optical structures 110 1 -110 NThe height of the coupling portion 1102 is substantially the same height. In the illustrated embodiment, the plurality of solder balls 1010 and the plurality of interconnect pads 1004 that contact the plurality of vias 1006 electrically connect the SiPho chip 108 to the plurality of circuit traces 1002 in the package substrate 101. Additionally, one or more pedestal structures 1015 may be used to position, support, and / or assist in aligning the SiPho chip 108 within the chip mounting area 204. In one example, the pedestal structure 1015 ( Figure 10 ) is formed to help set the vertical alignment of the waveguide 108A with the optical structure 110. In some embodiments, as Figure 10 shown, the PGL substrate 106 includes one or more pedestal structures 1015 that are configured to support the SiPho chip 108 in a direction (e.g., the Z direction) that is substantially perpendicular to a plane (e.g., the X-Y plane) parallel to the plane in which the optical structure 110 1 -110 N extends.

[0102] Figure 12 FIG. is a schematic cross-sectional side view of the fiber optic connector 112 portion of the photon engine 103 according to one embodiment. Generally, the fiber optic connector 112 is used to removably connect an external fiber optic cable 120 to the photon engine 103. The plurality of optical fibers 112A of the fiber optic connector 112 transmit optical signals to and from the fiber optic cable 120 inserted into the fiber optic connector 112. The fiber optic connector 112 is configured to allow an external optical cable 120 to be attached to the optical input / output of the photon engine 103 without actively aligning the fiber optic cable 120 to the photon engine 103 on a per-core basis. Thus, the fiber optic connector 120 can be formed and configured to be interoperable with a variety of different fiber optic cable 120 assemblies and standards.

[0103] As Figure 12 shown, the light transmitted along the plurality of optical fibers 112A is directed through a lens assembly to the plurality of optical structures 110 on the PGL substrate 106 1 -110 N, for subsequent transmission to and through the photon engine 103. The lens assembly includes a first lens 112B and a third lens 112C formed on the fiber optic connector 112, and a second lens 1202 formed on the substrate 106. In the illustrated embodiment, light from the optical cable 120 travels along the optical fiber 112A toward the first lens 112B formed near the end of the optical fiber 112A. The first lens 112B directs the light traveling along the optical fiber 112A toward the second lens 1202 on the PGL substrate 106. The second lens 1202 on the PGL substrate 106 then reflects and redirects the light back to the third lens 112C on the fiber optic connector 112. The third lens 112C finally reflects the light to and redirects it to the optical structure 110 on the PGL substrate 106 for subsequent transmission through the photon engine 103.

[0104] In summary, embodiments herein relate to optical silicon photon devices and methods for manufacturing optical silicon photon devices. The methods described herein enable the mass fabrication and production of optical silicon photon devices having a plurality of optical structures formed on a photon glass layer substrate. The optical silicon photon device further includes a silicon photon chip mounted on the photon glass layer substrate and connected to the plurality of optical structures. The plurality of optical structures optically connect the silicon photon chip to a fiber optic connector configured for connection to an external optical fiber and operative to propagate optical signals between the fiber optic connector and the silicon photon chip.

[0105] While the foregoing is directed to various embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. An electronic and photonic device, comprising: a substrate having an optical transceiver chip mounting area configured to receive an optical transceiver chip and a fiber optic connector area configured to couple to a fiber optic connector, wherein the substrate comprises: a plurality of optical structures; and each of the plurality of optical structures is operable to transmit light between a first end and a second end of each of the plurality of optical structures, the first end being configured to receive light transmitted from a plurality of waveguides of the optical transceiver chip or transmit light to the waveguides of the optical transceiver chip, and the second end being configured to receive light transmitted from a plurality of optical fibers of the fiber optic connector or transmit light to the optical fibers of the fiber optic connector.

2. The electronic and photonic device according to claim 1, wherein the optical structure has a first refractive index and is separated by a second material having a second refractive index.

3. The electronic and photonic device according to claim 1, further comprising an optical transceiver chip, the optical transceiver chip being connected to the substrate by docking and coupling the plurality of waveguides of the optical transceiver chip to the plurality of optical structures.

4. The electronic and photonic device according to claim 1, further comprising an optical transceiver chip, the optical transceiver chip being connected to the substrate by evanescently coupling the plurality of waveguides of the optical transceiver chip to the plurality of optical structures.

5. The electronic and photonic device according to claim 1, wherein each of the plurality of optical structures comprises a waveguide extending from a first edge of the substrate to a second edge and extending in one or more directions parallel to a first plane.

6. The electronic and photonic device according to claim 5, wherein the plurality of waveguides have a cross-sectional area that changes along their length, the length extending between the first edge and the second edge.

7. The electronic and photonic device according to claim 1, wherein each of the plurality of optical structures comprises a plurality of waveguides extending from a first edge of the substrate to a second edge, and each of the plurality of waveguides comprises: a first end extending from the first edge of the substrate, wherein the first end of the waveguide has a first cross-sectional dimension; and a second end extending from the second edge of the substrate, wherein the second end of the waveguide has a second cross-sectional dimension, and the second cross-sectional dimension is greater than the first cross-sectional dimension.

8. The electronic and photonic device according to claim 7, wherein the first cross-sectional dimension comprises a height dimension of approximately 1 micron, and wherein the second cross-sectional dimension comprises a height dimension of approximately 9 microns.

9. The electronic and photonic device according to claim 1, wherein the optical transceiver chip mounting area further comprises a via array configured to be electrically connected to one or more contacts formed on the optical transceiver chip.

10. The electronic and photonic device according to claim 9, further comprising: Multiple solder balls for electrically connecting the optical transceiver chip to a plurality of vias extending through the substrate. Wherein the plurality of optical structures include waveguides that extend from the first end to the second end and are parallel to a first plane, and the substrate further includes one or more support structures configured to support the optical transceiver chip in a first direction that is substantially perpendicular to the first plane.

11. The electronic and photonic device of claim 1, further comprising a lens assembly formed between the substrate and the optical connector, wherein the lens assembly is operable to transmit light between the plurality of optical fibers of the fiber optic connector and the plurality of optical structures.

12. The electronic and photonic device of claim 1, further comprising a plurality of electronic and photonic devices selected from the group consisting of an electronic PHY chip, an optoelectronic chip, or a SiPho chip.

13. A co-packaged electronic and photonic device comprising: A packaging substrate; One or more electrical or optoelectronic integrated circuits mounted on the packaging substrate; One or more electronic and photonic devices mounted on the packaging substrate, wherein each of the one or more electronic and photonic devices is connected to one or more of the electrical or optoelectronic integrated circuits; Wherein each of the one or more electronic and photonic devices includes: A support substrate having an optical transceiver chip mounting area configured to receive an optical transceiver chip and a fiber optic connector area configured to couple to a fiber optic connector, and wherein the support substrate includes a plurality of optical structures formed within the support substrate and operable to transmit light between a first end and a second end of the support substrate.

14. The co-packaged electronic and photonic device of claim 13, wherein the optical structures have a first refractive index and are separated by a second material having a second refractive index.

15. The co-packaged electronic and photonic device of claim 13, further comprising an optical transceiver chip connected to the support substrate by butt-coupling the plurality of waveguides of the optical transceiver chip to the plurality of optical structures.

16. The co-packaged electronic and photonic device of claim 13, further comprising an optical transceiver chip connected to the support substrate by evanescently coupling the plurality of waveguides of the optical transceiver chip to the plurality of optical structures.

17. The co-packaged electronic and photonic device of claim 13, further comprising an optical transceiver chip that communicates with the optical structures and communicates with a plurality of metal traces connected to the one or more electrical or optoelectronic integrated circuits.

18. The co-packaged electronic and photonic device of claim 13, wherein each of the plurality of optical structures extends parallel to a first plane from the first end to the second end.

19. The co-packaged electronic and photonic device according to claim 13, wherein one or more of the optical structures have an optical transmission region having a cross-sectional area that varies along its length, the length extending between the first end and the second end.

20. The co-packaged electronic and photonic device according to claim 13, wherein each of the one or more electronic and photonic devices is configured to transmit signals between an optical cable of the support substrate connected to the one or more electronic and photonic devices and one or more electrical or optoelectronic integrated circuits mounted on the package substrate.

Images