Phase detection simulation circuit, method and device

Abstract

The invention relates to a phase detection simulation circuit, method and device, and the circuit comprises a random signal generation module which is used for generating a random signal; the signal selection module is used for receiving the first simulation delay signal, the second simulation delay signal and the random signal, and selecting the second simulation delay signal or the random signal as a selection output signal according to a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; the sampling simulation register is used for outputting a sampling simulation result signal according to the first simulation delay signal and the selection output signal; wherein the preset threshold range is used for representing the establishment retention time of the sampling register simulated by the sampling simulation register. According to the invention, the simulation of the sampling register under the metastable state is realized, the integrity and reliability of the simulation result are improved, and the reliability of the simulation phase detection circuit on the prediction result of whether the simulation phase detection circuit meets the requirement of the design target is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and particularly to a phase detection simulation circuit, method and device. Background Art

[0002] The phase detection circuit plays an important role in an integrated circuit, which is related to signal synchronization and demodulation, and has an important impact on the stability and reliability of the performance of the integrated circuit.

[0003] In the phase detection circuit, the sampling register for signal comparison has metastable states, so the output of the sampling register will quickly jitter between high and low levels. And this situation is difficult to achieve in the pre-simulation stage of circuit design, which results in the function of the phase detection related circuit being difficult to be verified more realistically by means of equivalent simulation. Summary of the Invention

[0004] In view of this, the present disclosure provides a phase detection simulation circuit, method and device to enable the phase detection simulation circuit to simulate metastable states and help improve the reliability of the pre-simulation results of the integrated circuit.

[0005] The technical solution of the present disclosure is implemented as follows: According to one aspect of the embodiments of the present disclosure, a phase detection simulation circuit is provided, including: A random signal generation module for generating a random signal; A signal selection module for receiving a first simulation delay signal, a second simulation delay signal and the random signal, and selecting one of the second simulation delay signal and the random signal as a selection output signal according to the comparison result between the phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; A sampling simulation register, the clock signal terminal of which is used to receive the first simulation delay signal, the input terminal of which is used to receive the selection output signal, and the sampling simulation register outputs a sampling simulation result signal at its output terminal according to the first simulation delay signal and the selection output signal, and the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal; Wherein, the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0006] In a possible implementation manner, the signal selection module includes: A phase counting unit, configured to receive the first simulation delay signal and the second simulation delay signal, obtain a first count value at the transition edge moment of the first simulation delay signal, and obtain a second count value at the transition edge moment of the second simulation delay signal, wherein the first count value is used to represent the transition edge moment of the first simulation delay signal, and the second count value is used to represent the transition edge moment of the second simulation delay signal; A phase difference comparison unit, configured to obtain the comparison result according to the first count value, the second count value and the preset threshold range; A signal selection unit, configured to select one of the second simulation delay signal and the random signal as the selected output signal according to the comparison result.

[0007] In a possible implementation manner, the phase counting unit includes: A counting unit, configured to perform counting associated with time; A capture unit, configured to receive the first simulation delay signal and the second simulation delay signal, and capture the first count value generated by the counting unit at the transition edge moment of the first simulation delay signal, and capture the second count value generated by the counting unit at the transition edge moment of the second simulation delay signal.

[0008] In a possible implementation manner, the phase difference comparison unit includes: A phase difference calculation unit, configured to obtain the phase difference according to the first count value and the second count value; A comparison unit, configured to compare the phase difference with the preset threshold range to obtain the comparison result.

[0009] In a possible implementation manner, the phase detection simulation circuit further includes: A first signal simulation delay circuit, configured to receive a first simulation signal and perform simulation delay on the first simulation signal to obtain the first simulation delay signal; A second signal simulation delay circuit, configured to receive a second simulation signal and perform simulation delay on the second simulation signal to obtain the second simulation delay signal.

[0010] In a possible implementation manner, the first signal simulation delay circuit includes: A first simulation delay unit, configured to receive the first simulation signal and perform simulation delay on the first simulation signal to obtain at least one first delay candidate signal; The first simulation multiplexing unit is configured to receive the at least one first delay candidate signal and a first selection signal, and select one of the at least one first delay candidate signals as the first simulation delay signal according to the first selection signal; The second signal simulation delay circuit includes: A second simulation delay unit configured to receive the second simulation signal and perform simulation delay on the second simulation signal to obtain at least one second delay candidate signal; A second simulation multiplexing unit is configured to receive the at least one second delay candidate signal and a second selection signal, and select one of the at least one second delay candidate signals as the second simulation delay signal according to the second selection signal.

[0011] In a possible implementation manner, the first simulation delay unit includes: At least one first simulation delay register cascaded on the path of delaying the first simulation signal, wherein the input end of the first simulation delay register receives the signal to be delayed, and the output end of the first simulation delay register generates the delayed signal. When the number of the first simulation delay registers is at least two, the first simulation signal obtains at least two first delay candidate signals with different delays through the pipelined delay of at least two first simulation delay registers; The second simulation delay unit includes: At least one second simulation delay register cascaded on the path of delaying the second simulation signal, wherein the input end of the second simulation delay register receives the signal to be delayed, and the output end of the second simulation delay register generates the delayed signal. When the number of the second simulation delay registers is at least two, the second simulation signal obtains at least two second delay candidate signals with different delays through the pipelined delay of at least two second simulation delay registers.

[0012] According to another aspect of the embodiments of the present disclosure, a phase detection simulation method is provided, including: Obtaining a first simulation delay signal, a second simulation delay signal, and a random signal; Selecting one of the second simulation delay signal and the random signal as a selection output signal according to a comparison result between a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; Receive the first simulation delay signal at the clock signal terminal of the sampling simulation register, and receive the selected output signal at the input terminal of the sampling simulation register, and obtain a sampling simulation result signal at the output terminal of the sampling simulation register, where the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal; Wherein, the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0013] In a possible implementation manner, the selecting, as the selected output signal, one of the second simulation delay signal and the random signal according to a comparison result between a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range includes: When the comparison result is that the phase difference is outside the preset threshold range, using the second simulation delay signal as the selected output signal; When the comparison result is that the phase difference is within the preset threshold range, using the random signal as the selected output signal.

[0014] In a possible implementation manner, the phase detection simulation method further includes: Obtain a first simulation signal and a second simulation signal; Perform simulation delay on the first simulation signal to obtain the first simulation delay signal; Perform simulation delay on the second simulation signal to obtain the second simulation delay signal.

[0015] According to another aspect of the embodiments of the present disclosure, there is provided a phase detection simulation device, including: A signal receiving module, configured to receive a first simulation delay signal, a second simulation delay signal, and a random signal; A selection module, configured to select, as the selected output signal, one of the second simulation delay signal and the random signal according to a comparison result between a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; A phase relationship determination module, configured to receive the first simulation delay signal at the clock signal terminal of the sampling simulation register, and receive the selected output signal at the input terminal of the sampling simulation register, and obtain a sampling simulation result signal at the output terminal of the sampling simulation register, where the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal; Wherein, the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0016] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, including: a processor; a memory for storing executable instructions of the processor; wherein, the processor is configured to execute the executable instructions to implement the phase detection simulation method described in any one of the above.

[0017] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the phase detection simulation method described in any one of the above.

[0018] As can be seen from the above solutions, for the phase detection simulation circuit, method and device of the present disclosure, by comparing the phase difference between the first simulation delay signal and the second simulation delay signal with a preset threshold range, it is determined whether the transition edge of the second simulation delay signal falls within the "setup hold time" of the sampling simulation register. And according to the determination result of whether the transition edge of the second simulation delay signal falls within the "setup hold time" of the sampling simulation register, the second simulation delay signal or a random signal is selected to be given to the sampling simulation register. Furthermore, the sampling simulation register outputs a sampling simulation result signal at its output end according to the first simulation delay signal received at its clock signal end and the selected output signal (the second simulation delay signal or the random signal) received at its input end. Among them, a random number is used to replace the input signal of the sampling simulation register within the "setup hold time" of the sampling simulation register. The value of the random number may be the same as or different from the second simulation delay signal. In this way, the input signal within the setup hold time of the sampling simulation register may be either correct or incorrect. Thus, the output signal of the sampling simulation register may be either correct or incorrect, thereby simulating the uncertainty of the output signal result after the metastability ends due to the existence of metastability in the sampling register, thus realizing the simulation of the sampling register in the case of containing metastability, equivalent to the sampling situation of the sampling register, solving the simulation problem of the phase detection circuit in digital circuits, helping to improve the integrity and reliability of the simulation result of the phase detection simulation circuit, and helping to improve the reliability of the prediction result of whether the phase detection circuit simulated by the phase detection simulation circuit meets the design target requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic structural diagram of a phase detection circuit in the related art; Figure 2 is a schematic structural diagram of a phase detection simulation circuit in the related art; Figure 3It is a schematic structural diagram of a phase detection simulation circuit shown according to a schematic embodiment; Figure 4 It is a schematic structural diagram of a second phase detection simulation circuit shown according to a schematic embodiment; Figure 5 It is a schematic flowchart of a phase detection simulation method shown according to a schematic embodiment; Figure 6 It is a schematic flowchart of obtaining a simulation delay signal shown according to a schematic embodiment; Figure 7 It is a schematic diagram of a phase detection simulation system shown according to a schematic embodiment; Figure 8 It is a schematic structural diagram of a phase detection simulation device shown according to a schematic embodiment; Figure 9 It is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the following takes examples with reference to the accompanying drawings and further elaborates on the present disclosure in detail.

[0021] It should be noted that the terms "first", "second", etc. in the description and claims of the present disclosure and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0022] Figure 1 It is a schematic structural diagram of a phase detection circuit in the related art. As Figure 1 shown, the phase detection circuit includes a first delay circuit 10, a second delay circuit 20, and a sampling register 30. When using this phase detection circuit to perform phase detection on a first signal s1 and a second signal s2, the first signal s1 and the second signal s2 are respectively input into the first delay circuit 10 and the second delay circuit 20. The first delay circuit 10 and the second delay circuit 20 respectively delay the first signal s1 and the second signal s2 under the control of a first delay control signal cs1 and a second delay control signal cs2 to obtain a first delay signal s11 and a second delay signal s21. The output ends of the first delay circuit 10 and the second delay circuit 20 are respectively coupled to the clock signal terminal clk and the input terminal D of the sampling register 30, and a sampling result signal s_out is generated at the output terminal Q of the sampling register 30. Thus, the phase relationship between the first signal s1 and the second signal s2 can be judged according to the sampling result signal s_out. Among them, the sampling register 30 can be a D flip-flop.

[0023] Figure 2It is a schematic structural diagram of a phase detection simulation circuit in the related art. Figure 2 The structure shown is for Figure 1 the simulation circuit of the phase detection circuit shown in the design stage. Figure 2 The structure shown is a virtual circuit implemented by computer program code, used to verify the correctness of the phase detection circuit. As Figure 2 shown, the phase detection simulation circuit includes a first signal simulation delay circuit 11, a second signal simulation delay circuit 21, and a sampling simulation register 31. The first signal simulation delay circuit 11 receives a first simulation signal ss1, delays the first simulation signal ss1 through the beat buffering of the simulation register therein, and obtains a first simulation delay signal ss11 under the control of a first simulation delay control signal scs1. The second signal simulation delay circuit 21 receives a second simulation signal ss2, delays the second simulation signal ss2 through the beat buffering of the simulation register therein, and obtains a second simulation delay signal ss21 under the control of a second simulation delay control signal scs2. The output end of the first signal simulation delay circuit 11 and the output end of the second signal simulation delay circuit 21 are respectively coupled to the clock signal end clk and the input end D of the sampling simulation register 31, and a sampling simulation result signal ss_out is generated at the output end Q of the sampling simulation register 31. The phase relationship between the first simulation signal ss1 and the second simulation signal ss2 can be judged according to the sampling simulation result signal ss_out.

[0024] Among them, the first signal simulation delay circuit 11 is a simulation circuit for simulating the first delay circuit 10, the second signal simulation delay circuit 21 is a simulation circuit for simulating the second delay circuit 20, the sampling simulation register 31 is a simulation circuit for simulating the sampling register 30, the first simulation signal ss1 is a simulation signal for simulating the first signal s1, the second simulation signal ss2 is a simulation signal for simulating the second signal s2, the first simulation delay control signal scs1 is a simulation signal for simulating the first delay control signal cs1, the second simulation delay control signal scs2 is a simulation signal for simulating the second delay control signal cs2, the first simulation delay signal ss11 is a simulation signal for simulating the first delay signal s11, the second simulation delay signal ss21 is a simulation signal for simulating the second delay signal s21, and the sampling simulation result signal ss_out is a simulation signal for simulating the sampling result signal s_out.

[0025] Although the phase detection simulation circuit can perform pre-fabrication simulation on the phase detection circuit to predict the accuracy of the phase detection circuit, that is, to predict whether the designed phase detection circuit meets the requirements of the design goal, however, restricted by the objective behavior of semiconductor devices within the integrated circuit under physical conditions, it is difficult for the phase detection simulation circuit to fully predict all the behaviors of the phase detection circuit. For example, the impact of the metastability of the sampling register on the signal is difficult to simulate and predict from the phase detection simulation circuit.

[0026] In the related technologies of integrated circuits, the CMOS (Complementary Metal-Oxide-Semiconductor) process is used for device preparation. The register consists of multiple semiconductor devices. Due to the fact that the charging and discharging processes of semiconductor devices during operation require time, and there are also time constraints for signal transmission inside the register, for this reason, the register has a metastable state. Metastability refers to the state where the register cannot reach a confirmable state within a specified time period. When the register is in the metastable state, its output terminal will oscillate for a long time, and the oscillating output level will propagate in the signal channel and affect the circuit function.

[0027] If the setup and hold times of the register are not met in terms of timing, metastability will occur. Therefore, in the timing design, the requirements for the setup time and hold time of the register need to be satisfied. Among them, the setup time (Tsu, setup time) refers to the time during which the level state of the input signal remains stable before the rising edge of the clock signal of the register arrives. If the setup time is insufficient, the level state of the input signal will not be stably latched into the register at the rising edge of the clock signal. The hold time (Td, hold time) refers to the time during which the level state of the input signal remains stable after the rising edge of the clock signal of the register arrives. If the hold time is insufficient, the level state of the input signal cannot be stably latched into the register either.

[0028] Due to the existence of register metastability, the phase detection simulation circuit in the related technologies cannot simulate the situation where the sampling register is within the setup and hold times during the digital circuit simulation and field programmable gate array (FPGA) verification stages, that is, the situation of the phase difference between the detected signals (such as the first delay signal s11 and the second delay signal s21) within the setup and hold times of the sampling register, thereby resulting in the inability to truly verify the function of the phase detection circuit through the equivalent simulation circuit. Among them, in the embodiments of the present disclosure, the setup and hold time refers to the period of time between the start moment of the setup time and the end moment of the hold time.

[0029] In view of this, embodiments of the present disclosure provide a phase detection simulation circuit, method and device to implement the simulation of the metastable behavior of a sampling register, thereby helping to improve the integrity and reliability of the simulation results of the phase detection simulation circuit, and helping to improve the reliability of the prediction results of whether the phase detection circuit simulated by the phase detection simulation circuit meets the requirements of the design target.

[0030] Figure 3 is a schematic structural diagram of a phase detection simulation circuit shown according to an exemplary embodiment, as Figure 3 shown, the phase detection simulation circuit mainly includes a random signal generation module 41, a signal selection module 42 and a sampling simulation register 31. Among them, the random signal generation module 41 is used to generate a random signal rs. The signal selection module 42 is logically coupled to the random signal generation module 41. The signal selection module 42 is used to receive a first simulation delay signal ss11, a second simulation delay signal ss21 and the random signal rs, and select one of the second simulation delay signal ss21 and the random signal rs as the selected output signal sos according to the comparison result cr between the phase difference pd between the first simulation delay signal ss11 and the second simulation delay signal ss21 and a preset threshold range. The input terminal D of the sampling simulation register 31 is logically coupled to the signal selection module 42. The clock signal terminal clk of the sampling simulation register 31 is used to receive the first simulation delay signal ss11. The input terminal D of the sampling simulation register 31 is used to receive the selected output signal sos. The sampling simulation register 31 outputs a sampling simulation result signal ss_out at its output terminal Q according to the first simulation delay signal ss11 and the selected output signal sos. The sampling simulation result signal ss_out is used to characterize the phase relationship between the first simulation delay signal ss11 and the second simulation delay signal ss21. Among them, the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register 31.

[0031] In the phase detection simulation circuit of the embodiments of the present disclosure, the comparison result cr between the phase difference pd between the first simulation delay signal ss11 and the second simulation delay signal ss21 and the preset threshold range characterizes whether the phase difference between the first delay signal s11 and the second delay signal s21 to be simulated falls within the setup and hold time of the sampling register. Although there is no metastable state in the sampling simulation register 31 itself, however, based on the truth table relationship between the input signal and the output signal of the register, the randomness of the input signal D of the sampling simulation register 31 will directly lead to the randomness of the sampling simulation result signal ss_out of the output of the sampling simulation register 31. Therefore, in the phase detection simulation circuit of the embodiments of the present disclosure, the signal selection module 42 determines whether the second simulation delay signal ss21 (the edge of the signal) falls within the "setup and hold time" of the sampling simulation register 31 by using the comparison between the phase difference pd between the first simulation delay signal ss11 and the second simulation delay signal ss21 and the preset threshold range, and selects the second simulation delay signal ss21 or the random signal rs for the sampling simulation register 31 according to the determination result of whether the second simulation delay signal ss21 (the edge of the signal) falls within the "setup and hold time" of the sampling simulation register 31. Furthermore, the sampling simulation register 31 outputs the sampling simulation result signal ss_out at its output terminal Q according to the first simulation delay signal ss11 received by its clock signal terminal clk and the selected output signal sos (the second simulation delay signal ss21 or the random signal rs) received by its input terminal D, thereby realizing the simulation of the random output result of the sampling register 30 after the metastable state ends. Since the output signal of the sampling register 30 itself after the metastable state ends is randomly uncertain, even though there may be a difference between the sampling simulation result signal ss_out obtained by the sampling simulation register 31 according to the random signal rs each time in the embodiments of the present disclosure and the random output result of the sampling register 30 after the metastable state ends each time, however, from a statistical perspective, this difference does not affect the reliability of the simulation statistical result corresponding to the statistical result of the random output of the sampling register 30 after multiple metastable states end.

[0032] In the illustrative embodiment, the sampling simulation register 31 may be implemented by a simulated D flip-flop.

[0033] Continue to refer to Figure 3As shown, in the illustrative embodiment, the signal selection module 42 may include a phase counting unit 421, a phase difference comparison unit 422, and a signal selection unit 423. Among them, the phase counting unit 421 is configured to receive a first simulation delay signal ss11 and a second simulation delay signal ss21, obtain a first count value cv1 at the transition edge of the first simulation delay signal ss11, and obtain a second count value cv2 at the transition edge of the second simulation delay signal ss21. Herein, the first count value cv1 is used to represent the transition edge time of the first simulation delay signal ss11, and the second count value cv2 is used to represent the transition edge time of the second simulation delay signal ss21; the phase difference comparison unit 422 is logically coupled to the phase counting unit 421 and is configured to obtain a comparison result cr according to the first count value cv1, the second count value cv2, and a preset threshold range; the signal selection unit 423 is logically coupled to the phase difference comparison unit 422, the random signal generation module 41, and the sampling simulation register 31, and the signal selection unit 423 is configured to select one of the second simulation delay signal ss21 and the random signal rs as the selected output signal sos according to the comparison result cr.

[0034] In the illustrative embodiment, the signal selection unit 423 may adopt a multiplexer. Herein, the second simulation delay signal ss21 and the random signal rs are two input signals of the multiplexer, the comparison result cr is the gating control signal of the multiplexer, and the selected output signal sos is the output signal of the multiplexer. Among them, the multiplexer is a simulation device.

[0035] Continue to refer to Figure 3 As shown, in order to obtain the first count value cv1 at the transition edge of the first simulation delay signal ss11 and the second count value cv2 at the transition edge of the second simulation delay signal ss21, in the illustrative embodiment, the phase counting unit 421 includes a counting unit 4211 and a capture unit 4212. Among them, the counting unit 4211 is configured to perform counting associated with time. For example, as time goes by, the count value of the counting unit 4211 continuously increases. In the illustrative embodiment, a relatively high-frequency clock signal may be used as a control signal to perform the counting of the counting unit 4211. The capture unit 4212 is logically coupled to the counting unit 4211. The capture unit 4212 is configured to receive the first simulation delay signal ss11 and the second simulation delay signal ss21, and capture the first count value cv1 generated by the counting unit 4211 at the transition edge of the first simulation delay signal ss11, and capture the second count value cv2 generated by the counting unit 4211 at the transition edge of the second simulation delay signal ss21.

[0036] Continue to refer to Figure 3As shown, in the illustrative embodiment, in order to obtain the comparison result cr, the phase difference comparison unit 422 may include a phase difference calculation unit 4221 and a comparison unit 4222. Among them, the phase difference calculation unit 4221 is logically coupled to the phase counting unit 421. Further, the phase difference calculation unit 4221 is logically coupled to the capture unit 4212. The phase difference calculation unit 4221 is configured to obtain the phase difference pd according to the first count value cv1 and the second count value cv2. The comparison unit 4222 is logically coupled to the phase difference calculation unit 4221 and the signal selection unit 423. The comparison unit 4222 is configured to compare the phase difference pd with a preset threshold range to obtain the comparison result cr.

[0037] In the illustrative embodiment, the preset threshold range may include a range within the first threshold and the second threshold. Among them, the first threshold is a negative value, and the second threshold is a positive value. The phase difference pd is the difference between the first count value cv1 and the second count value cv2. The phase difference pd being greater than or equal to the first threshold and less than or equal to the second threshold (i.e., the phase difference pd is within the preset threshold range) indicates that the transition edge of the second simulation delay signal ss21 falls within the "setup hold time" of the sampling simulation register 31. The phase difference pd being less than the first threshold or greater than the second threshold (i.e., the phase difference pd is outside the preset threshold range) indicates that the transition edge of the second simulation delay signal ss21 is outside the "setup hold time" of the sampling simulation register 31.

[0038] In the illustrative embodiment, when the comparison result cr is that the phase difference pd is outside the preset threshold range, the second simulation delay signal ss21 is used as the selected output signal sos; when the comparison result cr is that the phase difference pd is within the preset threshold range, the random signal rs is used as the selected output signal sos.

[0039] In the illustrative embodiment, when the phase difference pd is outside the preset threshold range, the value of the comparison result cr may be 1, and when the phase difference pd is within the preset threshold range, the value of the comparison result cr may be 0; or, when the phase difference pd is outside the preset threshold range, the value of the comparison result cr may be 0, and when the phase difference pd is within the preset threshold range, the value of the comparison result cr may be 1.

[0040] In the illustrative embodiment, the random signal generation module 41 may be implemented by a variety of simulation circuits that can generate a random signal rs of 0 or 1. For example, a simulation model of a linear feedback shift register may be used as the random signal generation module 41 to generate the random signal rs.

[0041] In a schematic embodiment, it can be combined with a phase detection simulation circuit of the related art. The first simulation delay signal ss11 and the second simulation delay signal ss21 can be obtained by delaying the first simulation signal ss1 and the second simulation signal ss2. Figure 4 is a schematic structural diagram of a second phase detection simulation circuit shown according to a schematic embodiment. As Figure 4 shown, on the basis of the structure of the phase detection simulation circuit embodiment shown in Figure 3 this phase detection simulation circuit further includes a first signal simulation delay circuit 11 and a second signal simulation delay circuit 21. Among them, the first signal simulation delay circuit 11 is logically coupled to the signal selection module 42. The first signal simulation delay circuit 11 is also logically coupled to the clock signal terminal clk of the sampling simulation register 31. The first signal simulation delay circuit 11 is configured to receive a first simulation signal ss1 and perform simulation delay on the first simulation signal ss1 to obtain a first simulation delay signal ss11. The second signal simulation delay circuit 21 is logically coupled to the signal selection module 42. The second signal simulation delay circuit 21 is configured to receive a second simulation signal ss2 and perform simulation delay on the second simulation signal ss2 to obtain a second simulation delay signal ss21.

[0042] It should be noted that Figure 4 in the phase detection simulation circuit embodiment shown, the structure and function of the signal selection module 42 are the same as those of the signal selection module 42 shown in Figure 3 this.

[0043] Continuing to refer to Figure 4 shown, in a schematic embodiment, the first signal simulation delay circuit 11 includes a first simulation delay unit 111 and a first simulation multiplexing unit 112. Among them, the first simulation delay unit 111 is configured to receive the first simulation signal ss1 and perform simulation delay on the first simulation signal ss1 to obtain at least one first delay candidate signal. For example, Figure 4 shown, the at least one first delay candidate signal includes a first delay candidate signal dss1_1, a first delay candidate signal dss1_2,..., a first delay candidate signal dss1_N. The first simulation multiplexing unit 112 is logically coupled to the first simulation delay unit 111, the signal selection module 42, and the sampling simulation register 31. The first simulation multiplexing unit 112 is configured to receive the at least one first delay candidate signal and a first selection signal s_s1, and select one of the at least one first delay candidate signals as the first simulation delay signal ss11 according to the first selection signal s_s1. For example, Figure 4 shown, the first simulation multiplexing unit 112 selects one of the first delay candidate signals dss1_1 to the first delay candidate signal dss1_N as the first simulation delay signal ss11.

[0044] In a schematic embodiment, the second signal simulation delay circuit 21 includes a second simulation delay unit 211 and a second simulation multiplexing unit 212. Among them, the second simulation delay unit 211 is configured to receive a second simulation signal ss2, and perform simulation delay on the second simulation signal ss2 to obtain at least one second delay candidate signal. For example Figure 4 as shown, the at least one second delay candidate signal includes a second delay candidate signal dss2_1, a second delay candidate signal dss2_2,..., a second delay candidate signal dss2_M. The second simulation multiplexing unit 212 is logically coupled to the second simulation delay unit 211 and the signal selection module 42. The second simulation multiplexing unit 212 is configured to receive the at least one second delay candidate signal and a second selection signal s_s2, and select one of the at least one second delay candidate signals as the second simulation delay signal ss21 according to the second selection signal s_s2. For example Figure 4 as shown, the second simulation multiplexing unit 212 selects one of the second delay candidate signals dss2_1 to dss2_M as the second simulation delay signal ss21.

[0045] In a schematic embodiment, the first simulation delay unit 111 may include at least one first simulation delay register that is logically cascaded on the path for delaying the first simulation signal ss1. Among them, the input terminal D of each first simulation delay register receives the signal to be delayed, and the output terminal Q of each first simulation delay register generates the delayed signal. When the number of the first simulation delay registers is at least two, the first simulation signal ss1 obtains at least two first delay candidate signals with different delays through the pipelined delay of at least two first simulation delay registers. For example Figure 4 as shown, the first simulation delay unit 111 includes N first simulation delay registers that are logically cascaded on the path for delaying the first simulation signal ss1. For example, N≥3, including a first simulation delay register SDR1_1, a first simulation delay register SDR1_2,..., a first simulation delay register SDR1_N. Among them, the input terminal D of the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N receives the signal to be delayed, the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N generate the delayed signal, and the first simulation signal ss1 obtains the first delay candidate signals dss1_1 to dss1_N with different delays through the pipelined delay of the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N.

[0046] In a schematic embodiment, the second simulation delay unit 211 may include at least one second simulation delay register logically cascaded in a path for delaying the second simulation signal ss2. Wherein, the input terminal D of each second simulation delay register receives the signal to be delayed, and the output terminal Q of each second simulation delay register generates the delayed signal. When the number of second simulation delay registers is at least two, the second simulation signal ss2 is subjected to beat delays through at least two second simulation delay registers to obtain at least two second delayed candidate signals with different delays. For example Figure 4 As shown, the second simulation delay unit 211 includes M first simulation delay registers logically cascaded in a path for delaying the second simulation signal ss2. For example, M≥3 (M may be equal to N or not equal to N), including the second simulation delay register SDR2_1, the second simulation delay register SDR2_2,..., the second simulation delay register SDR2_M. Wherein, the input terminal D of the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M receives the signal to be delayed, and the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M generate the delayed signal. The second simulation signal ss2 is subjected to beat delays through the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M to obtain the second delayed candidate signals dss2_1 to the second delayed candidate signals dss2_M with different delays.

[0047] In a schematic embodiment, the first simulation delay register and the second simulation delay register may be implemented by a simulated D flip-flop.

[0048] In a schematic embodiment, in the phase detection simulation circuit of the present disclosure embodiment, the random signal generation module 41, the signal selection module 42, the first signal simulation delay circuit 11, and the second signal simulation delay circuit 21 may all be controlled by a clock signal ck with a frequency higher than the frequencies of the first simulation delay signal ss11 and the second simulation delay signal ss21 for timing, so as to ensure that the registers in the phase detection simulation circuit of the present disclosure embodiment can correctly capture the signal states at their input terminals in each clock cycle. Wherein, the clock signal ck is connected to the clock signal terminal clk of each first simulation delay register and second simulation delay register. For example Figure 4 As shown, the clock signal ck is connected to the clock signal terminal clk of the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N and the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M. In the first signal simulation delay circuit 11 and the second signal simulation delay circuit 21, the signal period of the clock signal ck is the minimum delay time for each first simulation delay register and each second simulation delay register to the received simulation signal. For exampleFigure 4 As shown, the signal period of the clock signal ck is the minimum delay time of each of the first simulation delay registers SDR1_1 to SDR1_N and the second simulation delay registers SDR2_1 to SDR2_M for the received simulation signal.

[0049] In a digital circuit system, if the setup and hold time requirements of a flip-flop are not met during data transmission, metastability may occur. At this time, the signal at the output terminal of the flip-flop remains in an uncertain state for a relatively long time after the effective clock edge. During this period, the signal at the output terminal of the flip-flop oscillates between 0 and 1, rather than being equal to the value of the signal at the input terminal of the flip-flop. This period is called the resolution time. After the resolution time, although the signal at the output terminal of the flip-flop will stabilize to the state of 0 or 1, the stabilization to 0 or 1 is random and there is no inevitable relationship with the input signal. That is to say, the finally stabilized output signal of the flip-flop may be an incorrect signal. The idea of the phase detection simulation circuit in the embodiments of the present disclosure is to use a random number (random signal rs) to replace the input signal (second simulation delay signal ss21) of the sampling simulation register 31 within the setup and hold time of the sampling simulation register 31. Among them, the random number may be 0 or 1, that is, the value of the random signal rs may be the same as or different from the value of the second simulation delay signal ss21. In this way, the input signal within the setup and hold time of the sampling simulation register 31 may be correct or incorrect, so that the output signal of the sampling simulation register 31 may also be correct or incorrect, thereby simulating the uncertainty of the output signal result of the sampling register 30 after the metastability ends due to the existence of metastability. In this way, by statistically calculating the correct rate or error rate of the output signal of the sampling simulation register 31 within a certain period of time, the statistical law of the phase detection simulation circuit can be obtained according to the correct rate or error rate, so as to perform relevant verification on the corresponding phase detection circuit.

[0050] Based on this, in a schematic embodiment, the embodiments of the present disclosure further provide a phase detection simulation and statistics system, which may include a statistics module and the phase detection simulation circuit of any one of the above embodiments. Among them, the statistics module is logically coupled to the output terminal Q of the sampling simulation register 31, and is used to receive the sampling simulation result signal ss_out and statistically calculate the correct rate or error rate of the sampling simulation result signal ss_out within a preset time period.

[0051] Figure 5 is a flowchart showing a phase detection simulation method according to a schematic embodiment. As Figure 5 shown, the phase detection simulation method mainly includes the following steps 501 to 503.

[0052] Step 501: Obtain a first simulation delay signal, a second simulation delay signal, and a random signal; Step 502: According to the comparison result between the phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range, select one of the second simulation delay signal and the random signal as the selected output signal; Step 503: Receive the first simulation delay signal at the clock signal terminal of the sampling simulation register, and receive the selected output signal at the input terminal of the sampling simulation register, and obtain a sampling simulation result signal at the output terminal of the sampling simulation register, where the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal.

[0053] Wherein, the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0054] In the illustrative embodiment, step 502 may specifically include: when the comparison result is that the phase difference is outside the preset threshold range, use the second simulation delay signal as the selected output signal; when the comparison result is that the phase difference is within the preset threshold range, use the random signal as the selected output signal.

[0055] Figure 6 is a schematic flowchart showing the process of obtaining a simulation delay signal according to an illustrative embodiment, as Figure 6 shown, the phase detection simulation method implemented by the present disclosure may further include the following steps 601 to 603.

[0056] Step 601: Obtain a first simulation signal and a second simulation signal; Step 602: Perform simulation delay on the first simulation signal to obtain a first simulation delay signal; Step 603: Perform simulation delay on the second simulation signal to obtain a second simulation delay signal.

[0057] In the illustrative embodiment, the phase detection simulation method of the present disclosure may further include: counting the correct rate or error rate of the sampling simulation result signal within a preset time period.

[0058] For the implementation of each step in the phase detection simulation method implemented by the present disclosure, reference may be made to the relevant descriptions in the above-mentioned phase detection simulation circuit embodiment, and details will not be elaborated here.

[0059] The present disclosure also provides a phase detection simulation system 700, as Figure 7As shown, the phase detection simulation system 700 includes a first processor 710 and a storage device 720. The storage device 720 is coupled to the first processor 710. In a schematic embodiment, the system may be, for example, a server system. The storage device 720 and the first processor 710 are coupled through a bus system in the server system. In a schematic embodiment, the storage device 720 is used to store programs, scripts, files, data, etc. associated with the phase detection simulation method. In a schematic embodiment, the first processor 710 can execute programs and scripts to implement and execute the phase detection simulation circuit and method. The files and data may include the files, data, etc. involved in the phase detection simulation method.

[0060] In a schematic embodiment, the first processor 710 can obtain corresponding results by calling the content (at least one of programs, scripts, files, data) stored in the storage device 720 and performing corresponding processing. For example, the first processor 710 can establish a model of the phase detection simulation circuit by calling the relevant parameters of the phase detection simulation circuit stored in the storage device 720, and obtain the required results by running the model of the phase detection simulation circuit. All kinds of intermediate data, files, final results and data involved can be stored in the storage device 720.

[0061] In a schematic embodiment, the first processor 710 may be a central processing unit (CPU), other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), other similar processing devices, or a combination of such devices. In a schematic embodiment, the storage device 720 may be a computer-readable storage medium having computer-readable instructions stored thereon, and when the computer-readable instructions are run by the first processor 710, the steps in the phase detection simulation method of the embodiments of the present disclosure may be executed. In a schematic embodiment, the computer-readable storage medium may be, for example, a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory, and the volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, various forms of RAM may be employed, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct memory bus random access memory (DR RAM), etc. The storage device 720 may store the data, scripts, programs, software, algorithms, etc. required to implement the various steps in the phase detection simulation method of the embodiments of the present disclosure, and supply them for execution by the first processor 710.

[0062] Figure 8 is a schematic structural diagram of a phase detection simulation device shown according to a schematic embodiment, as Figure 8As shown in the figure, the phase detection simulation device mainly includes a signal receiving module 801, a selection module 802, and a phase relationship determination module 803. Among them, the signal receiving module 801 is configured to receive a first simulation delay signal, a second simulation delay signal, and a random signal. The selection module 802 is configured to select one of the second simulation delay signal and the random signal as the selected output signal according to the comparison result between the phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range. The phase relationship determination module is configured to receive the first simulation delay signal at the clock signal terminal of the sampling simulation register and receive the selected output signal at the input terminal of the sampling simulation register, and obtain a sampling simulation result signal at the output terminal of the sampling simulation register. The sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal. The preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0063] In the illustrative embodiment, the selection module 802 is further configured to perform: when the comparison result is that the phase difference is outside the preset threshold range, use the second simulation delay signal as the selected output signal; when the comparison result is that the phase difference is within the preset threshold range, use the random signal as the selected output signal.

[0064] In the illustrative embodiment, the phase detection simulation device further includes: a simulation signal acquisition module configured to acquire a first simulation signal and a second simulation signal; a first delay module configured to perform simulation delay on the first simulation signal to obtain a first simulation delay signal; a second delay module configured to perform simulation delay on the second simulation signal to obtain a second simulation delay signal.

[0065] In the illustrative embodiment, the phase detection simulation device further includes: a phase relationship statistics module configured to perform statistics on the correct rate or error rate of the sampling simulation result signal within a preset time period.

[0066] Regarding the phase detection simulation device in the above embodiments, the specific manners in which each unit performs operations have been described in detail in the embodiments related to the phase detection simulation method and the phase detection simulation circuit, and will not be elaborated here.

[0067] It should be noted that: the above embodiments are only examples for illustration according to the above division of each functional module. In practical applications, the above functions can be allocated to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0068] Figure 9 Figure 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 900 may vary greatly due to configuration or performance differences, and may include one or more processors (Central Processing Units, CPUs) 901 and one or more memories 902. Among them, at least one program code is stored in the memory 902, and the at least one program code is loaded and executed by the processor 901 to implement the phase detection simulation methods provided by the above various embodiments. Of course, the electronic device 900 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The electronic device 900 may also include other components for implementing the functions of the device, which will not be elaborated here.

[0069]

[0069] In an exemplary embodiment, there is also provided a computer-readable storage medium including at least one instruction, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the phase detection simulation method in the above embodiment.

[0070]

[0070] Optionally, the above computer-readable storage medium may be a non-transitory computer-readable storage medium. For example, the non-transitory computer-readable storage medium may include a ROM (Read-Only Memory), a RAM (Random-Access Memory), a CD-ROM (Compact Disc Read-Only Memory), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0071]

[0071] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A phase detection simulation circuit, characterized in that: include: A random signal generating module, wherein the random signal generating module is used to generate a random signal; a signal selection module, the signal selection module being used to receive a first simulation delay signal, a second simulation delay signal and the random signal, and select one of the second simulation delay signal and the random signal as a selection output signal according to a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; A sampling simulation register, wherein a clock signal end of the sampling simulation register is used to receive the first simulation delay signal, an input end of the sampling simulation register is used to receive the selection output signal, and the sampling simulation register outputs a sampling simulation result signal at its output end according to the first simulation delay signal and the selection output signal, wherein the sampling simulation result signal is used to characterize a phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

2. The phase detection simulation circuit according to claim 1, characterized in that: The signal selection module comprises: A phase counting unit, used for receiving the first simulation delay signal and the second simulation delay signal, obtaining a first count value at the transition edge moment of the first simulation delay signal, and obtaining a second count value at the transition edge moment of the second simulation delay signal, wherein the first count value is used to characterize the transition edge moment of the first simulation delay signal, and the second count value is used to characterize the transition edge moment of the second simulation delay signal; a phase difference comparison unit, configured to obtain the comparison result according to the first count value, the second count value and the preset threshold range; A signal selection unit, wherein the signal selection unit is used to select one of the second simulated delayed signal and the random signal as the selected output signal according to the comparison result.

3. The phase detection simulation circuit according to claim 2, characterized in that: The phase counting unit comprises: A counting unit, the counting unit being used to count in relation to time; A capture unit, wherein the capture unit is used to receive the first simulation delay signal and the second simulation delay signal, and to capture the first count value generated by the counting unit at the transition edge of the first simulation delay signal, and to capture the second count value generated by the counting unit at the transition edge of the second simulation delay signal.

4. The phase detection simulation circuit according to claim 2, characterized in that: The phase difference comparison unit comprises: a phase difference calculation unit, configured to obtain the phase difference according to the first count value and the second count value; A comparison unit, wherein the comparison unit is used to compare the phase difference with the preset threshold range to obtain the comparison result.

5. The phase detection simulation circuit according to claim 1, characterized in that: The phase detection simulation circuit also includes: A first signal simulation delay circuit is used to receive a first simulation signal and perform simulation delay on the first simulation signal to obtain the first simulation delayed signal; The second signal simulation delay circuit is used to receive a second simulation signal and perform simulation delay on the second simulation signal to obtain the second simulation delayed signal.

6. The phase detection simulation circuit according to claim 5, characterized in that: The first signal simulation delay circuit comprises: A first simulation delay unit, the first simulation delay unit is used to receive the first simulation signal, and perform simulation delay on the first simulation signal to obtain at least one first delayed selected signal; a first simulation multi-path selection unit, the first simulation multi-path selection unit being used to receive the at least one first delayed selected signal and a first selection signal, and select one of the at least one first delayed selected signal as the first simulation delayed signal according to the first selection signal; The second signal simulation delay circuit comprises: A second simulation delay unit, the second simulation delay unit is used to receive the second simulation signal, and perform simulation delay on the second simulation signal to obtain at least one second delayed selected signal; The second simulation multi-way selection unit is used to receive the at least one second delayed selected signal and a second selection signal, and select one of the at least one second delayed selected signal as the second simulation delayed signal according to the second selection signal.

7. The phase detection simulation circuit according to claim 6, characterized in that: The first simulation delay unit comprises: At least one first simulation delay register cascaded on a path for delaying the first simulation signal, wherein an input end of the first simulation delay register receives a signal to be delayed, and an output end of the first simulation delay register generates a delayed signal, and in the case where the number of the first simulation delay registers is at least two, the first simulation signal is delayed by the beats of at least two of the first simulation delay registers to obtain at least two first delayed selected signals after different delays; The second emulation delay unit comprises: At least one second simulation delay register is cascaded on a path for delaying the second simulation signal, wherein an input end of the second simulation delay register receives a signal to be delayed, and an output end of the second simulation delay register generates a delayed signal. When the number of the second simulation delay registers is at least two, the second simulation signal is delayed by beats of at least two of the second simulation delay registers to obtain at least two second delayed selected signals after different delays.

8. A phase detection simulation method, comprising: Acquire a first simulation delay signal, a second simulation delay signal and a random signal; According to a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range, selecting one of the second simulation delay signal and the random signal as a selection output signal; Utilize the clock signal end of the sampling simulation register to receive the first simulation delay signal, utilize the input end of the sampling simulation register to receive the selection output signal, obtain the sampling simulation result signal at the output end of the sampling simulation register, and the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

9. The phase detection simulation method according to claim 8, characterized in that: The selecting one of the second simulation delay signal and the random signal as the selected output signal according to the comparison result of the phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range comprises: When the comparison result is that the phase difference is outside the preset threshold range, using the second simulated delay signal as a selection output signal; When the comparison result is that the phase difference is within the preset threshold range, the random signal is used as a selection output signal.

10. The phase detection simulation method according to claim 8, characterized in that: The phase detection simulation method also includes: Acquire a first simulation signal and a second simulation signal; Performing simulation delay on the first simulation signal to obtain the first simulation delayed signal; Performing simulation delay on the second simulation signal to obtain the second simulation delayed signal.

11. A phase detection simulation device, characterized in that: include: A signal receiving module, configured to receive a first simulated delayed signal, a second simulated delayed signal and a random signal; A selection module is configured to select one of the second simulation delay signal and the random signal as a selection output signal according to a comparison result between a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; a phase relationship determination module, configured to receive the first simulation delay signal using a clock signal end of a sampling simulation register, receive the selection output signal using an input end of the sampling simulation register, and obtain a sampling simulation result signal at an output end of the sampling simulation register, wherein the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

12. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the phase detection simulation method as described in any one of claims 8 to 10.

13. A computer-readable storage medium, characterized in that: When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the phase detection simulation method as described in any one of claims 8 to 10.

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