Setting latch capable of resisting single event transient and single event upset

Abstract

The invention relates to an anti-single event transient and anti-single event upset setting latch, which is characterized in that a setting signal end circuit is re-reinforced and designed, and a setting signal access terminal structure of the setting signal end circuit, which is accessed to a setting latch main body circuit, is correspondingly improved; by means of delay and judgment processing provided by a delay chain A, a delay chain B, an XNOR gate and a three-state phase inverter of a setting signal end circuit, it is ensured that a setting signal can be normally transmitted to a setting redundant circuit formed by a first phase inverter and a second phase inverter when no external transient pulse is input to a setting signal end; two paths of setting signals generated by the setting redundant circuit are respectively accessed to the setting latch main body circuit; when external transient pulse input exists at the setting signal end, the setting signal which is influenced by the transient state and causes an error cannot generate effective output through the three-state inverter, so that the error is filtered out, and the purpose of effectively realizing reinforcing design aiming at the external input transient state of the setting signal end is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a set latch for single event transient (SET) and single event upset (SEU) resistance. Background Art

[0002] There are various radiation particles (such as heavy ions, protons, neutrons, and electrons, etc.) and high-energy rays (such as γ rays and x rays, etc.) widely existing in the cosmic space environment. Bombardment of semiconductor devices by high-energy particles or rays can cause various types of failures of the devices, seriously reducing the reliability of integrated circuits in spacecraft control systems, reducing the service life of spacecraft or even damaging spacecraft, resulting in irreparable losses. Therefore, it is necessary to perform radiation hardening design on integrated circuits to improve their reliability in the cosmic space environment.

[0003] Standard cells are the basis of chip design. Strengthening the design of standard cells can effectively improve the reliability of aerospace-grade chips. The sequential logic unit in the standard cell is the key to storing data. The DICE (Dual Interlocked Storage Cell) hardening design is most commonly used for the sequential logic unit to achieve the purpose of SET and SEU resistance. However, the potential hazard of abnormal sampling of the circuit caused by bombardment of the set signal terminal of the sequential unit is often ignored. The above events can cause single event upset errors in the sequential unit. Therefore, how to perform hardening design for the external input transient of the set signal terminal has become a technical problem to be solved. Summary of the Invention

[0004] Aiming at the problems existing in the above traditional technologies, the present invention proposes a set latch for SET and SEU resistance, which can effectively implement the hardening design for the external input transient of the set signal terminal.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: Provide a set latch for SET and SEU resistance, including a set latch main circuit, a hardened set signal terminal circuit, and a clock redundancy circuit. The set signal terminal circuit is used to provide a first set signal and a second set signal for the set latch main circuit, and the clock redundancy circuit is used to provide a clock signal for the set latch main circuit; The set signal terminal circuit includes a delay chain A, a delay chain B, an exclusive-NOR gate, a tri-state inverter, a first inverter, and a second inverter. The input terminals of both the delay chain A and the delay chain B are used to receive the set signal SN. The output terminal of the delay chain A is connected to the input terminal of the tri-state inverter. The output terminal of the tri-state inverter is respectively connected to the input terminals of the first inverter and the second inverter. The output terminal of the first inverter is used to output a first set signal, and the output terminal of the second inverter is used to output a second set signal. The output terminal of the delay chain B is connected to the first input terminal of the exclusive-NOR gate. The second input terminal of the exclusive-NOR gate is connected to the input terminal of the delay chain B. The output terminal of the exclusive-NOR gate is connected to the enable control terminal of the tri-state inverter. The delay of the delay chain A is greater than the delay of the exclusive-NOR gate, and the delay of the delay chain A is less than the sum of the delay of the delay chain B and the delay of the exclusive-NOR gate. The inverter INVa in the set latch main circuit is connected to the second set signal and the first set signal through a first N-type transistor and a first P-type transistor respectively. The inverter INVb in the set latch main circuit is connected to the first set signal and the second set signal through a second N-type transistor and a second P-type transistor respectively. The sources of the first N-type transistor and the second N-type transistor are grounded. The gate of the first N-type transistor is connected to the output terminal of the second inverter. The drain of the first N-type transistor is connected to the source of the N-type transistor of the inverter INVa. The gate of the second N-type transistor is connected to the output terminal of the first inverter. The drain of the second N-type transistor is connected to the source of the N-type transistor of the inverter INVb. The sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage. The gate of the first P-type transistor is connected to the output terminal of the first inverter. The drain of the first P-type transistor is connected to the output terminal of the inverter INVa. The gate of the second P-type transistor is connected to the output terminal of the second inverter. The drain of the second P-type transistor is connected to the output terminal of the inverter INVb.

[0006] In one embodiment, the structure of the second inverter is the same as that of the first inverter.

[0007] In one embodiment, the clock redundancy circuit includes a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter. The input terminals of both the third inverter and the fifth inverter are used to receive the clock signal CK. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the third inverter is respectively connected to the first clock input terminal of the second data input circuit and the second clock input terminal of the second feedback circuit in the set latch main circuit. The output terminal of the fourth inverter is respectively connected to the second clock input terminal of the first data input circuit and the first clock input terminal of the first feedback circuit in the set latch main circuit. The output terminal of the fifth inverter is respectively connected to the first clock input terminal of the first data input circuit and the second clock input terminal of the first feedback circuit in the set latch main circuit, and the output terminal of the sixth inverter is respectively connected to the second clock input terminal of the second data input circuit and the first clock input terminal of the second feedback circuit in the set latch main circuit.

[0008] One of the technical solutions in the above technical solutions has the following advantages and beneficial effects: The above set latch for single event transient and single event upset resistance reinforces the design of the set signal terminal circuit and correspondingly improves the structure of the set signal access terminal for accessing the set latch main circuit. By using the delay chains A and B, the exclusive-NOR gate, and the tri-state inverter in the set signal terminal circuit to provide delay and decision processing, it is ensured that when there is no external transient pulse input at the set signal terminal, the set signal can be normally transmitted to the set redundancy circuit composed of the first inverter and the second inverter, and two set signals generated by the set redundancy circuit are respectively connected to the set latch main circuit; when there is an external transient pulse input at the set signal terminal, due to the output control effect of the delay and decision processing, the incorrect set signal affected by the transient at this time cannot generate an effective output through the tri-state inverter, so that the error is filtered out, avoiding the SN irradiation risk and more effectively improving the radiation resistance performance of the set latch, achieving the purpose of effectively implementing the reinforcement design for the external input transient of the set signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 It is a schematic diagram of the existing set signal terminal circuit design; Figure 2 It is a schematic diagram of the structure of the set latch main circuit in an embodiment; Figure 3 It is a schematic diagram of the structure of the set signal terminal circuit with reinforcement design in an embodiment; Figure 4 It is a schematic diagram of the structure of the clock redundancy circuit in an embodiment; Figure 5 It is a schematic diagram of the structure of the set signal terminal circuit with reinforcement design in another embodiment; Figure 6 It is a schematic diagram of the structure of the clock redundancy circuit in another embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0012] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The display of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0013] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0014] As Figure 1 shown in the design of the set signal terminal circuit, it cannot effectively shield the transient input from the outside of the set signal terminal, so that when the transient appears, the subsequent set signal SN1 will be abnormally turned on, causing the latch to be mis-set. Among them, the P transistor represents a P-type MOS transistor, the N transistor represents an N-type MOS transistor, and SN1 represents the set signal after the set signal SN passes through two inverters (each inverter is composed of a pair of P transistors and N transistors). The same applies hereinafter. For the design of the set signal terminal circuit as Figure 1 shown, the present invention proposes a new reinforcement design for the set signal terminal, so that the circuit of the improved latch can effectively remove the external input transient of the set signal terminal, so that the latch applied by it can resist both single-event transients and single-event upsets, further improving the radiation resistance of the latch, so as to enhance the reliability of the latch in a complex space environment and meet the application requirements of actual aerospace engineering.

[0015] In one embodiment, a set latch that resists single-event transients and single-event upsets is provided, including a set latch main circuit 100 as Figure 2 shown, a set signal terminal circuit 300 with a reinforcement design as Figure 3 shown, and as Figure 4The clock redundancy circuit 500 shown. The set signal terminal circuit 300 is used to provide a first set signal SN1 and a second set signal SN2 for the set latch main body circuit 100. The clock redundancy circuit 500 is used to provide clock signals (including clock signal nclk, clock signal nclk1, clock signal bclk, and clock signal bclk1) for the set latch main body circuit 100. The set signal terminal circuit 300 includes a delay chain A, a delay chain B, an exclusive-NOR gate XNOR, a tri-state inverter INV (Inverter), a first inverter INV1, and a second inverter INV2. The input ends of the delay chain A and the delay chain B are both used to access the set signal SN. The output end of the delay chain A is connected to the input end of the tri-state inverter INV. The output end of the tri-state inverter INV is respectively connected to the input ends of the first inverter INV1 and the second inverter INV2. The output end of the first inverter INV1 is used to output the first set signal SN1. The output end of the second inverter INV2 is used to output the second set signal SN2. The output end of the delay chain B is connected to the first input end of the exclusive-NOR gate XNOR. The second input end of the exclusive-NOR gate XNOR is connected to the input end of the delay chain B. The output end of the exclusive-NOR gate XNOR is connected to the enable control end EN of the tri-state inverter INV. The delay of the delay chain A is greater than the delay of the exclusive-NOR gate XNOR, and the delay of the delay chain A is less than the sum of the delay of the delay chain B and the delay of the exclusive-NOR gate XNOR.

[0016] The inverter INVa in the set latch main body circuit 100 accesses the second set signal SN2 and the first set signal SN1 through a first N-type transistor 101 and a first P-type transistor 201 respectively. The inverter INVb in the set latch main body circuit 100 accesses the first set signal SN1 and the second set signal SN2 through a second N-type transistor 102 and a second P-type transistor 202 respectively. The sources of the first N-type transistor 101 and the second N-type transistor 102 are grounded. The gate of the first N-type transistor 101 is connected to the output end of the second inverter INV2. The drain of the first N-type transistor 101 is connected to the source of the N-type transistor of the inverter INVa. The gate of the second N-type transistor 102 is connected to the output end of the first inverter INV1. The drain of the second N-type transistor 102 is connected to the source of the N-type transistor of the inverter INVb. The sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage. The gate of the first P-type transistor 201 is connected to the output end of the first inverter INV1. The drain of the first P-type transistor 201 is connected to the output end of the inverter INVa. The gate of the second P-type transistor 202 is connected to the output end of the second inverter INV2. The drain of the second P-type transistor 202 is connected to the output end of the inverter INVb.

[0017] It can be understood that the clock signal CK and the part of the set latch main body circuit 100 are both existing signal and circuit parts in the art. The improvement point of this embodiment lies in the structural design of the set signal circuit and the adaptive improvement of the local circuit part of the latch. Among them, Figure 4The third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6 are the main components of the hardened clock redundancy circuit 500. Each inverter can be formed by connecting MOS transistors, and the number of MOS transistors included in each inverter can be the same or different, and can be specifically selected according to the clock signal required by the set latch main circuit 100 in actual applications.

[0018] The set latch with single event transient immunity and single event upset immunity has three input terminals and one output terminal. The three input terminals are the clock signal CK terminal, the data input signal D terminal, and the set signal terminal, and the one output terminal is the Q terminal. The set signal SN is processed through the delay, decision, and redundancy circuits to output the processed set signals SN1 and SN2. After the data D passes through the inverters (i.e., the inverters in the first data input circuit DA1 and the second data input circuit DA2) controlled by the clock signals nclk, nclk1, bclk, and bclk1 output by the clock redundancy circuit 500, the signals ND1 and ND2 are output. The signals ND1 and ND2 pass through the inverters INVa and INVb, and the inverter in the output circuit of the set latch main circuit 100 and are output to the Q terminal. The inverters INVa and INVb in the set latch main circuit 100 together form a part of the existing DICE hardened circuit structure of the latch, and play a key role in improving the radiation resistance and data processing reliability of the latch.

[0019] When there is an external transient pulse input at the set signal terminal, due to the delay of the delay chain B, the signal phases at the two input terminals of the XNOR gate are inconsistent, resulting in its output being low level (i.e., EN is low level), and the tri-state inverter INV is enabled to turn off. At this time, the set signal SN signal (after passing through the delay chain A) cannot be transmitted (that is, it cannot reach the subsequent set latch main circuit 100). Therefore, the design of the set signal terminal circuit 300 can effectively remove this transient and eliminate the influence of this transient on the storage state of the subsequent latch. It should be noted that when designing, it is necessary to pay attention that the delay of the delay chain A should be greater than the delay of the XNOR gate, and the delay of the delay chain A is less than the total delay of the delay chain B + the XNOR gate to meet the setup and hold time requirements of the set signal SN and the enable signal EN.

[0020] When the clock signal CK is at a high level, the data D is output through an inverter to the existing DICE circuit structure of the set latch main circuit 100, forming signals ND1 and ND2 in the same state. The signals ND1 and ND2 are then sent to the output Q terminal through a stage of inverter. When the clock signal CK is at a low level, the data D cannot be output through the inverter to the DICE, but the feedback circuit of the DICE circuit structure is turned on, and the stored data is continuously output to the Q terminal. The set signal SN is at a low level to perform a set operation on the latch, and the Q terminal is at a high level after the set operation.

[0021] When the clock signal CK is at a low level, a storage cycle occurs inside the latch. Assume that the voltages of nodes A and B are both at a high level. Although the set signal SN is at a high level (the latch is in a set release state), the set signals SN1 and SN2 are at a high level state, but the drains of the N transistors connected to the set signals SN1 and SN2 are sensitive points. When this sensitive point is bombarded (assuming the drain of the N transistor connected to the set signal SN1 is bombarded), the state of the set signal SN1 changes from a high level to a low level, forming a 101 error signal. This error signal forces the connected P transistor to turn on, so node A is pulled high to a high level. However, the N transistor connected to the set signal SN1 is turned off, so the voltage of node B remains at the correct high level. Due to the competition between nodes A and B, the state of the Q terminal is in an indeterminate state at this time. When the above error is removed, the state of node A is restored to a high level through the feedback circuit. Finally, the Q terminal returns to the normal high level state. Therefore, the set latch can effectively improve the single-event transient and single-event upset resistance capabilities through the reinforcement of the set signal terminal.

[0022] For the above set latch with single-event transient and single-event upset resistance, by re-reinforcing and designing the set signal terminal circuit 300 and correspondingly improving the set signal access terminal structure for accessing the set latch main circuit 100, using the delay provided by the delay chain A, delay chain B, exclusive-NOR gate XNOR, and tri-state inverter INV in the set signal terminal circuit 300 and the decision processing, it is ensured that when there is no external transient pulse input at the set signal terminal, the set signal can be normally transmitted to the set redundancy circuit composed of the first inverter INV1 and the second inverter INV2, and two set signals are generated by the set redundancy circuit and respectively connected to the set latch main circuit; when there is an external transient pulse input at the set signal terminal, due to the output control effect of the delay and decision processing, the set signal affected by the transient error at this time cannot generate an effective output through the tri-state inverter INV, so that the error is filtered out, avoiding the SN irradiation risk and at the same time more effectively improving the radiation resistance performance of the set latch, achieving the purpose of effectively implementing the reinforcement design for the external input transient of the set signal terminal.

[0023] In one embodiment, as Figure 5As shown, the first inverter INV1 includes a P-type transistor and an N-type transistor. The source of the P-type transistor is connected to the power supply voltage (such as VDD). The gates of both the P-type transistor and the N-type transistor are connected to the output terminal of the tri-state inverter INV. The drain of the P-type transistor is connected to the drain of the N-type transistor and serves as the output terminal of the first inverter INV1. The source of the N-type transistor is grounded (such as GND or VSS).

[0024] It can be understood that in this embodiment, a relatively simple and efficient circuit structure of the first inverter INV1 is provided, which consists of a pair of MOS transistors. That is, the reliable output of the SN1 signal can be achieved with a relatively small circuit scale, which helps to further reduce the overall circuit area of the set latch.

[0025] In one embodiment, the structure of the second inverter INV2 is the same as that of the first inverter INV1.

[0026] It can be understood that in this embodiment, the second inverter INV2 and the first inverter INV1 adopt the same circuit structure, so that two set signals can be respectively output by a more concise set redundancy structure, further reducing the circuit design difficulty and, at the same time, further reducing the overall circuit area of the set latch.

[0027] In one embodiment, as Figure 2 and 6 shown, the clock redundancy circuit 500 includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5 and a sixth inverter INV6. The input terminals of both the third inverter INV3 and the fifth inverter INV5 are used to receive the clock signal CK. The output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4. The output terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6. The output terminal of the third inverter INV3 is respectively connected to the first clock input terminal of the second data input circuit DA2 and the second clock input terminal of the second feedback circuit F2 in the set latch main circuit 100. The output terminal of the fourth inverter INV4 is respectively connected to the second clock input terminal of the first data input circuit DA1 and the first clock input terminal of the first feedback circuit F1 in the set latch main circuit 100. The output terminal of the fifth inverter INV5 is respectively connected to the first clock input terminal of the first data input circuit DA1 and the second clock input terminal of the first feedback circuit F1 in the set latch main circuit 100. The output terminal of the sixth inverter INV6 is respectively connected to the second clock input terminal of the second data input circuit DA2 and the first clock input terminal of the second feedback circuit F2 in the set latch main circuit 100.

[0028] It can be understood that, in this embodiment, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6 are each composed of a P transistor and an N transistor, thereby forming a simple and reinforced clock redundancy circuit 500, which is implemented to provide the required clock signals nclk, nclk1, bclk, and bclk1 for the set latch main circuit 100, ensuring that even when the CK terminal of the clock signal is bombarded, single-event transients will not be introduced into the set latch main circuit 100, thereby further enhancing the set latch's resistance to single-event transients and single-event upsets.

[0029] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0030] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A single-particle transient and single-particle upset resistant set latch, characterized in that: It includes a set latch main circuit, a set signal end circuit with a reinforced design, and a clock redundancy circuit, wherein the set signal end circuit is used to provide a first set signal and a second set signal for the set latch main circuit, and the clock redundancy circuit is used to provide a clock signal for the set latch main circuit; The set signal terminal circuit includes a delay chain A, a delay chain B, an XNOR gate, a three-state inverter, a first inverter and a second inverter. The input terminals of the delay chain A and the delay chain B are both used to access the set signal SN. The output terminal of the delay chain A is connected to the input terminal of the three-state inverter. The output terminal of the three-state inverter is respectively connected to the input terminals of the first inverter and the second inverter. The output terminal of the first inverter is used to output the first set signal. The output terminal of the second inverter is used to output the second set signal. The output terminal of the delay chain B is connected to the first input terminal of the XNOR gate. The second input terminal of the XNOR gate is connected to the input terminal of the delay chain B. The output terminal of the XNOR gate is connected to the enable control terminal of the three-state inverter. The delay of the delay chain A is greater than the delay of the XNOR gate, and the delay of the delay chain A is less than the sum of the delay of the delay chain B and the delay of the XNOR gate. The inverter INVa in the main circuit of the set latch is connected to the second set signal and the first set signal respectively through the first N-tube and the first P-tube, and the inverter INVb in the main circuit of the set latch is connected to the first set signal and the second set signal respectively through the second N-tube and the second P-tube, the sources of the first N-tube and the second N-tube are grounded, the gate of the first N-tube is connected to the output end of the second inverter, the drain of the first N-tube is connected to the source of the N-tube of the inverter INVa, the gate of the second N-tube is connected to the output end of the first inverter, the drain of the second N-tube is connected to the source of the N-tube of the inverter INVb, the sources of the first P-tube and the second P-tube are connected to the power supply voltage, the gate of the first P-tube is connected to the output end of the first inverter, the drain of the first P-tube is connected to the output end of the inverter INVa, the gate of the second P-tube is connected to the output end of the second inverter, and the drain of the second P-tube is connected to the output end of the inverter INVb.

2. The single-event transient and single-event upset resistant set latch according to claim 1, characterized in that: The first inverter includes a P tube and an N tube, the source of the P tube is connected to the power supply voltage, the gate of the P tube and the gate of the N tube are both connected to the output end of the three-state inverter, the drain of the P tube is connected to the drain of the N tube and serves as the output end of the first inverter, and the source of the N tube is grounded.

3. The single-event transient and single-event upset resistant set latch according to claim 2, characterized in that: The structure of the second inverter is the same as that of the first inverter.

4. The single event transient and single event upset resistant set latch according to any one of claims 1 to 3, characterized in that: The clock redundancy circuit comprises a third inverter, a fourth inverter, a fifth inverter and a sixth inverter, the input ends of the third inverter and the fifth inverter are both used to access the clock signal CK, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fifth inverter is connected to the input end of the sixth inverter; The output end of the third inverter is respectively connected to the first clock input end of the second data input circuit and the second clock input end of the second feedback circuit in the set latch main circuit, and the output end of the fourth inverter is respectively connected to the second clock input end of the first data input circuit and the first clock input end of the first feedback circuit in the set latch main circuit; The output end of the fifth inverter is respectively connected to the first clock input end of the first data input circuit and the second clock input end of the first feedback circuit in the set latch main circuit, and the output end of the sixth inverter is respectively connected to the second clock input end of the second data input circuit and the first clock input end of the second feedback circuit in the set latch main circuit.

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