Tuning voltage calibration device, phase-locked loop and tuning voltage calibration method

Abstract

The embodiment of the invention provides a tuning voltage calibration device, a phase-locked loop and a tuning voltage calibration method, the device comprises a voltage comparison module and a calibration module, the output end of the voltage comparison module is connected with the input end of the calibration module, the voltage comparison module is connected with the phase-locked loop, and the phase-locked loop is connected with the calibration module. The comparator is used for comparing a reference voltage with a preset value with a tuning voltage in a phase-locked loop through a hysteresis comparator to generate an error signal; and the calibration module is used for determining the calibration direction of the tuning voltage according to the error signal, calibrating the tuning voltage based on the calibration direction, and stopping calibration of the tuning voltage under the condition that the error signal is continuously overturned. According to the embodiment of the invention, one hysteresis comparator is adopted, the implementation mode is simpler, the controllable range of the tuning voltage is enlarged, calibration is stopped when the tuning voltage is stable, power consumption generated by continuous calibration is avoided, and the problems that the tuning voltage range of double comparators is limited and continuous power consumption overhead exists in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular, to a calibration device for tuning voltage, a phase-locked loop, and a calibration method for tuning voltage. Background Art

[0002] With the rapid development of wireless communication technology, various electronic communication devices have put forward higher requirements for the performance of phase-locked loops.

[0003] In order to meet the phase tracking of the phase-locked loop in a temperature drift environment and the requirements of each communication system for an increasingly wide operating frequency range of the phase-locked loop, the tuning gain (Kvco) of the voltage-controlled oscillator (VCO) needs to be designed to be very large. However, the power supply push index of the voltage-controlled oscillator with a large tuning gain will correspondingly increase, and the VCO is more vulnerable to the interference of power supply noise fluctuations and is more difficult to achieve high performance. Figure 1 FIG. is a schematic diagram of the tuning voltage calibration technology of a phase-locked loop in the related art, which is to collect the voltage in the voltage-controlled oscillator and calibrate the voltage-controlled signal of the oscillator based on the comparison result of the collected voltage with the detection voltage windows preset by two comparators.

[0004] Due to the linearity limitation of the phase discrimination module, the magnitudes of different tuning voltages have a certain impact on the loop noise performance of the phase-locked loop, and the tuning voltage range of the dual comparator is limited. The limited tuning voltage range cannot ensure that the tuning voltage at lock-in is the optimal tuning voltage.

[0005] At the same time, for the scenario where the tuning voltage ripple is large in the locked state, the comparator will always be in the working state to calibrate the tuning voltage, which is an additional power consumption overhead for a steady-state system.

[0006] In summary, there is no good solution to the problem that the tuning voltage range of the dual comparator in the related art is limited and there is continuous power consumption overhead. Summary of the Invention

[0007] Embodiments of the present application provide a calibration device for tuning voltage, a phase-locked loop, and a calibration method for tuning voltage, so as to at least solve the problem that the tuning voltage range of the dual comparator in the related art is limited and there is continuous power consumption overhead.

[0008] According to an embodiment of the present application, a calibration device for a tuning voltage is provided. The device includes a voltage comparison module and a calibration module. The output end of the voltage comparison module is connected to the input end of the calibration module. Wherein, the voltage comparison module is configured to compare a reference voltage of a preset value with the tuning voltage in a phase-locked loop through a hysteresis comparator to generate an error signal; the calibration module is configured to determine the calibration direction of the tuning voltage according to the error signal, calibrate the tuning voltage based on the calibration direction, and stop calibrating the tuning voltage when the error signal continuously flips.

[0009] According to another embodiment of the present application, a phase-locked loop is provided. The phase-locked loop includes a phase-locked loop circuit and the calibration device for the tuning voltage in any of the above embodiments. The phase-locked loop circuit includes a voltage-controlled oscillator. The input end of the calibration device is connected to the input end of the voltage-controlled oscillator, and the output end of the calibration device is connected to the control end of the voltage-controlled oscillator. Wherein, the calibration device is configured to calibrate the tuning voltage in the phase-locked loop circuit; the voltage-controlled oscillator is configured to generate a target signal under the control of the calibrated tuning voltage.

[0010] According to another embodiment of the present application, a method for calibrating the tuning voltage of a phase-locked loop is provided, which is applied to the phase-locked loop in any of the above embodiments. The method includes: comparing a reference voltage of a preset value with the tuning voltage in the phase-locked loop through a hysteresis comparator to generate an error signal; determining the calibration direction of the tuning voltage according to the error signal, calibrating the tuning voltage based on the calibration direction, and stopping calibrating the tuning voltage when the error signal continuously flips.

[0011] According to still another embodiment of the present application, a computer-readable storage medium is further provided. A computer program is stored in the storage medium. Wherein, when the computer program is run by a processor, the steps in any of the above method embodiments are executed.

[0012] According to still another embodiment of the present application, an electronic device is further provided, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0013] In the embodiment of the present application, a calibration device for tuning voltage is designed. By using a hysteresis comparator, the implementation method is simpler, the controllable range of the tuning voltage is increased, and the calibration is stopped when the tuning voltage is stable, avoiding the power consumption caused by continuous calibration. Furthermore, it can solve the problems in the related art that the tuning voltage range of the dual comparator is limited and there is continuous power consumption overhead. Using a hysteresis comparator can also avoid the situation where the tuning voltage calibration in the prior art is easily affected by environmental interference. After the calibration is completed, by configuring the hysteresis range of the hysteresis comparator, the impact on the phase-locked loop can be avoided within a certain environmental change range, thereby improving the overall performance of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of the calibration device for tuning voltage according to the embodiment of the present application;

[0015] Figure 2 is a block diagram of the calibration module according to the embodiment of the present application;

[0016] Figure 3 is a schematic structural diagram of the calibration comparison unit according to the embodiment of the present application;

[0017] Figure 4 is a schematic structural diagram of a phase-locked loop according to the embodiment of the present application;

[0018] Figure 5 is a schematic structural diagram of an analog phase-locked loop with a classic structure according to the embodiment of the present application;

[0019] Figure 6 is a schematic structural diagram (one) of a sampling phase-locked loop according to the embodiment of the present application;

[0020] Figure 7 is a schematic structural diagram (two) of a sampling phase-locked loop according to the embodiment of the present application;

[0021] Figure 8 is a schematic diagram of the simulation result of the tuning voltage calibration according to the embodiment of the present application;

[0022] Figure 9 is a flowchart of the tuning voltage calibration method according to the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In the following, the embodiments of the present application will be described in detail with reference to the drawings and in combination with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0025] An embodiment of the present application provides a calibration device for a tuning voltage. Figure 1 It is a structural block diagram of the calibration device for the tuning voltage in the embodiment of the present application. As Figure 1 shown, the calibration device for the tuning voltage includes the following structure:

[0026] A voltage comparison module 10 and a calibration module 20.

[0027] In this embodiment, the output end of the voltage comparison module is connected to the input end of the calibration module.

[0028] In this embodiment, the voltage comparison module 10 is configured to compare a reference voltage of a preset value with a tuning voltage in a phase-locked loop through a hysteresis comparator to generate an error signal.

[0029] In this embodiment, the calibration module 20 is configured to determine a calibration direction of the tuning voltage according to the error signal, calibrate the tuning voltage based on the calibration direction, and stop calibrating the tuning voltage when the error signal continuously flips.

[0030] In this embodiment, the reference voltage is set to a target value to which the tuning voltage needs to be calibrated. The voltage comparison module uses a hysteresis comparator to compare the magnitudes of the reference voltage and the actual tuning voltage, and generates error information for the calibration module to perform calibration.

[0031] Through the embodiment of the present application, one hysteresis comparator is used to replace two comparators, saving resources such as area and power consumption. Moreover, by using the hysteresis comparator, the controllable range of the tuning voltage can be increased, avoiding the situation that the calibration of the tuning voltage is easily affected by environmental interference, and further overcoming the ripple disturbance on the tuning voltage when the phase-locked loop is locked, with stronger stability. The embodiment of the present application also stops calibration when the tuning voltage is stable, avoiding the power consumption generated by continuous calibration, and thus can solve the problems in the related art that the tuning voltage range of the dual comparator is limited and there is continuous power consumption overhead.

[0032] In some embodiments, after calibration is completed, by configuring the hysteresis range of the hysteresis comparator, the control of the tuning voltage can be achieved, and the influence on the phase-locked loop can also be avoided within a certain environmental change range, thereby improving the overall performance of the phase-locked loop.

[0033] Figure 2 It is a structural block diagram of the calibration module according to the embodiment of the present application. As Figure 2 shown, the calibration module 20 includes the following structure:

[0034] A calibration comparison unit 22 and a calibration control unit 24.

[0035] In this embodiment, the input end of the calibration comparison unit is connected to the output end of the voltage comparison module, and the output end of the calibration comparison unit is connected to the input end of the calibration control unit.

[0036] In this embodiment, the calibration comparison unit 22 is configured to generate a calibration direction signal and a calibration control signal based on the error signal input from the voltage comparison module and an externally input sampling clock signal, wherein the calibration direction signal is used to indicate the calibration direction of the tuning voltage, and the calibration control signal is used to indicate whether to stop calibrating the tuning voltage.

[0037] In this embodiment, the calibration control unit 24 is configured to calibrate the tuning voltage based on the calibration direction signal and the calibration control signal.

[0038] In some embodiments, the calibration control unit 24 is further configured to perform downward calibration on the tuning voltage when the calibration control signal is at a low level and the calibration direction signal is at a low level; perform upward calibration on the tuning voltage when the calibration control signal is at a low level and the calibration direction signal is at a high level; and stop calibrating the tuning voltage when the calibration control signal is at a high level.

[0039] In some embodiments, the calibration comparison unit 22 is further configured to continuously sample the error signal based on the sampling clock signal, and compare whether the results of two adjacent samplings are consistent. When the results of two adjacent samplings are consistent, the calibration control signal is output at a low level; when the results of two adjacent samplings are inconsistent, the calibration control signal is output at a high level.

[0040] In some embodiments, the calibration comparison unit 22 is further configured to generate the calibration direction signal based on the error signal.

[0041] In some embodiments, the calibration control unit calibrates the tuning voltage and controls the voltage-controlled oscillator by means of a control capacitor array, or can be implemented by means of a current mirror digital-to-analog converter, etc. The present application does not limit this.

[0042] In this embodiment, the calibration comparison unit can determine the calibration direction according to the error signal output by the hysteresis comparator. If opposite signals are continuously sampled, it indicates that the tuning voltage has reached the target voltage value, and a calibration termination signal (equivalent to the calibration control signal) is output through logic.

[0043] Figure 3 is a schematic structural diagram of the calibration comparison unit according to an embodiment of the present application. As Figure 3 shown, the calibration comparison unit 22 includes the following structure:

[0044] The first D flip-flop 221, the second D flip-flop 222, the exclusive-OR gate 223, the third D flip-flop 224, and the NOT gate 225.

[0045] In this embodiment, the clock input terminals of the first D flip-flop and the second D flip-flop are connected to the sampling clock signal, the data input terminal of the first D flip-flop is connected to the output terminal of the voltage comparison module, the output terminal of the first D flip-flop is respectively connected to the data input terminal of the second D flip-flop and the first input terminal of the exclusive-OR gate, the output terminal of the second D flip-flop is connected to the second input terminal of the exclusive-OR gate, the output terminal of the exclusive-OR gate is connected to the clock input terminal of the third D flip-flop, the data input terminal of the third D flip-flop is connected to a high-level signal, the input terminal of the NOT gate is connected to the output terminal of the voltage comparison module, and the output terminals of the third D flip-flop and the NOT gate are connected to the input terminal of the calibration control unit.

[0046] In this embodiment, the calibration comparison unit is configured to obtain the current sampling result of the error signal through the first D flip-flop under the control of the sampling clock signal, obtain the previous sampling result of the error signal from the output terminal of the first D flip-flop through the second D flip-flop under the control of the sampling clock signal, determine whether the current sampling result and the previous sampling result are consistent through the exclusive-OR gate, and control the third D flip-flop to output the calibration control signal as a low level when the current sampling result and the previous sampling result are consistent, and control the third D flip-flop to output the calibration control signal as a high level when the current sampling result and the previous sampling result are inconsistent.

[0047] In this embodiment, the calibration comparison unit is further configured to perform an inversion operation on the error signal through the NOT gate and output the calibration direction signal.

[0048] In the embodiment of the present application, the calibration direction is determined according to the error signal output by the hysteresis comparator, and the exclusive-OR logic operation is performed on the error signals sampled by multiple D flip-flops. If opposite signals are continuously sampled, it indicates that the tuning voltage has reached the target voltage value, and the calibration termination signal is output through the logic circuit in this embodiment.

[0049] In some embodiments, in addition to being implemented by a logic circuit, the calibration comparison unit can also be implemented by a fully digital solution.

[0050] In some embodiments, the tuning voltage calibration device further includes a reference voltage generation module 30, and the output terminal of the reference voltage generation module is connected to the second input terminal of the voltage comparison module.

[0051] In this embodiment, the reference voltage generation module is configured to generate a reference voltage of the preset value through a digital register.

[0052] In the embodiment of the present application, the control of the tuning voltage can be realized through a digital register, thereby making up for the defect of the linearity of the phase discriminator module in the PLL loop and improving the reliability of the PLL and the loop performance of the system.

[0053] In some embodiments, compared with the conventional dual comparator calibration, the single hysteresis comparator tuning voltage calibration of the present invention does not introduce additional noise. The newly added resistor sizes in the hysteresis comparator structure are relatively large, and the additional resistor thermal noise is very small. Moreover, it can be seen from the simulation results in the same scenario that the tuning voltage ripple of the present invention is even smaller than that of the conventional comparator, because the contribution of the additional comparator to the system noise during operation is reduced.

[0054] In other embodiments, the voltage comparison module in the present application is not limited to being implemented by a single hysteresis comparator. It can also be replaced by multiple comparators and calibration control for increasing the tuning voltage fluctuation range, which can also improve the anti-interference ability while completing the tuning voltage calibration. In addition, both dynamic comparators and static comparators can be used as the comparators here to achieve calibration without affecting the calibration timing.

[0055] In another embodiment of the present application, a phase-locked loop is provided. The phase-locked loop includes: a phase-locked loop circuit 40 and the calibration device for the tuning voltage in any of the above embodiments. The phase-locked loop circuit includes a voltage-controlled oscillator 41. The input end of the calibration device is connected to the input end of the voltage-controlled oscillator, and the output end of the calibration device is connected to the control end of the voltage-controlled oscillator.

[0056] In this embodiment, the calibration device is configured to calibrate the tuning voltage in the phase-locked loop circuit;

[0057] In this embodiment, the voltage-controlled oscillator is configured to generate a target signal under the control of the calibrated tuning voltage.

[0058] The embodiment of the present application can be applied to the scenario where the tuning gain design of the voltage-controlled oscillator (VCO) is small and cannot fully cover the temperature drift. When the tuning gain is small, with the change of the external temperature, the output frequency of the VCO may deviate, resulting in loop unlocking. However, through tuning voltage calibration, the loop can still maintain loop stability under temperature changes, improving the stability of the loop. Moreover, for a VCO with a smaller designed tuning gain, its own performance can also be designed better.

[0059] The embodiments of the present application can also be applied to the scenario where after the analog phase-locked loop completes locking, due to the poor linearity of the phase discriminator module, the noise performance of the phase-locked loop is very poor at certain tuning voltages. By calibrating the value of the tuning voltage to half of the power supply voltage (or other more optimal values) through digital control, the phase-locked loop can exhibit better performance.

[0060] The embodiments of the present application can also be applied to the scenario where there is a large ripple in the tuning voltage when the phase-locked loop is locked. The large ripple may be due to various reasons such as too much noise in the power supply or ground terminal and poor loop filtering effect. However, in all cases, the calibrated tuning voltage can be stabilized through the present invention, and there is no need for periodic repeated calibration, saving the power consumption of the calibration loop part. In the design of complex high-performance phase-locked loops, the power consumption of the digital part cannot be ignored either.

[0061] Figure 4 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application, as Figure 4 shown, the phase-locked loop in the phase-locked loop includes the following structures:

[0062] a voltage-controlled oscillator 41, a phase discriminator 42, a loop filter 43, and a multi-mode frequency divider 44.

[0063] In this embodiment, the first input terminal of the phase discriminator is connected to an externally input reference clock signal, the second input terminal of the phase discriminator is connected to the output terminal of the multi-mode frequency divider, the output terminal of the phase discriminator is connected to the input terminal of the loop filter, the output terminal of the loop filter is connected to the input terminal of the voltage-controlled oscillator, and the output terminal of the voltage-controlled oscillator is connected to the input terminal of the multi-mode frequency divider.

[0064] In some embodiments, the phase discriminator is configured to generate a phase difference signal based on the externally input reference clock signal and the feedback signal output by the multi-mode frequency divider, and input the phase difference signal into the loop filter; the loop filter is configured to perform filtering processing on the phase difference signal to generate the tuning voltage; the multi-mode frequency divider is configured to perform frequency division processing on the target signal to obtain the feedback signal.

[0065] In some embodiments, the calibration device for the tuning voltage in the present application can be applied to an analog phase-locked loop with a classic structure.

[0066] Figure 5 is a schematic structural diagram of an analog phase-locked loop with a classic structure according to an embodiment of the present application, as Figure 5 shown, without changing the original phase-locked loop structure, only by replacing the original calibration module (such as a scheme using a dual comparator) with the calibration module (using a single hysteresis comparator) in the embodiments of the present application, high-stability, low-power, and low-area tuning voltage calibration can be achieved.

[0067] In this embodiment, the phase-locked loop circuit uses a combination of a charge pump and a low-pass filter. The phase detector uses a frequency discriminator / phase detector. The multi-mode frequency divider can divide the output of the voltage-controlled oscillator under the action of a sigma-delta modulator (∑△M).

[0068] In some embodiments, the calibration logic control part can also be fully implemented using digital circuits. In addition to using a capacitor design to control the VCO with a digital signal, it is also possible to control the VCO by designing a digital-to-analog converter, but it is necessary to ensure that this part does not deteriorate the noise performance of the VCO.

[0069] In some other embodiments, the tuning voltage calibration device in the present application can also be applied to a sampling phase-locked loop.

[0070] Figure 6 is a schematic diagram (one) of the structure of a sampling phase-locked loop according to an embodiment of the present application, as Figure 6 shown. In addition to the above-mentioned general voltage-controlled oscillator 41, phase detector 42, loop filter 43, and multi-mode frequency divider 44 in the sampling phase-locked loop, the following structures are further included:

[0071] Digital time converter 45 and frequency-locked loop 46.

[0072] In this embodiment, the digital time converter is used to perform calibration processing on the reference clock signal and input the calibrated reference clock into the phase detector and the frequency-locked loop.

[0073] In this embodiment, the frequency-locked loop is used to assist in locking the target signal based on the calibrated reference clock and the feedback signal output by the multi-mode frequency divider.

[0074] In this embodiment, the sampling phase-locked loop is composed of a phase-locked loop main loop, a frequency-locked loop (Frequency Locked Loop, abbreviated as FLL), and a digital time converter (Digital to Time Converter, abbreviated as DTC).

[0075] In this embodiment, since the phase detection range in the initial locking stage of the sampling phase-locked loop (Sampling Phase Locked Loop, abbreviated as SPLL) is very narrow, it is necessary to rely on the frequency-locked loop for assisted locking.

[0076] In this embodiment, the digital time converter can use calibration algorithms such as the Least Square Method (abbreviated as LMS) to reduce the quantization noise of the Sigma Delta Modulation (abbreviated as SDM) (also known as the sigma-delta modulator).

[0077] Figure 7 This is the schematic diagram (II) of the structure of a sampling phase-locked loop according to an embodiment of the present application. As Figure 7 shown, the structure of the phase-locked loop in the sampling phase-locked loop is as follows:

[0078] There are two phase discrimination methods in the phase discriminator in the phase-locked loop, namely a sampling detector (abbreviated as SPD) and an exclusive OR logic circuit (abbreviated as XOR).

[0079] The loop filter includes a proportional path and an integral path. Among them, the integral path includes a transconductance module and an integrating capacitor, and the output end of the transconductance module is connected to the input end of the calibration device; the calibration device is used to obtain the tuning voltage from the phase-locked loop through the integral path.

[0080] In this embodiment, a part of the signal output by the phase discriminator serves as the tuning voltage of the proportional path VCO, and another part of the signal passes through the transconductance module and the integrating capacitor to become the tuning voltage of the integral path VCO. The calibration module is connected to the tuning voltage of the integral path of the main loop.

[0081] In this embodiment, the calibration device includes a voltage comparison module and a calibration module. The structure adopted by the voltage comparison module is a hysteresis comparator structure. The calibration module obtains the information of calibration completion by means of multi-stage D flip-flop sampling, transfers the calibration information to the digital calibration module for processing, and finally the output digital control word can complete the tuning voltage calibration by adjusting the VCO capacitor array.

[0082] The tuning voltage calibration device in the embodiment of the present application can not only be applied to the sampling phase-locked loop, but also to all analog phase-locked loops using voltage-controlled oscillators, with simple implementation and a large controllable range of the tuning voltage. Secondly, the voltage comparison module replaces two comparators with one hysteresis comparator, saving resources such as area and power consumption, and the voltage comparison module implemented by the hysteresis comparator can overcome the ripple disturbance on the tuning voltage during locking and has stronger stability. Finally, the controllable tuning voltage implemented in the present application can make up for the defect of the linearity of the phase discrimination module in the phase-locked loop and improve the reliability of the phase-locked loop and the loop performance of the system.

[0083] Figure 8 This is the schematic diagram of the simulation result of the tuning voltage calibration according to an embodiment of the present application. As Figure 8 shown, after the tuning voltage calibration is completed, the tuning voltage no longer changes.

[0084] In this embodiment, after the sampling phase-locked loop completes frequency locking through the frequency-locked loop and then switches to the phase-locked loop to complete phase locking, if the locked tuning voltage does not meet the expectation or the external temperature perturbation is large, the tuning voltage calibration can be turned on after the loop is locked at this time. First, it is compared with the target voltage (i.e., the reference voltage) through a hysteresis comparator, and the error information of the tuning voltage is sent to the input terminal of the D flip-flop. A low-frequency clock signal is used to sample the error information. If the sampled error information remains unchanged, it means that the calibration process is still in progress, and the error information represents the calibration direction. If different error information is sampled twice in a row, the exclusive OR logic is performed on the error information of the two times. If the output signal of the logic generates a rising edge, it indicates that the tuning voltage calibration has been completed and the tuning voltage will no longer change.

[0085] Compared with the conventional dual-comparator calibration, the single-hysteresis comparator tuning voltage calibration in the embodiments of the present application does not introduce additional noise. The newly added resistor sizes in the hysteresis comparator structure are relatively large, and the additional resistor thermal noise is very small. Moreover, it can be seen from the simulation results in the same scenario that the tuning voltage ripple of the present application is even smaller than that of the conventional comparator, because the contribution of the additional comparator to the system noise during operation is reduced.

[0086] In another embodiment of the present application, a method for calibrating a tuning voltage is provided. This method can be implemented by an analog circuit. This method can also be applied to the phase-locked loop or calibration device in any of the above embodiments.

[0087] Figure 9 is a flowchart of the method for calibrating a tuning voltage according to an embodiment of the present application, as Figure 9 shown, this method includes the following steps:

[0088] Step S1, comparing a reference voltage with a preset value and the tuning voltage in the phase-locked loop through a hysteresis comparator to generate an error signal;

[0089] Step S2, determining the calibration direction of the tuning voltage according to the error signal, calibrating the tuning voltage based on the calibration direction, and stopping calibrating the tuning voltage when the error signal continuously flips.

[0090] In this embodiment, the reference voltage with a preset value can be adjusted and configured through an external register to achieve controllability of the tuning voltage.

[0091] In some embodiments, the method for calibrating the tuning voltage can also implement the functions in any of the above device embodiments or the phase-locked loop.

[0092] In the embodiments of the present application, the tuning voltage can directly complete the detection and calibration process of the tuning voltage according to the result of a single comparison, saving the required area and power consumption compared with the dual-comparator calibration. The value of the reference voltage can be set by itself, achieving the technical effects of controllable tuning voltage and more stable calibration results, and being less susceptible to the environment, which can solve the problems of limited tuning voltage range of the dual-comparator and continuous power consumption overhead in the related art.

[0093] The embodiments of the present application also have the following advantages: in scenarios where a smaller tuning gain is required, the temperature drift can be covered by this calibration; in scenarios where the linearity limitation of the phase detector module in the phase-locked loop causes differences in the performance of different tuning voltage loops, the tuning voltage can be made controllable through this tuning voltage calibration; in scenarios where the interference signal is strong at the power supply or ground terminal of the phase-locked loop and the tuning voltage ripple is large, the anti-interference effect can be achieved through this calibration method.

[0094] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored. When the computer program is run by a processor, it executes the steps in any one of the above method embodiments.

[0095] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0096] The embodiments of the present application also provide an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0097] In an exemplary embodiment, the above electronic device may further include a transmission device and input / output devices, where the transmission device is connected to the above processor, and the input / output devices are connected to the above processor.

[0098] The specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be repeated here.

[0099] The above are only exemplary embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present application shall be included in the protection scope of the present application.

Claims

1. A calibration device for a tuning voltage, characterized in that, the device includes a voltage comparison module and a calibration module, and an output end of the voltage comparison module is connected to an input end of the calibration module, wherein, the voltage comparison module is configured to compare a reference voltage of a preset value with a tuning voltage in a phase-locked loop through a hysteresis comparator to generate an error signal; the calibration module is configured to determine a calibration direction of the tuning voltage according to the error signal, calibrate the tuning voltage based on the calibration direction, and stop calibrating the tuning voltage when the error signal continuously flips.

2. The device according to claim 1, characterized in that, the calibration module includes a calibration comparison unit and a calibration control unit, an input end of the calibration comparison unit is connected to an output end of the voltage comparison module, and an output end of the calibration comparison unit is connected to an input end of the calibration control unit, wherein, the calibration comparison unit is configured to generate a calibration direction signal and a calibration control signal based on the error signal input from the voltage comparison module and an externally input sampling clock signal, wherein the calibration direction signal is used to indicate a calibration direction of the tuning voltage, and the calibration control signal is used to indicate whether to stop calibrating the tuning voltage; the calibration control unit is configured to calibrate the tuning voltage based on the calibration direction signal and the calibration control signal.

3. The device according to claim 2, characterized in that, the calibration control unit is further configured to perform downward calibration on the tuning voltage when the calibration control signal is at a low level and the calibration direction signal is at a low level; perform upward calibration on the tuning voltage when the calibration control signal is at a low level and the calibration direction signal is at a high level; stop calibrating the tuning voltage when the calibration control signal is at a high level.

4. The device according to claim 2, characterized in that, the calibration comparison unit is further configured to continuously sample the error signal based on the sampling clock signal, and compare whether two adjacent sampling results are consistent. When the two adjacent sampling results are consistent, output the calibration control signal at a low level; when the two adjacent sampling results are inconsistent, output the calibration control signal at a high level; the calibration comparison unit is further configured to generate the calibration direction signal based on the error signal.

5. The device according to claim 4, characterized in that, The calibration comparison unit includes: a first D flip-flop, a second D flip-flop, an exclusive-OR gate, a third D flip-flop, and a NOT gate. Among them, the clock input terminals of the first D flip-flop and the second D flip-flop are connected to the sampling clock signal, the data input terminal of the first D flip-flop is connected to the output terminal of the voltage comparison module, the output terminal of the first D flip-flop is respectively connected to the data input terminal of the second D flip-flop and the first input terminal of the exclusive-OR gate, the output terminal of the second D flip-flop is connected to the second input terminal of the exclusive-OR gate, the output terminal of the exclusive-OR gate is connected to the clock input terminal of the third D flip-flop, the data input terminal of the third D flip-flop is connected to a high-level signal, the input terminal of the NOT gate is connected to the output terminal of the voltage comparison module, and the output terminals of the third D flip-flop and the NOT gate are connected to the input terminal of the calibration control unit; The calibration comparison unit is configured to obtain the current sampling result of the error signal through the first D flip-flop under the control of the sampling clock signal, obtain the previous sampling result of the error signal from the output terminal of the first D flip-flop through the second D flip-flop under the control of the sampling clock signal, determine whether the current sampling result and the previous sampling result are consistent through the exclusive-OR gate, and when the current sampling result and the previous sampling result are consistent, control the third D flip-flop to output the calibration control signal as a low level, and when the current sampling result and the previous sampling result are inconsistent, control the third D flip-flop to output the calibration control signal as a high level; The calibration comparison unit is further configured to perform an inversion operation on the error signal through the NOT gate and output the calibration direction signal.

6. The device according to claim 1, wherein, the device further includes a reference voltage generation module, and the output terminal of the reference voltage generation module is connected to the second input terminal of the voltage comparison module. Among them, the reference voltage generation module is configured to generate a reference voltage of the preset value through a digital register.

7. A phase-locked loop, wherein, the phase-locked loop includes: a phase-locked loop circuit and the calibration device of the tuning voltage in any one of claims 1 to 6 above. The phase-locked loop circuit includes a voltage-controlled oscillator. The input terminal of the calibration device is connected to the input terminal of the voltage-controlled oscillator, and the output terminal of the calibration device is connected to the control terminal of the voltage-controlled oscillator. Among them, the calibration device is configured to calibrate the tuning voltage in the phase-locked loop circuit; the voltage-controlled oscillator is configured to generate a target signal under the control of the calibrated tuning voltage.

8. The phase-locked loop according to claim 7, wherein, The phase-locked loop circuit further includes: a phase detector, a loop filter, and a multi-mode frequency divider. Among them, a first input terminal of the phase detector is connected to an externally input reference clock signal, a second input terminal of the phase detector is connected to an output terminal of the multi-mode frequency divider, an output terminal of the phase detector is connected to an input terminal of the loop filter, an output terminal of the loop filter is connected to an input terminal of the voltage-controlled oscillator, and an output terminal of the voltage-controlled oscillator is connected to an input terminal of the multi-mode frequency divider.

9. The phase-locked loop according to claim 8, wherein, the phase-locked loop further includes: a digital time converter and a frequency-locked loop. Among them, the digital time converter is configured to calibrate the reference clock signal and input the calibrated reference clock into the phase detector and the frequency-locked loop; the frequency-locked loop is configured to assist in locking the target signal based on the calibrated reference clock and a feedback signal output by the multi-mode frequency divider.

10. The phase-locked loop according to claim 8, wherein, the phase detector is an exclusive-OR logic circuit or a sampling detector.

11. The phase-locked loop according to claim 8, wherein, the loop filter includes a proportional path and an integral path. Among them, the integral path includes a transconductance module and an integrating capacitor, and an output terminal of the transconductance module is connected to an input terminal of the calibration device; the calibration device is configured to obtain the tuning voltage from the phase-locked loop circuit through the integral path.

12. A method for calibrating a tuning voltage, wherein, applied to the phase-locked loop in any one of claims 7 to 11 above, the method includes: comparing a reference voltage of a preset value with the tuning voltage in the phase-locked loop through a hysteresis comparator to generate an error signal; determining a calibration direction of the tuning voltage according to the error signal, calibrating the tuning voltage based on the calibration direction, and stopping calibrating the tuning voltage when the error signal continuously flips.

13. A computer-readable storage medium, wherein, a computer program is stored in the storage medium. Among them, when the computer program is run by a processor, the method described in claim 12 is executed.

14. An electronic device includes a memory and a processor, wherein, a computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in claim 12.

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