Verification sequence processing method and device, electronic equipment and storage medium
By setting protection intervals in the verification sequence and determining the puncture position using the rate matching error value, the problem of inaccurate puncture position of the verification sequence in the prior art is solved, and the performance and applicability of the verification sequence are improved.
Patent Information
- Application Number
- CN202311643809.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-01
- Publication Date
- 2025-06-03
AI Technical Summary
When the prior art deletion of the verification sequence, the performance of the verification sequence after the deletion is not effectively guaranteed, and the accuracy and reliability of obtaining the deletion position are insufficient.
By setting the protection interval of the verification sequence, specific position information is locked, the accuracy of the punctured position is improved, and the punctured position is determined by the error value during the rate matching process, ensuring the performance of the target verification sequence.
The accuracy and reliability of the check sequence punctured position is improved, the target verification sequence performance after punctured is ensured, and the robustness and applicability in the rate matching process are enhanced.
Smart Images
Figure CN120090757A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of wireless communication technologies, and in particular, to a method, apparatus, electronic device, and storage medium for processing a check sequence. Background Art
[0002] In related technologies, when puncturing a check sequence, different puncturing matrices are often used to perform different degrees of puncturing on the check sequence to achieve flexible code rate adaptation. The check sequence can also be punctured in a rotation manner or a co-phase puncturing manner. However, in the above technologies, how to ensure the performance of the punctured check sequence is not considered. Therefore, how to improve the accuracy and reliability of obtaining the puncturing positions of the check sequence to ensure the performance of the target check sequence after puncturing has become one of the important research directions. Summary of the Invention
[0003] The present disclosure aims to solve at least one of the technical problems in the related technologies to some extent.
[0004] To this end, the first object of the present disclosure is to propose a method for processing a check sequence. By setting a guard interval of the check sequence, specific position information of the check sequence can be locked and protected, improving the accuracy of obtaining the puncturing positions of the check sequence, ensuring the performance of the target check sequence after puncturing, and improving the robustness and applicability in the rate matching process of the check sequence.
[0005] The second object of the present disclosure is to propose an apparatus for processing a check sequence.
[0006] The third object of the present disclosure is to propose an electronic device.
[0007] The fourth object of the present disclosure is to propose a computer-readable storage medium.
[0008] The fifth object of the present disclosure is to propose a computer program product.
[0009] To achieve the above object, an embodiment of the first aspect of the present disclosure provides a method for processing a check sequence, including: obtaining a check sequence to be processed, and performing at least one rate matching on the check sequence; determining an error value of the check sequence in each rate matching process, and determining a puncturing position of each rate matching of the check sequence according to the error value and a preset interval of the check sequence; and puncturing the check values at the puncturing positions in the check sequence to obtain a target check sequence.
[0010] The method for processing a check sequence according to an embodiment of the present disclosure includes obtaining a check sequence to be processed, performing at least one rate matching on the check sequence, determining an error value of the check sequence in each rate matching process, determining a puncturing position of each rate matching of the check sequence according to the error value and a preset interval of the check sequence, and puncturing the check value at the puncturing position in the check sequence to obtain a target check sequence. Thus, by setting a protection interval for the check sequence, the present disclosure can lock and protect specific position information of the check sequence, improve the accuracy of obtaining the puncturing position of the check sequence, ensure the performance of the target check sequence after puncturing, and improve the robustness and applicability in the rate matching process of the check sequence.
[0011] To achieve the above object, an embodiment of the second aspect of the present disclosure provides a processing device for a check sequence, including: an obtaining module, configured to obtain a check sequence to be processed and perform at least one rate matching on the check sequence; a determining module, configured to determine an error value of the check sequence in each rate matching process and determine a puncturing position of each rate matching of the check sequence according to the error value and a preset interval of the check sequence; and a puncturing module, configured to puncture the check value at the puncturing position in the check sequence to obtain a target check sequence.
[0012] To achieve the above object, an embodiment of the third aspect of the present disclosure provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the method for processing a check sequence according to the embodiment of the first aspect of the present disclosure is implemented.
[0013] To achieve the above object, an embodiment of the fourth aspect of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method for processing a check sequence according to the embodiment of the first aspect of the present disclosure is implemented.
[0014] To achieve the above object, an embodiment of the fifth aspect of the present disclosure provides a computer program product. When the instruction processor in the computer program product executes, the method for processing a check sequence according to the embodiment of the first aspect of the present disclosure is implemented.
[0015] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. Description of the Drawings
[0016] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:
[0017] Figure 1Flow chart of a method for processing a check sequence provided by an embodiment of the present disclosure;
[0018] Figure 2 Flow chart of another method for processing a check sequence provided by an embodiment of the present disclosure;
[0019] Figure 3 Flow chart of another method for processing a check sequence provided by an embodiment of the present disclosure;
[0020] Figure 4 Flow chart of another method for processing a check sequence provided by an embodiment of the present disclosure;
[0021] Figure 5 Schematic diagram of a check sequence provided by an embodiment of the present disclosure;
[0022] Figure 6 Curve schematic diagram of the decoding performance effect of a check sequence provided by an embodiment of the present disclosure;
[0023] Figure 7 Schematic diagram of the structure of a check sequence processing device provided by an embodiment of the present disclosure;
[0024] Figure 8 Block diagram of an electronic device for a method of processing a check sequence shown according to an exemplary embodiment. Detailed implementation manners
[0025] The embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure and should not be construed as limiting the present disclosure.
[0026] The following describes a method for processing a check sequence, a device, an inter-satellite routing calculation system, an electronic device, and a storage medium according to an embodiment of the present disclosure with reference to the accompanying drawings.
[0027] Figure 1 Flow chart of a method for processing a check sequence provided by an embodiment of the present disclosure.
[0028] As Figure 1 shown, the method for processing the check sequence may include the following steps:
[0029] S101, obtain a check sequence to be processed, and perform at least one rate matching on the check sequence.
[0030] It should be noted that for the application scenario of low-earth orbit satellite communication, when transmitting high-rate services such as data services or streaming media, the Turbo coding scheme is usually adopted. During the transmission process, the amount of data in a transmission channel can change within different transmission time intervals, but the configured physical channel capacity is fixed. To match the carrying capacity of the physical channel, the rate matching method is often used to control the generation of different transmission code rates and determine the positions of some data that need to be deleted or repeated in the input parity sequence.
[0031] It should be noted that the present disclosure does not limit the specific manner of obtaining the parity sequence to be processed, which can be selected according to the actual situation.
[0032] Optionally, the information sequence can be encoded to obtain the parity sequence U(m) (m = 1, 2... n) to be processed, where the number of bits of the parity sequence to be processed is n.
[0033] It should be noted that after obtaining the parity sequence to be processed, at least one rate matching can be performed based on the preset code rate of the target parity sequence and the code rate of the parity sequence to be processed.
[0034] S102, determine the error value of the parity sequence in each rate matching process, and determine the puncturing position of the parity sequence in each rate matching according to the error value and the preset interval of the parity sequence.
[0035] Optionally, the present disclosure does not limit the setting of the size and position of the preset interval, which can be set based on the characteristics of the Turbo coding scheme or the actual situation of the target parity sequence.
[0036] It should be noted that when the number of bits of the preset interval of the parity sequence is set to 0, it does not affect the implementation of the solution of the present disclosure, that is, the protection of some parity bits is not considered, and all bits are punctured under the same conditions.
[0037] Optionally, when the parity sequence performs the first rate matching, the initial error value and the error decrement value can be obtained, and the error value of the parity sequence in the first rate matching process can be determined according to the initial error value and the error decrement value.
[0038] Optionally, when the parity sequence performs non-first matching, the error value of the (i - 1)th time and the error increment value can be obtained, and the error value of the parity sequence in the ith rate matching process can be determined according to the error value of the (i - 1)th time and the error increment value, where i is a positive integer and i ≥ 2.
[0039] In the embodiment of the present disclosure, after obtaining the error value of the parity sequence in each rate matching process, the puncturing position of the parity sequence in each rate matching can be determined according to the error value and the preset interval of the parity sequence.
[0040] For example, a current position indication value of a check sequence can be obtained, and in response to the error value being less than zero and the current position indication value not being within a preset interval, the position indicated by the current position indication value is used as the puncturing position.
[0041] S103. Puncture the check value at the puncturing position in the check sequence to obtain a target check sequence.
[0042] In an embodiment of the present disclosure, after obtaining the puncturing position of each rate matching of the check sequence, the check value at the puncturing position in the check sequence can be punctured to obtain a target check sequence v(z) (z = 1, 2... λ), where the number of bits of the target check sequence is λ.
[0043] In summary, according to the method for processing a check sequence in an embodiment of the present disclosure, by obtaining a check sequence to be processed, performing at least one rate matching on the check sequence, determining an error value in each rate matching process of the check sequence, determining the puncturing position of each rate matching of the check sequence according to the error value and a preset interval of the check sequence, and puncturing the check value at the puncturing position in the check sequence to obtain a target check sequence. Thus, the present disclosure can lock and protect specific position information of the check sequence by setting a guard interval of the check sequence, improve the accuracy of obtaining the puncturing position of the check sequence, ensure the performance of the target check sequence after puncturing, and improve the robustness and applicability in the rate matching process of the check sequence.
[0044] As a possible implementation manner, as Figure 2 shown, on the basis of the above steps, the specific process of determining the error value in each rate matching process of the check sequence in step S102 includes the following steps:
[0045] S201. Obtain an initial error value and an error decrement value, and determine the error value in the first rate matching process of the check sequence according to the initial error value and the error decrement value.
[0046] Optionally, when obtaining the initial error value, the first number of bits of a preset interval can be obtained, and the initial error value is obtained according to the first number of bits.
[0047] For example, for the first number of bits T of a preset interval, the initial error value e ini is T / 2, that is, e ini = T / 2.
[0048] Optionally, when obtaining the error decrement value, the second number of bits of the check sequence can be obtained, and the error decrement value is obtained according to the second number of bits.
[0049] For example, for the second number of bits n of the check sequence, the error decrement value emin us is the second number of bits, i.e., e min us = n.
[0050] In an embodiment of the present disclosure, after obtaining the initial error value and the error decrement value, the error value of the check sequence in the first matching rate process can be determined according to the initial error value and the error decrement value.
[0051] For example, when the initial error value is e ini and the error decrement value is e min us , the error value e 1 of the check sequence in the first rate matching process is the difference between the initial error value and the error decrement value, that is: e 1 = e ini - e min us , where the current position indication value m of the check sequence is 1, z = 1; m indicates the position of the bit sequence, m indicates the output bit sequence count, and z is the check bit count value output by the target check sequence.
[0052] S202. Obtain the error value and the error increment value of the (i - 1)-th time, and determine the error value of the check sequence in the i-th rate matching process according to the error value and the error increment value of the (i - 1)-th time, where i is a positive integer and i ≥ 2.
[0053] Optionally, when obtaining the error increment value, the preset third number of bits of the target check sequence can be obtained, and the error increment value can be obtained according to the second number of bits and the third number of bits.
[0054] For example, for the second number of bits n of the check sequence, the third number of bits of the target check sequence is λ, and the error increment value e plus is the difference between the second number of bits and the third number of bits, that is e plus = n - λ.
[0055] In an embodiment of the present disclosure, after obtaining the error value and the error increment value of the (i - 1)-th time, the error value of the check sequence in the i-th rate matching process can be determined according to the error value and the error increment value of the (i - 1)-th time.
[0056] For example, if the check sequence performs the second rate matching, that is, i = 2, the error value of the check sequence in the second rate matching process is e 2 = e 1 + e plus ; if the check sequence performs the third rate matching, that is, i = 3, the error value of the check sequence in the third rate matching process is e 3 = e 2 + e plus .
[0057] As a possible implementation, as Figure 3 shown, based on the above steps, the specific process of determining the puncturing position for each rate matching of the check sequence according to the error value and the preset interval of the check sequence in step S103 above includes the following steps:
[0058] S301, obtain the current position indication value of the check sequence.
[0059] S302, in response to the error value being less than or equal to zero and the current position indication value not being within the preset interval, set the check value indicated by the current position indication value to the target value.
[0060] It should be noted that the present disclosure does not limit the setting of the target value, which can be set according to the actual situation. Optionally, the target value δ can be set to a value other than 0 or 1, that is
[0061] For example, when the current position indication value is 1 and the corresponding error value is e 1 = e ini - e min us , if e 1 ≤0 and the current position indication value is not within the preset interval, then set the check value indicated by the current position indication value to the target value, that is, U(1) = δ.
[0062] In the embodiment of the present disclosure, if at least one of the conditions that the error value is greater than zero and the current position indication value is within the preset interval is satisfied, no operation is performed on the check value indicated by the current position indication value, that is, the position indicated by the current position indication value is not the puncturing position of the check sequence.
[0063] S303, determine the puncturing position for each rate matching of the check sequence from the target value.
[0064] In the embodiment of the present disclosure, the target value δ of the check sequence can be obtained, and the position corresponding to the target value is used as the puncturing position of the check sequence.
[0065] In the embodiment of the present application, before puncturing the check value at the puncturing position in the check sequence to obtain the target check sequence, it is possible to determine whether the check sequence satisfies the rate matching end condition according to the current position indication value and the second number of bits. If the check sequence satisfies the rate matching end condition, puncture the check value at the puncturing position in the check sequence to obtain the target check sequence. If the check sequence does not satisfy the rate matching end condition, continue to determine the puncturing position for the rate matching of the check sequence according to the error value and the preset interval of the check sequence.
[0066] For example, the rate matching end condition can be set such that when the current position indication value is greater than the second number of bits, that is, when m is greater than n, the rate matching end condition is satisfied.
[0067] It should be noted that the higher the correlation degree between the output sequence and the input sequence after rate matching, the more auxiliary decoding information is retained in the punctured sequence, the less information is lost after puncturing, and the higher the target coding reliability. Therefore, a puncturing evaluation criterion based on the maximum information coefficient is introduced in the present disclosure solution.
[0068] As a possible implementation, as Figure 4 shown, on the basis of the above steps, the specific process of obtaining the puncturing evaluation result includes the following steps:
[0069] S401, obtain the maximum information coefficient of the check sequence and the target check sequence.
[0070] For example, for the check sequence to be processed U = (u 1 , u 2 , …, u n ), the punctured target check sequence is V out = (α 1 , α 2 , …, α λ ), where u i (i = 1, 2, …, n) and α j (j = 1, 2, …, λ) respectively represent the i-th bit of the check sequence U and the j-th bit of V out .
[0071] Optionally, the distribution mean of the target check sequence V out can be calculated and compared with the check sequence U. According to the puncturing position index, fill the signal sequence V with card v . Denote the filled signal as V = (v out , v 1 , …, v 2 , …, v n ). For the check sequence U and the filled sequence V, construct a scatter point set map UV , map UV = {(u 1 , s 1 ), (u 2 , s 2 ), …, (u n , s n )}, and map this scatter point set to a scatter plot Pic. For any segmentation method ω g×h, construct \(g\times h\) regions on the scatter plot Pic, where \(g\) and \(h\) are the number of rows and columns of the division respectively, and the scatter point set map can be calculated UV of the mutual information:
[0072] I UV =H(U)+H(V)-H(U,V)
[0073] where, p(u i ,v i ) is the joint probability density of the \(i\)-th and \(j\)-th signals, and p(u i ) and p(v i ) are the marginal probability densities of the \(i\)-th and \(j\)-th signals respectively.
[0074] where, for p(u i ,v i ) and p(u i ) the acquisition process is:
[0075] First, according to the two-dimensional histogram estimation method, it can be known that where \((u i ,v i ) ∈ Ω f (f = 1, 2, …, g×h), Ω f is the \(f\)-th region under the division ω g×h , m is the dimension of the signal sequence, num(Ω f ) is the number of scatter points in the region Ωf, and surfΩf is the area of the region Ωf.
[0076] Secondly, in order to obtain p(u i ), denote where, is the normalized value of u i . On this basis, the interval Δ u = [u min ,u max can be constructed and equally spaced divided with a length of . Δ η (η = 1, 2, …, θ + 1) is the η-th sub-interval, where θ is the number of divisions, and Δ η = [u min + (η - 1)len, u min + ηlen]. According to the one-dimensional histogram estimation method, it can be obtained that:
[0077]
[0078] where, num(Δ η ) is the normalized original signal set in which is located in Δη The number of scatter points within.
[0079] Then, traverse all the partitioning methods under the dimension g×h, and calculate the corresponding mutual information about map UV in sequence, and define the maximum value element in the obtained mutual information set as the partitioning mutual information I g×h (U, V). To compare the mutual dependencies between signals under different partitioning dimensions, normalize I g×h (U, V):
[0080] Finally, construct the signal dependency feature matrix M(U, V) = m UV , and define the maximum value in the matrix M(U, V) as the maximum information coefficient mic g×h of the signal sets U and V, uv , where ζ(m) = m 0.6 .
[0081] S402. Obtain the puncturing evaluation result according to the maximum information coefficient.
[0082] In the embodiments of the present disclosure, after obtaining the maximum information coefficient, the puncturing evaluation result can be obtained according to the maximum information coefficient.
[0083] For example, a maximum information coefficient threshold can be set. In response to the maximum information coefficient being greater than or equal to the maximum information coefficient threshold, the puncturing evaluation result is "excellent"; in response to the maximum information coefficient being less than the maximum information coefficient threshold, the puncturing evaluation result is "poor".
[0084] In summary, the method for processing the check sequence proposed by the present disclosure can, based on the maximum information coefficient of the check sequence and the target check sequence, evaluate the quality of the puncturing result by comparing the maximum information coefficients, make up for the insufficiency of the current puncturing evaluation criterion, and provide strong algorithmic theoretical support.
[0085] The following explains the specific process of the method for processing the check sequence proposed by the embodiments of the present disclosure.
[0086] For example, as Figure 5 shown, in the application scenario of a communication system using Turbo coding, after Turbo coding is completed, the encoder register can be reset to zero by embedding a certain number of tail bits at the end of the data block. The preset interval can be defined as the respective tail bits of the two encoders in Turbo coding, and the default data stream form is arranged according to the check bit sequences of the first and second encoders, that is, the check sequence to be processed is Z k = [Z k1 Tail1 Z k2 Tail 2 , where Z k1 is the first path check sequence, and the corresponding first path tail bit sequence is Tail 1 , Z k2 is the second path check sequence, and the corresponding second path tail bit sequence is Tail 2 . The number of common bits in the two path check sequences with the same length is p, and the number of bits of the tail bits (preset interval) is t. Z k1 is p / 2, and the number of bits of Z k2 is, and the preset intervals respectively correspond to the positions [p / 2 + 1, p / 2 + t / 2] and [p + t / 2, p + t].
[0087] Optionally, the check sequence to be processed can be defined as U(k) (k = 1, 2,..., n). According to the above data description, k = p + t, and the target check sequence is V(i) (i = 1, 2,..., λ). U(k) = U k , V(i) = V k . k is the position indication value of the current check bit, and i is the check bit count value output by the target check sequence. Among them, the error increment value is e plus = p + t - λ, the error decrement value is e min us = p + t, and the initial error value e ini = t / 2.
[0088] For example, the specific process of the processing method of the check sequence may include the following steps:
[0089] (1) Calculate the initial error value e 0 = e ini . In this case, the position indication value k of the current check bit is 1, and the check bit count value i output by the target check sequence is 1;
[0090] (2) Determine the error value of the check sequence in the first rate matching process, which is determined according to the error decrement value and the initial error value, that is, e 1 = e 0 - e min us ;
[0091] (3) Determine whether e 1 <= 0 and the current position k is not within the ranges [p / 2 + 1, p / 2 + t / 2] and [p + t / 2, p + t]:
[0092] If e 1If <=0 and the current position indication value k is not within the ranges [p / 2 + 1, p / 2 + t / 2] and [p + t / 2, p + t], then set U(k) to the target value δ, where the target value δ can be set to any value other than 1 and 0. For example, set U(k) to the target value δ = -1, and update the error value e 2 = e 1 + e plus ;
[0093] If e 1 > 0 or the current position indication value k is within the ranges [p / 2 + 1, p / 2 + t / 2] and [p + t / 2, p + t] or e 1 > 0 and the current bit indication value k is within the ranges [p / 2 + 1, p / 2 + t / 2] and [p + t / 2, p + t], then no operation may be performed on the bit at the current position, or the corresponding position information may be stored in the output information sequence V(i) = U(k), and the check bit count value of the target check sequence output is updated as i = i + 1.
[0094] (4) Update the position indication value of the current check bit as k = k + 1;
[0095] (5) Determine whether k ≤ n(p + t). If k ≤ n, repeat steps (2) to (4), otherwise end the rate matching.
[0096] (6) Obtain the target value in the check sequence, use the position corresponding to the target value δ as the puncturing position, and puncture the check values at the puncturing positions in the check sequence to obtain the target check sequence V(i).
[0097] Furthermore, based on the requirements of the Turbo high code rate service for low earth orbit satellite narrowband communication, two groups of Turbo - encoded data can be randomly selected as test cases, and a large number of simulation verifications with random noise addition are carried out for decoding performance. One test case is the service data with an input Turbo - encoded information length of 200 and a target code rate of 0.78 after rate - matching puncturing, and the other test case is the service data with an input Turbo - encoded information length of 425 and a target code rate of 0.8 after rate - matching puncturing.
[0098] For example, for an Additive White Gaussian Noise (AWGN) channel, under Binary Phase Shift Keying (BPSK) modulation, using the Maximum a posteriori estimation (MAP) algorithm, under the simulation conditions of a maximum of 8 decoding iterations, as Figure 6As shown, a comparison curve graph of the decoding performance effects of the check sequence of the prior art solution and the technical solution of the present disclosure is determined, where Figure 6 In the figure, the solid line is the performance effect curve of the prior art solution, and the dashed line is the performance effect curve of the technical solution of the present disclosure. By analyzing the above comparison curve graph of performance effects, it can be known that: the problem of the error floor of the target high code rate Turbo code obtained by puncturing in the technical solution of the present disclosure is effectively solved, and the convergence is faster. At the same time, by calculating the maximum information coefficient of the punctured target check sequence and the check sequence before puncturing under two different test cases, the maximum information coefficient before and after rate matching in this solution is significantly higher than the maximum information coefficient in the prior art solution, and the difference in the maximum information coefficient is relatively large when the code rate is 0.78, and the difference in the maximum information coefficient is relatively small when the code rate is 0.8.
[0099] In summary, for the method for processing the check sequence proposed by the present disclosure, by setting a preset interval of the check sequence, the position information of specific positions of the check sequence can be locked and protected, the accuracy of obtaining the puncturing position of the check sequence is improved, the performance of the punctured target check sequence is ensured, and the size and position of the preset interval can be flexibly configured, improving the robustness and applicability in the rate matching process of the check sequence. And based on the maximum information coefficient of the check sequence and the target check sequence, the quality of the puncturing result can be evaluated, making up for the insufficiency of the current puncturing evaluation criterion, and providing strong algorithm theory support.
[0100] To implement the above embodiments, the present disclosure also proposes a device for processing a check sequence.
[0101] Figure 7 It is a schematic structural diagram of a device for processing a check sequence provided by an embodiment of the present disclosure.
[0102] As Figure 7 shown, the check sequence processing device 700 includes: an acquisition module 701, a determination module 702, and a puncturing module 703.
[0103] The acquisition module 701 is configured to acquire a check sequence to be processed and perform at least one rate matching on the check sequence;
[0104] The determination module 702 is configured to determine an error value of the check sequence in each rate matching process, and determine a puncturing position of each rate matching of the check sequence according to the error value and the preset interval of the check sequence;
[0105] The puncturing module 703 is configured to puncture the check values at the puncturing positions in the check sequence to obtain a target check sequence.
[0106] In one embodiment of the present disclosure, the determining module 702 is configured to: obtain an initial error value and an error decrement value, and determine an error value of the check sequence in the first rate matching process according to the initial error value and the error decrement value; obtain the error value and the error increment value of the (i - 1)-th time, and determine the error value of the check sequence in the i-th rate matching process according to the error value of the (i - 1)-th time and the error increment value, where i is a positive integer and i ≥ 2.
[0107] In one embodiment of the present disclosure, the determining module 702 is configured to: obtain the number of first bits of the preset interval; and obtain the initial error value according to the number of first bits.
[0108] In one embodiment of the present disclosure, the determining module 702 is configured to: obtain the number of second bits of the check sequence; and obtain the error decrement value according to the number of second bits.
[0109] In one embodiment of the present disclosure, the determining module 702 is configured to: obtain the number of third bits preset for the target check sequence; and obtain the error increment value according to the number of second bits and the number of third bits.
[0110] In one embodiment of the present disclosure, the determining module 702 is configured to: obtain a current position indication value of the check sequence; in response to the error value being less than or equal to zero and the current position indication value not being within the preset interval, set the check value indicated by the current position indication value to a target value; and determine a puncturing position for each rate matching of the check sequence from the target value.
[0111] In one embodiment of the present disclosure, the apparatus 700 is further configured to: determine whether the check sequence meets a rate matching end condition according to the current position indication value and the number of second bits; if the check sequence meets the rate matching end condition, puncture the check value at the puncturing position in the check sequence to obtain a target check sequence; if the check sequence does not meet the rate matching end condition, continue to determine the puncturing position of the rate matching of the check sequence according to the error value and the preset interval of the check sequence.
[0112] In one embodiment of the present disclosure, the apparatus 700 is further configured to: obtain a maximum information coefficient of the check sequence and the target check sequence; and obtain a puncturing evaluation result according to the maximum information coefficient.
[0113] It should be noted that the foregoing explanation of the embodiments of the processing method for the check sequence is also applicable to the processing apparatus for the check sequence in this embodiment, and will not be elaborated here.
[0114] The processing device for the check sequence according to the embodiments of the present disclosure obtains the check sequence to be processed, performs at least one rate matching on the check sequence, determines the error value in each rate matching process of the check sequence, determines the puncturing position of each rate matching of the check sequence according to the error value and the preset interval of the check sequence, punctures the check value at the puncturing position in the check sequence to obtain the target check sequence. Thus, by setting the protection interval of the check sequence, the present disclosure can lock and protect specific position information of the check sequence, improve the accuracy of obtaining the puncturing position of the check sequence, ensure the performance of the target check sequence after puncturing, and improve the robustness and applicability in the rate matching process of the check sequence.
[0115] To implement the above embodiments, the present application further provides an electronic device, as Figure 8 shown Figure 8 is a block diagram of an electronic device for a method of processing a check sequence according to an exemplary embodiment.
[0116] As Figure 8 shown, the above electronic device 800 includes:
[0117] A memory 810 and a processor 820, and a bus 830 connecting different components (including the memory 810 and the processor 820). The memory 810 stores a computer program, and when the processor 820 executes the program, the method for processing the check sequence according to the embodiments of the present disclosure is implemented.
[0118] The bus 830 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
[0119] The electronic device 800 typically includes a variety of electronic device-readable media. These media can be any available media accessible by the electronic device 800, including volatile and non-volatile media, removable and non-removable media.
[0120] The memory 810 may further include a computer system-readable medium in the form of volatile memory, such as random access memory (RAM) 840 and / or cache memory 850. The electronic device 800 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 860 may be used to read and write non-removable, non-volatile magnetic media ( Figure 8not shown, commonly referred to as a "hard disk drive"). Although Figure 8 not shown in Figure 8 , a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical medium) may be provided. In these cases, each drive may be connected to the bus 830 through one or more data medium interfaces. The memory 810 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments of the present disclosure.
[0121] A program / utility 880 having a set (at least one) of program modules 870 may be stored, for example, in the memory 810. Such program modules 870 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 870 generally perform the functions and / or methods in the embodiments described in the present disclosure.
[0122] The electronic device 1300 may also communicate with one or more external devices 890 (such as a keyboard, a pointing device, a display 891, etc.), and may also communicate with one or more devices that enable a user to interact with the electronic device 800, and / or communicate with any device that enables the electronic device 800 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication may be carried out through an input / output (I / O) interface 892. And, the electronic device 800 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 893. As Figure 8 shown, the network adapter 893 communicates with other modules of the electronic device 800 through the bus 830. It should be understood that although Figure 8 not shown in Figure 8 , other hardware and / or software modules may be used in combination with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.
[0123] The processor 820 executes various functional applications and data processing by running the programs stored in the memory 810.
[0124] It should be noted that for the implementation process and technical principle of the electronic device in this embodiment, refer to the foregoing explanation of the processing method of the check sequence of the embodiments of the present disclosure, which will not be elaborated here.
[0125] To implement the above embodiments, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processing method of the check sequence described in the above embodiments is implemented.
[0126] To implement the above embodiments, the present disclosure also provides a computer program product. When the instructions in the computer program product are executed by a processor, the processing method of the check sequence described in the above embodiments is executed.
[0127] In the description of this specification, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0128] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0129] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.
Claims
1. A method for processing a check sequence, characterized in that, the method includes: obtaining a check sequence to be processed and performing at least one rate matching on the check sequence; determining an error value of the check sequence in each rate matching process, and determining a puncturing position of each rate matching of the check sequence according to the error value and a preset interval of the check sequence; puncturing the check values at the puncturing positions in the check sequence to obtain a target check sequence.
2. The method according to claim 1, characterized in that, the determining of the error value of the check sequence in each rate matching process includes: obtaining an initial error value and an error decrement value, and determining the error value of the check sequence in the first rate matching process according to the initial error value and the error decrement value; obtaining the error value of the (i - 1)-th time and an error increment value, and determining the error value of the check sequence in the i-th rate matching process according to the error value of the (i - 1)-th time and the error increment value, where i is a positive integer and i ≥ 2.
3. The method according to claim 2, characterized in that, the obtaining of the initial error value includes: obtaining the number of first bits of the preset interval; obtaining the initial error value according to the number of first bits.
4. The method according to claim 2, characterized in that, the obtaining of the error decrement value includes: obtaining the number of second bits of the check sequence; obtaining the error decrement value according to the number of second bits.
5. The method according to claim 4, characterized in that, the obtaining of the error increment value includes: obtaining the number of third bits preset for the target check sequence; obtaining the error increment value according to the number of second bits and the number of third bits.
6. The method according to claim 1, characterized in that, the determining of the puncturing position of each rate matching of the check sequence according to the error value and the preset interval of the check sequence includes: obtaining a current position indication value of the check sequence; in response to the error value being less than or equal to zero and the current position indication value not being within the preset interval, setting the check value indicated by the current position indication value as a target value; determining the puncturing position of each rate matching of the check sequence from the target value.
7. The method according to any one of claims 1 - 6, characterized in that, before the puncturing of the check values at the puncturing positions in the check sequence to obtain a target check sequence, it includes: judging whether the check sequence meets a rate matching end condition according to the current position indication value and the number of second bits; if the check sequence meets the rate matching end condition, puncturing the check values at the puncturing positions in the check sequence to obtain a target check sequence; if the check sequence does not meet the rate matching end condition, continue to determine the puncturing position of the rate matching of the check sequence according to the error value and the preset interval of the check sequence.
8. The method according to any one of claims 1 - 6, characterized in that, After puncturing the parity values at the puncturing positions in the parity sequence to obtain a target parity sequence, the method further includes: Obtaining the maximum information coefficient of the parity sequence and the target parity sequence; Obtaining a puncturing evaluation result according to the maximum information coefficient.
9. An apparatus for processing a parity sequence, wherein, the apparatus includes: an obtaining module, configured to obtain a parity sequence to be processed and perform at least one rate matching on the parity sequence; a determining module, configured to determine an error value in each rate matching process of the parity sequence, and determine a puncturing position of each rate matching of the parity sequence according to the error value and a preset interval of the parity sequence; a puncturing module, configured to puncture the parity values at the puncturing positions in the parity sequence to obtain a target parity sequence.
10. The apparatus according to claim 9, wherein, the determining module is configured to: obtain an initial error value and an error decrement value, and determine an error value of the parity sequence in the first rate matching process according to the initial error value and the error decrement value; obtain an error value and an error increment value of the (i-1)-th time, and determine an error value of the parity sequence in the i-th rate matching process according to the error value of the (i-1)-th time and the error increment value, where i is a positive integer and i≥2.
11. The apparatus according to claim 10, wherein, the determining module is configured to: obtain a first number of bits of the preset interval; obtain the initial error value according to the first number of bits.
12. The method according to claim 10, wherein, the determining module is configured to: obtain a second number of bits of the parity sequence; obtain the error decrement value according to the second number of bits.
13. The apparatus according to claim 12, wherein, the determining module is configured to: obtain a third number of bits preset for the target parity sequence; obtain the error increment value according to the second number of bits and the third number of bits.
14. The apparatus according to claim 9, wherein, the determining module is configured to: obtain a current position indication value of the parity sequence; in response to the error value being less than or equal to zero and the current position indication value not being within the preset interval, set the parity value indicated by the current position indication value to a target value; determine the puncturing position of each rate matching of the parity sequence from the target value.
15. The apparatus according to any one of claims 9-14, wherein, the apparatus is further configured to: judge whether the parity sequence meets a rate matching end condition according to the current position indication value and the second number of bits; if the parity sequence meets the rate matching end condition, puncture the parity values at the puncturing positions in the parity sequence to obtain a target parity sequence; if the parity sequence does not meet the rate matching end condition, continue to determine the puncturing position of the rate matching of the parity sequence according to the error value and the preset interval of the parity sequence.
16. The apparatus according to any one of claims 1-6, wherein, the apparatus is further configured to: Obtain the maximum information coefficient of the obtained check sequence and the target check sequence; Obtain a puncturing evaluation result according to the maximum information coefficient.
17. An electronic device, characterized in that, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the processing method of the check sequence according to any one of claims 1-8 is implemented.
18. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the processing method of the check sequence according to any one of claims 1-8 is implemented.