Manufacturing method for improving single-particle burning resistance of trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention discloses a manufacturing method for improving single event burnout resistance of a trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and belongs to the technical field of semiconductor power devices. On the basis of a trench type MOSFET process, the anti-radiation performance of a device product is improved through process optimization, so that the device product adapts to a space environment of ionizing radiation in space, and the high reliability index of the device product is improved. The method is technically characterized in that the well region is injected before the groove is etched, so that the gate oxide process is prevented from being influenced; deep hole injection is realized by utilizing TC photoetching, and the hole extraction capability of a body region under the condition of heavy ion radiation is improved; the bottom of the gate trench is locally oxidized and thickened, so that the single-particle gate penetration resistance of the device is improved; and the gate oxidation process adopts a low-temperature wet oxygen process, so that the total dose resistance of the device is improved. By modifying the process steps and the process conditions, deepening hole injection is achieved, the single particle burning resistance is improved, the anti-radiation performance index of an MOSFET device is met, and the environment requirement of the aerospace field is met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and particularly to a manufacturing method for improving the single-event burnout resistance of trench MOSFETs. Background Art

[0002] Trench MOSFET is a new type of discrete power MOSFET power device. Compared with the performance of bipolar power devices, it has the advantages of low conduction loss, high operating frequency, being a voltage-controlled device, and having a simple control circuit, and is increasingly valued by the industrial community. Compared with planar MOSFETs, trench MOSFETs can achieve smaller cell sizes and higher current densities, improving the current-carrying capacity and switching performance of the device, especially having more obvious advantages in the field of medium and low voltage power MOSFETs.

[0003] With the exploration of the space field by humans, electronic components not only need excellent electrical performance but also need to cope with the harsh environment in space, such as gamma rays, solar winds, etc. In the space ionization radiation environment, the radiation effects generated by the device mainly include total dose radiation effects, single-event burnout, and single-event gate rupture. Therefore, radiation hardening design is required for the device. Summary of the Invention

[0004] The purpose of the present invention is to provide a manufacturing method for improving the single-event burnout resistance of trench MOSFETs to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a manufacturing method for improving the single-event burnout resistance of trench MOSFETs, including: Growing a first silicon oxide layer on a silicon epitaxial wafer, implementing a P-well through ion implantation, and performing high-temperature drive-in on the P-well; then depositing a first silicon nitride layer; Digging a trench structure on the wafer and filling and polishing the trench structure with silicon dioxide; Etching into the silicon epitaxial wafer at the position where the gate trench is to be formed on the wafer to form a gate trench; Depositing a layer of silicon oxide and silicon nitride in the gate trench, etching away the silicon nitride on the wafer surface and at the bottom of the gate trench, and growing silicon oxide at the bottom of the gate trench to achieve local oxidation thickening at the bottom; Removing the silicon nitride layer on the sidewall of the gate trench, controlling the wet etching time of the oxide layer, and only retaining the thickened silicon oxide layer at the bottom of the gate trench; Growing gate oxide using a low-temperature wet oxygen process, depositing in-situ polycrystal in the gate trench, and etching away the polycrystal on the silicon surface through a gate polycrystal back-etching process; Implementing source injection and activation through N+ lithography and using ion implantation; depositing a dielectric layer on the surface and performing a planarization process; Using hole lithography, perform the first step of dielectric hole etching and silicon hole etching. Inject P-type high-concentration impurities into the silicon surface at the bottom of the hole using hole injection, and inject P-type medium-concentration doping into the deep body region. Perform thermal activation through rapid annealing to form the body region lead-out; Using tungsten filling and polishing, achieve the metal lead-out of the contact hole; through metal deposition, lithography and etching, achieve metal interconnection and complete the overall device.

[0006] In one embodiment, the trench structure has an inclination angle, including a strip-shaped gate structure and a checkerboard gate structure, and the depth range is 0.5~1 µm.

[0007] In one embodiment, the thickness of the first silicon nitride layer is 1000 Å~2000 Å.

[0008] In one embodiment, the ion implantation of the P well is element B, the implantation energy is 50~120 Kev, and the dose is 1E13~5E13 per cm 2 .

[0009] In one embodiment, the depth of the gate trench is 1~2 µm.

[0010] In one embodiment, when growing silicon oxide at the bottom of the gate trench to locally oxidize and thicken the bottom, a partial silicon oxide layer is formed on the sidewall of the gate trench at the same time, and then the silicon oxide layer on the sidewall of the gate trench is removed using the phosphoric acid process.

[0011] In one embodiment, in the process of realizing source injection and activation, the injection elements are As / P, the injection energy is 60~100 Kev, and the injection dose is 5E15~1E16 per cm 2 .

[0012] In a manufacturing method for improving the single-event burnout resistance of trench-type MOSFETs provided by the present invention, the well region implantation and push-junction process are advanced to avoid affecting the gate oxide process; use the first photolithography etching to define the gate trench and the hole contact area to achieve self-alignment at two positions; through the first trench etching, finally realize the deep hole process to improve the ability to extract holes during heavy ion radiation; considering the requirement of anti-single-event gate breakdown, oxidize and thicken the bottom of the gate trench; for the requirement of the total dose resistance of the gate oxide itself, a low-temperature wet oxygen process needs to be used in the process. The present invention can realize products with improved single-event burnout resistance of trench-type MOSFETs by optimizing the process steps and process flow under the condition of limited increase in process difficulty and manufacturing cost. Description of the Drawings

[0013] Figure 1 is a schematic diagram of P well implantation and push-junction; Figure 2 This is a schematic diagram of the structure after TC photolithography and etching; Figure 3 It is a schematic diagram of the structure after mechanical grinding of the surface; Figure 4 This is a schematic diagram of the structure of GT after photolithography and etching; Figure 5 It is a schematic diagram of the groove bottom thickening process structure; Figure 6 It is a schematic diagram of gate oxide growth and gate polycrystalline back etching; Figure 7 This is a schematic diagram of N+ injection and activation; Figure 8 It is a schematic diagram of dielectric deposition and surface flattening; Figure 9 It is a schematic diagram of the hole corrosion and hole injection activation structure; Figure 10 This is a schematic diagram of device interconnection completed by metal lithography / etching. DETAILED DESCRIPTION

[0014] The following is a further detailed description of a manufacturing method for improving the single-particle burnout resistance of a trench-type MOSFET proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0015] The radiation-resistant trench-type MOSFET device is a three-terminal discrete device. The front of the wafer is divided into two parts: the source region (Source) and the gate region (Gate). These two regions are isolated from the outside world by trenches or field oxygen. The drain region (Drain) of the device is on the back of the wafer. The process method of the present invention is mainly aimed at the wafer source; the gate is led out to the edge of the tube core through the polycrystalline in the trench, and then connected by punching contact holes and metal interconnections on it; the drain only needs to be thinned and metal-plated on the back to lead out, which is understood by those skilled in the art, so the present invention will not describe it. The present invention is mainly a process processing technology proposed for the cell area, and a trench isolation ring is used on the periphery of the entire tube core area to achieve junction termination.

[0016] The present invention provides a manufacturing method for trench type MOSFET that is resistant to single particle burnout. On the basis of achieving the performance of reducing on-resistance, the radiation resistance performance is reinforced, and the quality of trench type MOSFET that is resistant to single particle burnout is effectively improved by improving some designs and processes.

[0017] The radiation-resistant trench MOSFET process is completed by the following method: Taking the N-type device as an example, the P-type device can be obtained by corresponding methods. First, grow a first silicon oxide layer 2 on the silicon epitaxial wafer 1, where the thickness of the first silicon oxide layer 2 is 200 Å to 500 Å; through the ion implantation process, perform P-well (PW) implantation, where B element is implanted, the energy is 50 - 120 Kev, and the dose is 1E13 - 5E13 atoms / cm 2 ; perform a high-temperature drive-in process on the P-type well implantation; then form an epitaxial silicon-silicon oxide-silicon nitride three-layer thin film structure by chemical vapor deposition of the first silicon nitride layer 3, where the thickness of the first silicon nitride layer 3 is 1000 Å to 2000 Å, as Figure 1 shown.

[0018] Through the TC trench lithography and etching process, dig out a trench structure with a certain tilt angle and a certain depth on the wafer. The depth of this trench structure is 0.5 - 1 µm, as Figure 2 shown; where TC trench is: the lithography definition level of the trench pattern, etching a relatively shallow trench.

[0019] After completing the first trench process, use the method of high-density plasma chemical vapor deposition to fill the trench structure with silicon dioxide 4, and then remove the surface silicon dioxide layer by chemical mechanical polishing, as Figure 3 shown.

[0020] Using the GT trench lithography and etching process, etch into the silicon epitaxial wafer 1 at the place on the wafer that needs to be the gate trench to form a gate trench 5 (longitudinal channel region) with a certain depth and morphology. The total depth range is 1 - 2 µm, as Figure 4 shown; where GT trench is: first etch off the oxide layer in the shallow trench, and then further etch off the silicon to deepen the trench to form a gate trench.

[0021] After completing the gate trench etching, remove the GT photoresist, and deposit a layer of silicon oxide layer and silicon nitride layer in the gate trench 5. Using dry etching anisotropy, etch off the silicon nitride layer on the surface of the wafer and the bottom of the gate trench 5, and the silicon nitride remains on the sidewalls of the gate trench 5. Then, through the thermal oxidation process, grow a silicon oxide layer at the bottom of the gate trench to achieve local oxidation thickening at the bottom and improve the single-event gate rupture resistance of the trench type. At this time, a partial silicon oxide layer is also formed on the sidewalls of the gate trench. Use the phosphoric acid and hydrofluoric acid process to remove the silicon nitride layer and the thin silicon oxide layer on the sidewalls of the gate trench 5, and control the wet etching time of the oxide layer, as Figure 5 shown, only retaining the thickened silicon oxide layer at the bottom of the gate trench 5.

[0022] The gate oxide is grown using a low-temperature wet oxygen process. Considering the requirements for radiation resistance characteristics, the gate oxide layer is generally grown using a low-temperature wet oxygen process, with a thickness of 300 - 800 Å and a growth temperature of 700 - 1000 °C. This step also forms silicon oxide on the sidewalls of the gate trench 5; in-situ polycrystal 6 is deposited in the gate trench 5 by chemical vapor deposition. The polysilicon on the silicon surface is etched away through a gate polysilicon etch-back process, as Figure 6 shown.

[0023] Through N+ lithography and ion implantation, source injection is achieved and activated, realizing the source contact region in the cell area. The implanted elements are As / P, the implantation energy is 60 - 100 Kev, and the implantation dose is 5E15 - 1E16 atoms / cm 2 , as Figure 7 shown.

[0024] So far, the processing of the front-end device process has been completed. Then, a dielectric layer 7 is deposited on the surface by chemical vapor deposition and planarized, as Figure 8 shown.

[0025] Using via lithography, the first step of dielectric via etching and silicon via etching is carried out. P-type high-concentration impurities are implanted into the silicon surface at the bottom of the via using via injection, and P-type medium-concentration doping is implanted into the deep body region. Finally, thermal activation is carried out through rapid annealing to form the body region lead-out, as Figure 9 shown. Since a shallow trench is etched in the first TC silicon, it ensures that the shallow trench and the deep trenches etched twice are self-aligned, improving the control accuracy; when performing via injection, a deeper ion implantation depth can be achieved, thereby improving the hole extraction ability under heavy ion radiation; secondly, this silicon trench is defined by a photomask and is located at the center of the left and right gate trenches, with the best extraction effect.

[0026] Using tungsten 8 filling and grinding, metal lead-out of the contact hole is achieved. Through metal 9 deposition, lithography, and etching, metal interconnection is achieved, completing the overall device as Figure 10 shown.

[0027] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A method for improving the single-event burnout resistance of a trench-type MOSFET, characterized in that: include: A first silicon oxide layer is grown on the silicon epitaxial wafer, a P-well is realized by ion implantation, and a high-temperature push-junction is performed on the P-well; depositing a first silicon nitride layer; A trench structure is dug out on the wafer, and the trench structure is filled with silicon dioxide and ground; The position on the wafer where the gate trench is required is etched into the silicon epitaxial wafer to form a gate trench; Depositing a layer of silicon oxide and silicon nitride in the gate trench, etching away the silicon nitride on the wafer surface and at the bottom of the gate trench, growing silicon oxide at the bottom of the gate trench, and achieving local oxidation thickening at the bottom; Remove the silicon nitride layer on the sidewall of the gate trench, control the wet etching time of the oxide layer, and only retain the thickened silicon oxide layer at the bottom of the gate trench; The gate oxide is grown using a low temperature wet oxygen process, in-situ polycrystalline is deposited in the gate trench, and the silicon surface polycrystalline is etched away using a gate polycrystalline etch-back process; Through N+ photolithography and ion implantation, source electrode is implanted and activated; a dielectric layer is deposited on the surface and planarized; The first step of dielectric hole etching and silicon hole etching is performed by hole photolithography, and P-type high-concentration impurities are injected into the silicon surface at the bottom of the hole by hole injection, and P-type medium-concentration doping is injected into the deep body region, and thermal activation is performed by rapid annealing to form body region leads; Tungsten filling and grinding are used to realize metal lead-out of contact holes; metal interconnection is achieved through metal deposition, photolithography and corrosion to complete the overall device.

2. A method for manufacturing a trench type MOSFET to improve single event burnout resistance as claimed in claim 1, characterized in that: The trench structure has an inclined angle, includes a stripe-type gate structure and a triangle-type gate structure, and has a depth range of 0.5-1µm.

3. A method for manufacturing a trench type MOSFET to improve single event burnout resistance as claimed in claim 1, characterized in that: The thickness of the first silicon nitride layer is 1000Å~2000Å.

4. The manufacturing method for improving the single event burnout resistance of trench type MOSFET according to claim 1, characterized in that: The ions implanted into the P well are B elements, with an implantation energy of 50-120 KeV and a dose of 1E13-5E13 ions / cm 2 .

5. The manufacturing method for improving the single event burnout resistance of trench type MOSFET according to claim 1, characterized in that: The depth of the gate trench is 1-2 μm.

6. The manufacturing method for improving the single event burnout resistance of trench type MOSFET according to claim 1, characterized in that: When silicon oxide is grown at the bottom of the gate trench to partially oxidize and thicken the bottom, the sidewalls of the gate trench are protected by silicon nitride, and only the bottom of the trench is oxidized and thickened. After the silicon oxide layer at the bottom of the trench is formed, the silicon nitride layer and thin silicon oxide layer on the sidewalls of the gate trench are removed using phosphoric acid and hydrofluoric acid processes, and most of the bottom oxide layer is retained.

7. The method for manufacturing a trench type MOSFET to improve single event burnout resistance as claimed in claim 1, characterized in that: In the process of implementing source injection and activation, the injection element is As / P, the injection energy is 60-100 KeV, and the injection dose is 5E15-1E16 cells / cm 2 .

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