Method for monitoring and representing double-peak effect of MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention discloses a method for monitoring and representing a double-peak effect of an MOS (Metal Oxide Semiconductor) transistor. The method comprises the following steps of: testing a first IdVg curve of the MOS transistor under the condition that back gate voltage is not applied; and testing a second IdVg curve under the condition of adding back gate voltage. And obtaining a first peak grid voltage and a second peak grid voltage corresponding to double peaks of the MOS transistor according to the second IdVg curve. And performing voltage mapping, including obtaining first and second drain currents corresponding to the first and second peak gate voltages from the second IdVg curve, and obtaining third and fourth gate voltages corresponding to the currents from the first IdVg curve. And performing bimodal characterization value calculation, namely obtaining a bimodal characterization value from a first voltage difference between the second peak grid voltage and the first peak grid voltage and a second voltage difference between the fourth grid voltage and the third grid voltage through the first voltage difference and the second voltage difference. And performing double-peak effect judgment: when the double-peak characterization value is greater than 0, judging that the double-peak effect exists, otherwise, judging that the double-peak effect does not exist. According to the invention, the double-peak effect of the transistor can be monitored on line and evaluated in time.

Description

Technical Field

[0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for monitoring and characterizing a bimodal effect of a MOS transistor. Background Art

[0002] Due to the development of submicron technology, the transition between the active area and the isolation area becomes more abrupt, resulting in a significant parasitic corner effect and early turn-on of the parasitic transistor, manifested as a double-peak effect of the IdVg curve, which greatly increases the subthreshold leakage.

[0003] There are two main reasons for the generation of parasitic transistors: one is the difference in doping between the center and edge of the transistor due to the segregation of boron to the adjacent STI oxide; the other is that the high mechanical stress of silicon at the junction of the STI and the active area causes the thickness of the gate oxide to decrease at the corner, making the threshold voltage of the parasitic transistor at the edge lower than the threshold voltage of the transistor itself. In order to solve this double peak problem, many solutions have been proposed. The most common method is to control the sharp corner passivation of the STI top or increase the doping concentration at the edge of the channel.

[0004] At present, the research on the bimodal effect is mostly focused on understanding and correcting the process steps that lead to this phenomenon, but less on characterizing and modeling it. In existing methods, the characterization of the bimodal effect mainly observes the hump phenomenon of the IdVg curve. This main characterization method has a lag and cannot provide timely feedback on the phenomenon. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method for monitoring and characterizing the bimodal effect of MOS transistors, which can monitor and timely evaluate the bimodal effect of transistors online, save test resources, and greatly improve evaluation efficiency.

[0006] In order to solve the above technical problems, the method for monitoring and characterizing the bimodal effect of MOS transistors provided by the present invention comprises the following steps:

[0007] The first IdVg curve of the MOS transistor is tested under the condition that no back gate voltage is applied.

[0008] The second IdVg curve of the MOS transistor is tested under the condition of applying a back-gate voltage, where Id represents the drain current of the MOS transistor and Vg represents the gate voltage of the MOS transistor.

[0009] A first peak gate voltage and a second peak gate voltage corresponding to the double peaks of the MOS transistor are obtained according to the second IdVg curve, and the second peak gate voltage is greater than the first peak gate voltage.

[0010] Voltage mapping is performed, including: obtaining a first drain current corresponding to the first peak gate voltage and a second drain current corresponding to the second peak gate voltage from the second IdVg curve; and obtaining a third gate voltage corresponding to the first drain current and a fourth gate voltage corresponding to the second drain current from the first IdVg curve.

[0011] Calculating a bimodal characterization value includes: subtracting the first peak gate voltage from the second peak gate voltage to obtain a first voltage difference, subtracting the third gate voltage from the fourth gate voltage to obtain a second voltage difference, and subtracting the second voltage difference from the first voltage difference to obtain the bimodal characterization value.

[0012] Performing a bimodal effect judgment includes: when the bimodal characterization value is greater than 0, judging that the MOS transistor has a bimodal effect; when the bimodal characterization value is less than or equal to 0, judging that the MOS transistor does not have a bimodal effect.

[0013] A further improvement is that the method further includes fitting the first IdVg curve to obtain a first IdVg function.

[0014] The second IdVg curve is fitted to obtain a second IdVg function.

[0015] A further improvement is that the first peak gate voltage and the second peak gate voltage are obtained by maximizing the H(Vg) function.

[0016] The formula of the H(Vg) function is:

[0017]

[0018] Wherein, Gm represents the transconductance of the MOS transistor.

[0019] A further improvement is that when the MOS transistor is tested without applying the back-gate voltage, the back-gate voltage is equal to the source voltage of the MOS transistor.

[0020] A further improvement is that when the MOS transistor is tested under the condition of applying the back-gate voltage, the back-gate voltage is equal to the drain voltage of the MOS transistor.

[0021] A further improvement is that the MOS transistor is an NMOS transistor, and when testing the MOS transistor, the drain voltage is added to the power supply voltage;

[0022] A further improvement is that the MOS transistor is a PMOS transistor, and when testing the MOS transistor, the drain voltage is added with a negative power supply voltage.

[0023] The present invention utilizes the back gate voltage to amplify the characteristic of the bimodal effect of the MOS transistor, and obtains the corresponding IdVg curves, namely the first IdVg curve and the second IdVg curve, respectively, by testing without adding the back gate voltage and adding the back gate voltage. The second IdVg curve can be used to obtain two peak gate voltages, and the currents corresponding to the two peak gate voltages are mapped onto the first IdVg curve to obtain two corresponding gate voltages, namely the third and fourth gate voltages. The difference between the two peak gate voltages, namely the first voltage difference, and the difference between the third and fourth gate voltages, namely the second voltage difference, are compared to obtain a quantified bimodal characterization value. If the bimodal characterization value is greater than 0, it indicates that there is a bimodal effect, otherwise there is no bimodal effect. Therefore, the present invention quantifies whether the transistor has a bimodal effect by utilizing the difference between the two groups of Vg with and without the back gate voltage, thereby enabling online monitoring and timely evaluation of the bimodal effect of the transistor, and timely feedback of reliability risks and targeted evaluation, thereby saving test resources and greatly improving evaluation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0025] Figure 1 is a flow chart of a method for monitoring and characterizing a bimodal effect of a MOS transistor according to an embodiment of the present invention;

[0026] Figure 2 are two IdVg curves of a method for monitoring and characterizing a bimodal effect of a MOS transistor according to an embodiment of the present invention;

[0027] Figure 3 It is a curve diagram of the H (Vg) function model corresponding to the double peak effect curve of the method for monitoring and characterizing the double peak effect of MOS transistors according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] like Figure 1 As shown, it is a flow chart of a method for monitoring and characterizing the bimodal effect of a MOS transistor according to an embodiment of the present invention; Figure 2 , which are two IdVg curves of the method for monitoring and characterizing the bimodal effect of MOS transistors according to an embodiment of the present invention; the method for monitoring and characterizing the bimodal effect of MOS transistors according to an embodiment of the present invention comprises the following steps:

[0029] Step S101 , testing a first IdVg curve 101 of a MOS transistor without applying a back-gate voltage.

[0030] In the embodiment of the present invention, when the MOS transistor is tested without applying the back-gate voltage, the back-gate voltage is equal to the source voltage of the MOS transistor.

[0031] In some embodiments, the MOS transistor is an NMOS transistor. When testing the MOS transistor, the drain voltage plus the power supply voltage, i.e., V DD .

[0032] In some embodiments, the MOS transistor is a PMOS transistor, and when testing the MOS transistor, the drain voltage is added with a negative power supply voltage, that is, -V DD .

[0033] In some embodiments, the following also include:

[0034] The first IdVg curve 101 is fitted to obtain a first IdVg function.

[0035] Right now Figure 1 In step S101, V B =0, Vd = -V DD When IdVg is measured, it is IdVg1. B represents the back gate voltage, Vd represents the drain voltage, V DD represents the power supply voltage, Id represents the drain current, Vg represents the gate voltage, IdVg represents the data of Id and Vg, and IdVg1 represents the first IdVg curve 101. Figure 2 In the figure, the ordinate of the first IdVg curve 101 is the logarithm of Id, namely log(Id).

[0036] Step S102: testing the second IdVg curve 102 of the MOS transistor under the condition of applying a back gate voltage, where Id represents the drain current of the MOS transistor and Vg represents the gate voltage of the MOS transistor. Figure 1 In, V B =-V DD , Vd=-V DD When , IdVg is measured and is IdVg2. IdVg2 represents the second IdVg curve 102.

[0037] In some embodiments, when the MOS transistor is tested under the condition of applying the back-gate voltage, the back-gate voltage is equal to the drain voltage of the MOS transistor. In other embodiments, the back-gate voltage can also be less than the drain voltage, as long as the PN junction between the source region and the body region of the MOS transistor is reverse biased; wherein the effect of the back-gate voltage being equal to the drain voltage of the MOS transistor is the best, and no additional power supply voltage needs to be introduced.

[0038] In some embodiments, the following also include:

[0039] The second IdVg curve 102 is fitted to obtain a second IdVg function.

[0040] Step S103: Obtain the first peak gate voltage V corresponding to the double peaks of the MOS transistor according to the second IdVg curve 102. max1 and the second peak gate voltage V max2 , the second peak gate voltage V max2 is greater than the first peak gate voltage V max1 .

[0041] like Figure 2 As shown, the double peak effect in the second IdVg curve 102 will become larger, because after the back gate voltage is introduced, the threshold voltage of the MOS transistor will increase, and the change of Id with Vg will become slower, so the double peak effect will be amplified.

[0042] In order to better obtain the first peak gate voltage V max1 and the second peak gate voltage V max2 In the embodiment of the present invention, the H(Vg) function is also introduced, and the first peak gate voltage V is obtained by finding the maximum value of the H(Vg) function. max1 and the second peak gate voltage V max2 .

[0043] The formula of the H(Vg) function is:

[0044]

[0045] Wherein, Gm represents the transconductance of the MOS transistor.

[0046] like Figure 3 As shown, it is a curve diagram of the H (Vg) function model corresponding to the double peak effect curve of the method for monitoring and characterizing the double peak effect of MOS transistors according to an embodiment of the present invention, Figure 3 In the figure, curve 103 is the H(Vg) function model curve. It can be seen that curve 103 has two peaks. The first peak gate voltage V max1 and the second peak gate voltage V max2 The values ​​of Vg corresponding to the two maximum values ​​of H(Vg), i.e. the peak values.

[0047] Figure 1 In step S103, the function Calculate IdVg2 and get two maximum values ​​V max1 、V max2 .

[0048] Step S104, performing voltage mapping, including: Figure 2 As shown, the first peak gate voltage V is obtained from the second IdVg curve 102. max1 The corresponding first drain current and the second peak gate voltage Vmax2 A third gate voltage V corresponding to the first drain current is obtained from the first IdVg curve 101. 1 and a fourth gate voltage V corresponding to the second drain current 2 .

[0049] Figure 1 In step S104, V 1 、V 2 V max1 and V max2 The corresponding ID is in V B =The corresponding gate voltage when 0.

[0050] Step S105, calculating the double peak characterization value, including: using the second peak gate voltage V max2 Subtract the first peak gate voltage V max1 The first voltage difference is obtained by the fourth gate voltage V 2 Subtract the third gate voltage V 1 A second voltage difference is obtained, and the double-peak characterization value is obtained by subtracting the second voltage difference from the first voltage difference.

[0051] Figure 1 Step S105 is also expressed as: ΔV 0 =V 2 -V 1 , ΔVH=V max2 -V max1 , N hump =ΔV H -ΔV 0 .

[0052] Where, ΔV 0 represents the second voltage difference, ΔVH represents the first voltage difference, N hump represents the bimodal characterization value.

[0053] Step S106: perform bimodal effect determination. Figure 1 In step S106, Nhump>0, that is, it is determined whether Nhump is greater than 0.

[0054] Step S107 : when the double-peak characterization value is greater than 0, it is determined that the MOS transistor has a double-peak effect, that is, IdVg has a double-peak effect.

[0055] Step S108 : When the double-peak characterization value is less than or equal to 0, it is determined that the MOS transistor does not have a double-peak effect, that is, IdVg has no double-peak effect.

[0056] In the embodiment of the present invention, the back gate voltage can amplify the characteristic of the bimodal effect of the MOS transistor. The corresponding IdVg curves, namely the first IdVg curve 101 and the second IdVg curve 102, are obtained by testing without adding the back gate voltage and adding the back gate voltage. The second IdVg curve 102 can be used to obtain two peak gate voltages. The currents corresponding to the two peak gate voltages are mapped onto the first IdVg curve 101 to obtain two corresponding gate voltages, namely the third and fourth gate voltages V2. The difference between the two peak gate voltages, namely the first voltage difference, and the third and fourth gate voltages V 1 The difference between the two voltages, i.e., the second voltage difference, can be used to obtain a quantified bimodal characterization value. If the bimodal characterization value is greater than 0, it indicates that there is a bimodal effect. Otherwise, there is no bimodal effect. Therefore, the embodiment of the present invention quantifies whether the transistor has a bimodal effect by utilizing the difference between the two groups of Vg with and without back gate voltage, thereby enabling online monitoring and timely evaluation of the bimodal effect of the transistor, and timely feedback of reliability risks and targeted evaluation, thereby saving test resources and greatly improving evaluation efficiency.

[0057] In the embodiment of the present invention, by applying a back-gate voltage, the bimodal effect of the transistor can be amplified, and the difference between the two groups of Vg with and without the back-gate voltage can be used to quantify whether the transistor has a bimodal effect, thereby online monitoring and timely evaluating the bimodal effect of the transistor, saving test resources, greatly improving evaluation efficiency, and being able to provide timely feedback on reliability risks and conduct targeted evaluations, which is a useful supplement to traditional testing methods.

[0058] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for monitoring and characterizing the bimodal effect of a MOS transistor, characterized in that: The steps include: Testing a first IdVg curve of a MOS transistor without applying a back-gate voltage, where Id represents a drain current of the MOS transistor, and Vg represents a gate voltage of the MOS transistor; Testing a second IdVg curve of the MOS transistor under a condition of applying a back gate voltage; Obtaining a first peak gate voltage and a second peak gate voltage corresponding to the double peaks of the MOS transistor according to the second IdVg curve, wherein the second peak gate voltage is greater than the first peak gate voltage; Performing voltage mapping, including: obtaining a first drain current corresponding to the first peak gate voltage and a second drain current corresponding to the second peak gate voltage from the second IdVg curve; obtaining a third gate voltage corresponding to the first drain current and a fourth gate voltage corresponding to the second drain current from the first IdVg curve; Calculating a bimodal characterization value includes: subtracting the first peak gate voltage from the second peak gate voltage to obtain a first voltage difference, subtracting the third gate voltage from the fourth gate voltage to obtain a second voltage difference, and subtracting the second voltage difference from the first voltage difference to obtain the bimodal characterization value; Performing a bimodal effect judgment includes: when the bimodal characterization value is greater than 0, judging that the MOS transistor has a bimodal effect; when the bimodal characterization value is less than or equal to 0, judging that the MOS transistor does not have a bimodal effect.

2. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 1, characterized in that: It also includes fitting the first IdVg curve to obtain a first IdVg function; The second IdVg curve is fitted to obtain a second IdVg function.

3. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 2, characterized in that: maximizing the H(Vg) function to obtain the first peak gate voltage and the second peak gate voltage; The formula of the H(Vg) function is: Wherein, Gm represents the transconductance of the MOS transistor.

4. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 1, characterized in that: When the MOS transistor is tested without applying the back-gate voltage, the back-gate voltage is equal to the source voltage of the MOS transistor.

5. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 4, characterized in that: When the MOS transistor is tested under the condition of applying the back-gate voltage, the back-gate voltage is equal to the drain voltage of the MOS transistor.

6. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 5, characterized in that: The MOS transistor is an NMOS transistor. When testing the MOS transistor, the drain voltage is added to the power supply voltage.

7. The method for monitoring and characterizing the bimodal effect of a MOS transistor according to claim 5, characterized in that: The MOS transistor is a PMOS transistor. When testing the MOS transistor, the drain voltage is added with a negative power supply voltage.

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