Electronic device for outputting random number
By designing an electronic device including input and output nodes, pull-up resistors, transistors, buffers and counters, the problem of high hardware cost of existing random number generators and the generation of random numbers can only be generated when the oscillator starts, achieving efficient and low-cost random number generation.
Patent Information
- Application Number
- CN202411128135.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-06
- Filing Date
- 2024-08-16
- Publication Date
- 2025-06-06
AI Technical Summary
The existing random number generators have the problem of high hardware costs, complex equipment, and can only generate random numbers when the oscillator starts.
An electronic device is designed, including an input and output node, a pull-up resistor, a transistor, a buffer and a counter. The clock signal is generated by controlling the opening and closing of the transistor, and the clock signal is counted by the counter to obtain a random number.
It realizes efficient generation of random numbers without increasing hardware costs and reduces the time required for random numbers to be generated.
Smart Images
Figure CN120104095A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an electronic device, and in particular to an electronic device for outputting random numbers. Background Art
[0002] There are three ways to generate random numbers in the prior art. First, an analog-to-digital converter is used to measure a fixed voltage from a linear regulator, and multiple bits of the least significant bit in the analog-to-digital converter are obtained as random numbers. However, the resolution requirement of the analog-to-digital converter is relatively high, resulting in excessively high hardware costs. Second, two oscillators are used to generate clock signals of different frequencies, and when the two asynchronous clock signals are unstable at the time of oscillation, they are sampled from each other to generate random numbers. However, this method requires two oscillators, and random numbers can only be obtained when the oscillation is just started.
[0003] Third, two oscillators are used to generate clock signals of different frequencies, and when the two asynchronous clock signals are unstable at the start of oscillation, random numbers are generated through different feedback polynomial calculations, such as Linear Feedback Shift Register (LFSR) or Cellular Automata Shift Register (CASR). However, this method requires two oscillators, and random numbers can only be obtained when the oscillation is just started. Summary of the invention
[0004] An electronic device according to an embodiment of the present invention includes an input-output node, a pull-up resistor, a first transistor, a second transistor, a buffer, and a counter. The input-output node has an input voltage. The pull-up resistor is electrically connected between the input-output node and the power supply voltage. The first transistor is connected in parallel with the pull-up resistor. The second transistor is electrically connected between the input-output node and the ground voltage. The buffer is electrically connected to the input-output node and outputs a logic signal in accordance with the input voltage. At a first time point, the first transistor and the second transistor are turned off, so that the input voltage starts to rise from the ground voltage. At a second time point, the counter detects the rising edge of the logic signal. The first time point is earlier than the second time point. The counter counts the clock signal between the first time point and the second time point to obtain a count value. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention.
[0006] Figure 2 For the embodiment of the present invention Figure 1 Waveform diagram of the input voltage 130 , the clock signal 120 , the logic signal 140 , and the count value C1 in the electronic device 100 .
[0007] Figure 3 For the embodiment of the present invention Figure 1 The waveform diagram of the input voltage 130 when the electronic device 100 executes multiple power supply cycles.
[0008] Explanation of symbols
[0009] 100: Electronic devices
[0010] 102: Input and output nodes
[0011] 104: Pull-up resistor
[0012] 106: Transistor
[0013] 108: Transistor
[0014] 110: Buffer
[0015] 112: Counter
[0016] 120: Clock signal
[0017] 130: Input voltage
[0018] 140:Logic signal
[0019] 150: Control signal
[0020] 160: Control signal
[0021] VDD: power supply voltage
[0022] VSS: Ground voltage
[0023] t1: time point
[0024] t2: time point
[0025] C1: count value
[0026] V T :Threshold voltage
[0027] t3: time point
[0028] t4: time point
[0029] C2: count value
[0030] t5: time point
[0031] t6: time point
[0032] C3: count value
[0033] t7: time point
[0034] t8: time point
[0035] C4: count value DETAILED DESCRIPTION
[0036] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0037] Certain words are used throughout the specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to...".
[0038] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only references to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention. In the drawings, each diagram depicts the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or properties covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.
[0039] The structure (or layer, component, substrate) described in the present invention is located on / above another structure (or layer, device, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present invention, when a certain structure is disposed "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.
[0040] The terms "approximately," "equal," "equal," or "same," "substantially," or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.
[0041] The ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the device. They do not imply or represent any previous ordinal number of the device (or devices), nor do they represent the order of one device and another device, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a device with a certain name clearly distinguishable from another device with the same name. The patent application and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the patent application.
[0042] The electrical connection or coupling described in the present invention may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the devices on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable devices, or combinations of the above devices between the endpoints of the devices on the two circuits, but it is not limited to these.
[0043] In the present invention, the thickness, length and width can be measured by an optical microscope, and the thickness or width can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values or directions used for comparison may have a certain error. In addition, the terms "equal", "equal", "same", "substantially" or "substantially" mentioned in the present invention generally represent a range of 10% within a given value or range. In addition, the terms "a given range is a first value to a second value", "a given range falls within the range of a first value to a second value" indicate that the given range includes the first value, the second value and other values therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 and 10 degrees.
[0044] It should be noted that the following embodiments can replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present invention. The features between the embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.
[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.
[0046] Figure 1FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 100 includes an input-output node 102, an impedance device, a first switch (e.g., transistor 106), a second switch (e.g., transistor 108), a buffer 110, and a counter 112. In one embodiment, the input-output node 102 is an input-output pin (IOpad), and the input-output pin is set in an integrated circuit chip, but the present invention is not limited to this. The input-output node 102 has an input voltage 130. In one embodiment, the impedance device can be a device such as a resistor, a capacitor, an inductor, or a combination of the foregoing devices. In the following description, the pull-up resistor 104 is used for illustration, but the present invention is not limited to this. The pull-up resistor 104 is electrically connected between the input-output node 102 and the power supply voltage VDD. In some embodiments, the pull-up resistor 104 can be, for example, a resistor with a resistance value of 1K ohm to 10K ohm, but the present invention is not limited to this. In one embodiment, the first switch or the second switch can be a transistor or a device with the same function. The transistor 106 is connected in parallel with the pull-up resistor 104. In some embodiments, transistor 106 may be, for example, a P-type metal oxide semiconductor field effect transistor (MOSFET), but the present invention is not limited thereto. Transistor 108 is electrically connected between input / output node 102 and ground voltage VSS. In some embodiments, transistor 108 may be, for example, an N-type metal oxide semiconductor field effect transistor, but the present invention is not limited thereto.
[0047] The buffer 110 is electrically connected to the input / output node 102. The buffer 110 outputs a logic signal 140 in response to the input voltage 130. In some embodiments, the buffer 110 is a 1-bit analog-to-digital converter. For example, when the input voltage 130 is less than a threshold voltage V T , the buffer 110 outputs a logic signal 140 with a low voltage level. When the input voltage 130 is greater than or equal to the threshold voltage V T , the buffer 110 outputs a logic signal 140 with a high voltage level. In some embodiments, the threshold voltage V T It is half of the power supply voltage VDD, but the present invention is not limited thereto.
[0048] The counter 112 is electrically connected to the buffer 110. The counter 112 receives a clock signal 120 and a logic signal 140 from the buffer 110. At a first time point, the transistor 106 and the transistor 108 are turned off, and the power supply voltage VDD starts to supply power through the pull-up resistor 104, so that the input voltage 130 starts to rise from the ground voltage VSS. At a second time point, the counter 112 detects a rising edge of the logic signal 140. The first time point is earlier than the second time point. The counter 112 counts the clock signal 120 between the first time point and the second time point to obtain a count value. In some embodiments, the counter 112 outputs the count value, and the count value is used as a random number. In some embodiments, the randomness of the random number is derived from the time length from the first time point to the second time point, that is, the input voltage 130 rises from the ground voltage VSS to the threshold voltage V T The time spent.
[0049] In some embodiments, at the first time point, transistor 106 is turned off by receiving a control signal 150 through its gate, and transistor 108 is turned off by receiving a control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals. Figure 1 In the embodiment of FIG. 1 , at the first time point, the control signal 150 is at a high voltage level, and the control signal 160 is at a low voltage level.
[0050] exist Figure 1 In the embodiment, before the first time point, transistor 106 and transistor 108 are turned on, so that input voltage 130 of input-output node 102 is pulled down to ground voltage VSS. Specifically, before the first time point, transistor 106 is turned on by receiving control signal 150 through its gate, and transistor 160 is turned on by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals. Figure 1 In the embodiment of FIG. 1 , before the first time point, the control signal 150 is at a low voltage level, and the control signal 160 is at a high voltage level.
[0051] exist Figure 1 In the embodiment of the present invention, the counter 112 in the electronic device 100 counts the clock signal 120 during a period when the power supply voltage VDD is supplied through the pull-up resistor 104, that is, between the first time point and the second time point, to obtain a count value. In other words, the power supply voltage VDD only needs to be supplied through the pull-up resistor 104 before the input voltage 130 rises to the threshold voltage VT, and the input voltage 130 does not need to be pulled up to the power supply voltage VDD. At the same time, the counter 112 counts the clock signal 120, thereby reducing the time required to obtain a random number.
[0052] In some embodiments, if a pull-down resistor (not shown) is used to replace the pull-up resistor 104, and the pull-down resistor is connected in parallel with the transistor 108, the counter 112 in the electronic device 100 can use the input voltage 130 to discharge the pull-down resistor during a discharge period to count the clock signal 120, and the count value can also be obtained. In some embodiments, the randomness of the count value is derived from the input voltage 130 dropping from the power supply voltage VDD to the threshold voltage V T length of time.
[0053] Specifically, in the embodiment where the counter 112 counts the clock signal 120 during the discharge period, first, the transistor 106 is turned on, but the transistor 108 is turned off, so that the input voltage 130 of the input-output node 102 is equal to the power supply voltage VDD. Then, the transistor 106 is turned off, and the transistor 108 remains turned off, so that the input voltage 130 of the input-output node 102 begins to discharge the pull-down resistor. At the same time, the counter 112 begins to count the clock signal 120. During the discharge period, the counter 112 can detect the falling edge of the logic signal. For example, when the input voltage 130 is less than the threshold voltage V T In other words, the input voltage 130 only needs to be less than the threshold voltage V T The pull-down resistor is discharged before, and there is no need to discharge its own voltage to the ground voltage VSS. At the same time, the counter 112 counts the clock signal 120, thereby reducing the time required to obtain the random number.
[0054] Figure 2 For the embodiment of the present invention Figure 1 Waveform diagram of the input voltage 130 , the clock signal 120 , the logic signal 140 , and the count value C1 in the electronic device 100 . Figure 2 The horizontal axis of the waveform graph in is time, and the vertical axis is voltage. Figure 1 and Figure 2 .like Figure 2 As shown, during the period from point zero (0) to time point t1 (ie, before time point t1), transistors 106 and 108 are turned on, so that the input voltage 130 of the input-output node 102 is pulled down to the ground voltage VSS (eg, 0V).
[0055] Specifically, during the period from the zero point (0) of the waveform to the time point t1, the transistor 106 is turned on by receiving the control signal 150 through its gate, and the transistor 160 is turned on by receiving the control signal 160 through its gate, and the control signal 150 and the control signal 160 are inverted signals. During the period from the zero point (0) of the waveform to the time point t1, the control signal 150 is at a low voltage level, and the control signal 160 is at a high voltage level.
[0056] At time point t1, transistor 106 and transistor 108 are turned off, and power supply voltage VDD is supplied through pull-up resistor 104, so that input voltage 130 starts to rise from ground voltage VSS. At time point t1, counter 112 starts to count clock signal 120. In detail, transistor 106 is turned off by receiving control signal 150 through its gate, and transistor 108 is turned off by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals to each other. At time point t1, control signal 150 is at a high voltage level, and control signal 160 is at a low voltage level.
[0057] At time t2, the input voltage 130 rises to the threshold voltage V T , the counter 112 also detects that the logic signal 140 output by the buffer 110 changes from a low voltage level to a high voltage level, that is, it detects the rising edge of the logic signal 140, and thus terminates the counting. The counter 112 counts the clock signal 120 between the time point t1 and the time point t2 to obtain the count value C1. In some embodiments, the counter 112 outputs the count value C1 as a random number. The randomness of the random number comes from the time length between the time point t1 and the time point t2.
[0058] Figure 3 For the embodiment of the present invention Figure 1 The waveform diagram of the input voltage 130 when the electronic device 100 executes multiple power supply cycles. Figure 3 The horizontal axis of the waveform graph in is time, and the vertical axis is voltage. Figure 1 , Figure 2 ,and Figure 3 .like Figure 3 As shown, continued Figure 2 , between time point t2 and time point t3 (i.e., before time point t3), transistor 106 and transistor 108 are turned on, so that input voltage 130 of input / output node 102 is pulled down to ground voltage VSS (e.g., 0V). Specifically, between time point t2 and time point t3, transistor 106 is turned on by receiving control signal 150 through its gate, and transistor 160 is turned on by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals to each other. Between time point t2 and time point t3, control signal 150 is at a low voltage level, and control signal 160 is at a high voltage level.
[0059] At time point t3, transistor 106 and transistor 108 are turned off, and power supply voltage VDD starts to supply power through pull-up resistor 104, so that input voltage 130 starts to rise from ground voltage VSS. At time point t3, counter 112 starts to count clock signal 120. In detail, transistor 106 is turned off by receiving control signal 150 through its gate, and transistor 108 is turned off by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals to each other. At time point t3, control signal 150 is at a high voltage level, and control signal 160 is at a low voltage level.
[0060] At time t4, the input voltage 130 rises to the threshold voltage V T , the counter 112 also detects the rising edge of the logic signal 140, and thus terminates the counting. The counter 112 counts the clock signal 120 between the time point t3 and the time point t4 to obtain the count value C2. In some embodiments, the counter 112 adds the count value C1 and the count value C2 to obtain a random number to increase the randomness of the random number, and outputs the random number. The randomness of the random number is derived from the time length between the time point t1 and the time point t2 and the time length between the time point t3 and the time point t4.
[0061] Between time point t4 and time point t5 (i.e., before time point t5), transistor 106 and transistor 108 are turned on, so that input voltage 130 of input / output node 102 is pulled down to ground voltage VSS (e.g., 0V). Specifically, between time point t4 and time point t5, transistor 106 is turned on by receiving control signal 150 through its gate, and transistor 160 is turned on by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are mutually inverted signals. Between time point t4 and time point t5, control signal 150 is at a low voltage level, and control signal 160 is at a high voltage level.
[0062] At time point t5, transistor 106 and transistor 108 are turned off, and power supply voltage VDD starts to supply power through pull-up resistor 104, so that input voltage 130 starts to rise from ground voltage VSS. At time point t5, counter 112 starts to count clock signal 120. In detail, transistor 106 is turned off by receiving control signal 150 through its gate, and transistor 108 is turned off by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals to each other. At time point t5, control signal 150 is at a high voltage level, and control signal 160 is at a low voltage level.
[0063] At time t6, the input voltage 130 rises to the threshold voltage V T, the counter 112 also detects the rising edge of the logic signal 140, thereby terminating the counting. The counter 112 counts the clock signal 120 between the time point t5 and the time point t6 to obtain the count value C3. In some embodiments, the counter 112 adds the count value C1, the count value C2, and the count value C3 to obtain a random number to increase the randomness of the random number, and outputs the random number. The randomness of the random number is derived from the time length between the time point t1 and the time point t2, the time length between the time point t3 and the time point t4, and the time length between the time point t5 and the time point t6.
[0064] Between time point t6 and time point t7 (i.e., before time point t7), transistor 106 and transistor 108 are turned on, so that input voltage 130 of input / output node 102 is pulled down to ground voltage VSS (e.g., 0V). Specifically, between time point t6 and time point t7, transistor 106 is turned on by receiving control signal 150 through its gate, and transistor 160 is turned on by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are mutually inverted signals. Between time point t6 and time point t7, control signal 150 is at a low voltage level, and control signal 160 is at a high voltage level.
[0065] At time point t7, transistor 106 and transistor 108 are turned off, and power supply voltage VDD starts to supply power through pull-up resistor 104, so that input voltage 130 starts to rise from ground voltage VSS. At time point t7, counter 112 starts to count clock signal 120. In detail, transistor 106 is turned off by receiving control signal 150 through its gate, and transistor 108 is turned off by receiving control signal 160 through its gate, and control signal 150 and control signal 160 are inverted signals to each other. At time point t7, control signal 150 is at a high voltage level, and control signal 160 is at a low voltage level.
[0066] At time t8, the input voltage 130 rises to the threshold voltage V T, the counter 112 also detects the rising edge of the logic signal 140, and thus terminates the counting. The counter 112 counts the clock signal 120 between time point t7 and time point t8 to obtain a count value C4. In some embodiments, the counter 112 adds the count value C1, the count value C2, the count value C3, and the count value C4 to obtain a random number to increase the randomness of the random number, and outputs the random number. The randomness of the random number is derived from the time length between time point t1 and time point t2, the time length between time point t3 and time point t4, the time length between time point t5 and time point t6, and the time length between time point t7 and time point t8. In some embodiments, the more count values obtained corresponding to multiple power supply cycles, the greater the randomness of the random number obtained after adding the count values.
[0067] In some embodiments, Figure 1 The buffer 110 in the embodiment can be designed as a circuit that is sensitive to the input voltage 130 (or the power supply voltage VDD), which can also increase the randomness of the output random number.
[0068] In some embodiments, Figure 1 During the counting process of the counter 112, the supply current through the pull-up resistor 104 will slightly change with the power noise of the power supply voltage VDD. Similarly, the input voltage 130 of the input-output node 102 will also slightly change with the power noise of the power supply voltage VDD. Therefore, the randomness of the random number output by the electronic device 100 also comes from the power noise of the power supply voltage VDD.
[0069] The electronic device 100 of the present invention does not require additional circuits, but only requires basic input and output (IO) circuits to achieve the output of random numbers. In practical applications, the clock signal 120 and the input voltage 130 are taken from the clock signal and voltage in the original circuit, without increasing hardware costs.
[0070] Although the embodiments of the present invention are described above, we should understand that what is presented above is only an example and not a limitation. Many changes to the above exemplary embodiments can be implemented without violating the spirit and scope of the disclosure according to this embodiment. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. More specifically, the scope of the present invention should be defined by the following claims and their equivalents. Although the above disclosure has been illustrated and described by one or more related executions, equivalent changes and modifications will be thought of by others who are familiar with this field based on the above specifications and drawings. In addition, although a particular feature of the present invention has been demonstrated by one of the related multiple executions, the above feature may be combined with one or more other features so that there may be a need and help for any known or special application.
[0071] The professional terms used in this specification are only for the purpose of describing specific embodiments and are not intended to be used as limitations of the present invention. Unless the context clearly indicates otherwise, the singular, one, the above and the above also include the plural. Furthermore, the words "include", "comprise", "have", "have", or their variations are either used as detailed descriptions or as the scope of the patent application. The above words mean to include, and to some extent are equivalent to the word "include". Unless there are different definitions, all the terms used in this article (including technical or scientific terms) can be generally understood by technicians in the field of technology disclosed above. We should be more aware that the above words, such as those defined in commonly used dictionaries, should be interpreted as the same meaning in the context of the relevant technology. Unless explicitly defined in this article, the above words will not be interpreted as idealized or overly formal.
Claims
1. An electronic device for outputting a random number, characterized in that: include: an input-output node having an input voltage; an impedance device electrically connected between the input-output node and a power supply voltage; a first switch connected in parallel with the impedance device; a second switch electrically connected between the input-output node and a ground voltage; a buffer, electrically connected to the input-output node, and outputting a logic signal corresponding to the input voltage; as well as a counter, electrically connected to the buffer, receiving a clock signal and the logic signal, Wherein, at a first time point, the first switch and the second switch are turned off, so that the input voltage starts to rise from the ground voltage; Wherein, at a second time point, the counter detects a rising edge of the logic signal; the first time point is earlier than the second time point; and The counter counts the clock signal between the first time point and the second time point to obtain a count value as a random number.
2. The electronic device according to claim 1, wherein: When the counter detects a rising edge of the logic signal, the input voltage is equal to a threshold voltage, and the threshold voltage is equal to half of the power supply voltage.
3. The electronic device according to claim 2, wherein: When the input voltage is less than the threshold voltage, the buffer outputs the logic signal with a low voltage level, and when the input voltage is greater than or equal to the threshold voltage, the buffer outputs the logic signal with a high voltage level.
4. The electronic device according to claim 1, wherein: At the first time point, the first switch receives a first control signal and is turned off, the second switch receives a second control signal and is turned off, and the first control signal and the second control signal are inverted signals to each other.
5. The electronic device according to claim 1, wherein: Before the first time point, the first switch and the second switch are turned on, so that the input voltage of the input-output node is pulled down to the ground voltage.
6. The electronic device as claimed in claim 5, characterized in that: Before the first time point, the first switch is turned on by receiving a first control signal through its gate, and the second switch is turned on by receiving a second control signal through its gate, and the first control signal and the second control signal are inverted signals to each other.
7. The electronic device according to claim 1, wherein: After the second time point and before a third time point, the first switch and the second switch are turned on, so that the input voltage of the input-output node is pulled down to the ground voltage; the second time point is earlier than the third time point.
8. The electronic device as claimed in claim 7, characterized in that: At the third time point, the first switch and the second switch are closed, so that the input voltage starts to rise from the ground voltage; at a fourth time point, the counter detects a rising edge of the logic signal; The third time point is earlier than the fourth time point; the counter counts the clock signal between the third time point and the fourth time point to obtain a second count value, and the counter adds the count value and the second count value to obtain a random number to increase the randomness of the random number, and outputs the random number.
9. The electronic device as claimed in claim 1, wherein: The buffer is a 1-bit analog-to-digital converter.
10. The electronic device as claimed in claim 8, characterized in that The randomness is derived from the time length from the first time point to the second time point, or the time length from the third time point to the fourth time point.