Memory core chip with TSV

Abstract

The invention relates to a memory core chip with TSVs. Disclosed herein is an apparatus comprising: an array of memory cells; a plurality of TSVs penetrating the semiconductor chip; an output circuit configured to output data to the TSVs; an input circuit configured to receive data from the TSVs; a pad supplied with data from the outside; and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with invention name “Memory core chip with TSV”, application number 202011022002.2, and application date September 25, 2020. Technical Field

[0003] The present invention relates generally to semiconductor chips, and more particularly, to memory core chips having TSVs (Through Silicon Vias). Background Art

[0004] Semiconductor chips used in memory devices such as HBM (High Bandwidth Memory) generally include many TSVs (Through Silicon Vias) arranged to penetrate a semiconductor substrate. The TSVs provided on each semiconductor chip are connected to TSVs arranged on another semiconductor chip and positioned at the same planar position via bumps and pad electrodes, respectively, thereby forming a signal path penetrating multiple semiconductor substrates. In the case where a specific TSV is in a poor conduction state or there is a poor connection at a connection point between two TSVs, the relevant signal path is defective and almost unusable. In this case, a spare signal path is used instead of the defective signal path to restore the defect to normal.

[0005] Poor conduction of TSV or poor connection at a connection point between two TSVs can be discovered only after a plurality of semiconductor chips are stacked. However, even if a defect is discovered on a signal path, it is difficult to determine whether the defect is caused by a defect of the TSV or a defect at a connection point between the TSVs, or whether an input / output circuit connected to the TSV has a defect. Therefore, a semiconductor device is needed in which an input / output circuit connected to the TSV can be tested before a plurality of semiconductor chips are stacked. Summary of the invention

[0006] On the one hand, the present invention relates to an apparatus comprising: a memory cell array; a plurality of TSVs penetrating a semiconductor chip; an output circuit configured to output data to the TSVs; an input circuit configured to receive data from the TSVs; a pad supplied with data from the outside; and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transmit the data from the memory cell array to the input circuit via the output circuit and the TSVs.

[0007] On the other hand, the present invention relates to a device, comprising: an interface chip; and a core chip stacked on the interface chip, the core chip including a memory cell array, a pad, a control circuit, a plurality of TSVs respectively coupled to the interface chip, and a plurality of data buffers respectively coupled to the plurality of TSVs, and each of the data buffers including a data receiver and a data transmitter; wherein the control circuit is configured to transmit the memory data read out from the memory cell array to the pad via the data transmitter and the data receiver of a selected one of the plurality of data buffers.

[0008] On the other hand, the present invention relates to a method for testing a device having a memory cell array, a plurality of TSVs, input and output circuits connected in parallel between the memory cell array and the TSVs, and a test pad, the method comprising: inputting test data to the test pad; writing the test data to the memory cell array; reading the test data from the memory cell array; and transmitting the test data from the memory cell array to the input circuit via the output circuit and the TSVs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic plan view showing a plan view of a memory core chip according to the present invention.

[0010] Figure 2 is a schematic diagram showing a configuration of an HBM on which eight memory core chips are stacked one on top of another according to the present invention.

[0011] Figure 3 is a table showing the channels, slice addresses, and groups assigned to each of the memory core chips.

[0012] Figure 4 is a schematic diagram for explaining the configuration of a signal path including a plurality of TSVs.

[0013] Figure 5 is a schematic diagram for explaining a state in which failure information is loaded into a domino switch circuit of each of the chips.

[0014] Fig. 6A : is a schematic diagram for explaining a connection relationship in a state in which replacement by the domino switch circuit is not performed.

[0015] Figure 6B is a schematic diagram for explaining a connection relationship in a state in which replacement by a domino switch circuit is performed.

[0016] Fig. 7A and 7Bis a schematic diagram for explaining TSV assignment in a TSV area.

[0017] Figure 8 is a schematic plan view showing the layout of TSVs arranged in the area of ​​the TSV region.

[0018] Fig. 9 is a block diagram showing the circuitry connected between the TSVs and the memory cell array.

[0019] Figures 10 to 12 A diagram used to explain the flow of test data in a test operation. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, because some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0021] like Figure 1 , a memory core chip according to the present invention includes 4 channels, TSV areas TAa and TAb, and a test pad TP. The 4 channels are channels Ch-A, Ch-C, Ch-E, and Ch-G or Ch-B, Ch-D, Ch-F, and Ch-H. Each of the channels includes a memory cell array MA in which many DRAM memory cells are arranged in an array and a peripheral circuit RIB. The channels can operate independently of each other. Therefore, terminals such as data input / output terminals, address terminals, command terminals, and clock terminals are assigned to each of the channels. In the present embodiment, the number of I / O bits per channel is 144 bits, of which 128 bits are actual data and 16 bits are ECC (error correction code) data. TSV areas TAa and TAb are areas in which a plurality of TSVs arranged to penetrate a semiconductor substrate are arranged in an array. Although not particularly limited, the area is divided into two TSV areas TAa and TAb in the memory core chip according to the present invention. The TSV area TAa is assigned to the channels Ch-A / Ch-B and the channels Ch-C / Ch-D, and the other TSV area TAb is assigned to the channels Ch-E / Ch-F and the channels Ch-G / Ch-H. The test pad TP is used to input / output data, such as test data, by probing in the wafer state. Unlike TSV, the test pad TP is formed on the surface of the semiconductor substrate without penetrating the semiconductor substrate. The plane size of the test pad TP is sufficiently larger than the plane size of the TSV to achieve probing.

[0022] like Figure 2 1 shows that a plurality of memory core chips according to the present invention are stacked one above the other on an interface chip 10 to thereby form an HBM. The interface chip 10 is a semiconductor chip that controls the memory core chips. Figure 2 In the example shown in FIG. 1 , the HBM has a configuration in which eight memory core chips 20 to 27 are stacked on the interface chip 10. The assignment of channels, slice addresses SIDs, and groups DW to each of the memory core chips 20 to 27 is as shown in FIG. Figure 3 As shown in Figure 3 , channels Ch-A, Ch-C, Ch-E and Ch-G are assigned to memory core chips 20 to 23, and channels Ch-B, Ch-D, Ch-F and Ch-H are assigned to memory core chips 24 to 27. The most significant bit SID0 of the slice address is assigned to the memory core chips 20, 22, 24 and 26, and the most significant bit SID1 of the slice address is assigned to the memory core chips 21, 23, 25 and 27. The slice address SID is a selection signal of the memory core chips 20 to 27, and one of the most significant bits SID0 and SID1 of the slice address is activated when actually accessed. Therefore, the memory core chips 20, 22, 24 and 26 and the memory core chips 21, 23, 25 and 27 are accessed exclusively from each other. Groups DW0 and DW2 are assigned to memory core chips 20, 21, 24, and 25, and groups DW1 and DW3 are assigned to memory core chips 22, 23, 26, and 27. Groups DW0 to DW3 are obtained by dividing 144 bits of I / O data per channel into 4 parts. Therefore, the number of I / O bits per group is 36 bits, of which 32 bits are actual data and 4 bits are ECC data. In this configuration, the signal path through the TSV is shared by two memory core chips. For example, mainly discussing channel Ch-A, when the slice address SID0 is activated, the memory core chips 20 and 22 are selected, and when the slice address SID1 is activated, the memory core chips 21 and 23 are selected. Because the same groups DW0 and DW2 are assigned to the memory core chip 20 and the memory core chip 21, the signal path P1 through the TSV is commonly assigned to the memory core chip 20 and the memory core chip 21, and any one of these memory core chips is selected by the most significant bit SID of the slice address, such as Figure 2 Similarly, because the same groups DW1 and DW3 are assigned to the memory core chip 22 and the memory core chip 23, the signal path P2 through the TSV is commonly assigned to the memory core chip 22 and the memory core chip 23, and either one of them is selected by the most significant bit SID of the slice address, as shown in FIG. Figure 2 Displayed in.

[0023] like Figure 4 , each of the interface chip 10 and the memory core chips 20 to 26 includes a plurality of TSVs 30 arranged to penetrate the corresponding semiconductor substrate. The interface chip 10 and the memory core chips 20 to 27 are all stacked by a face-down method, that is, in such a way that the main surface on which the transistors and wiring patterns (all not shown) are formed faces downward. Therefore, the memory core chip 27 positioned in the topmost layer does not need TSVs 30. However, the memory core chip 27 positioned in the topmost layer may include TSVs 30. Most of the TSVs 30 arranged on the memory core chips 20 to 26 are respectively connected to the front TSV pads 31A positioned at the same planar position. In contrast, most of the TSVs 30 arranged on the interface chip 10 and the front TSV pads 31A arranged on the interface chip 10 are positioned at different planar positions. The TSVs 30 located at the same plane position among the TSVs 30 provided on the interface chip 10 and the memory core chips 20 to 26 are cascade-connected via the front TSV pads 31A, the TSV bumps 31B, and the back TSV pads 31C, respectively, so that a plurality of signal paths 32 are formed. The command and write data output from the interface chip 10 are supplied to the memory core chips 20 to 27 via the signal paths 32. The read data output from the memory core chips 20 to 27 are supplied to the interface chip 10 via the signal paths 32. The external terminals 33 are provided on the interface chip 10, and signal transmission / reception to / from an external circuit is performed via the external terminals 33.

[0024] Some signal paths 32 are spare signal paths. The spare signal paths are used when some signal paths 32 have defects. Figure 4 As shown in FIG. 2 , latch circuits L are respectively assigned to TSVs, and failure information is stored in latch circuits L corresponding to respective TSVs 30 in defective signal paths 32 .

[0025] When the failure information is stored in the latch circuit L, the connection relationship between the internal circuit of the interface chip 10 and the internal circuit of the memory core chips 20 to 27 and the TSV 30 is switched so that the spare signal path is used to replace the defective signal path. Figure 5, a domino switch circuit 42 is provided in each of the interface chip 10 and the memory core chips 20 to 27. The domino switch circuit 42 is a circuit for switching the connection relationship between the internal circuit of the interface chip 10 and the internal circuit of the memory core chips 20 to 27 and the TSV 30, and the connection relationship between the internal circuit of the interface chip 10 and the internal circuit of the memory core chips 20 to 27 and the TSV 30 is switched based on the failure information stored in the latch circuit L. The failure information is first read from the anti-fuse circuit 40 during the initialization stage after power activation and is loaded into the latch circuit L of the interface chip 10 and the memory core chips 20 to 27 together. The transmission of the failure information is performed through the TSV 30F for the transmission of the failure information. The writing of the failure information to the anti-fuse circuit 40 is performed based on the result of the screening test performed at the manufacturing stage.

[0026] As in Fig. 6A As shown in FIG. 1 , each of the domino switch circuits 42 is connected between a plurality of input / output nodes of the internal circuit 46 and a plurality of TSVs 30. Fig. 6A In the example shown in FIG. 4 , the internal circuit 46 has eight input / output nodes N0 to N7, and nine TSVs 50 to 58 are correspondingly assigned to the output nodes. Among these TSVs, eight TSVs 50 to 57 are original TSVs, and one TSV 58 is a spare TSV. Corresponding latch circuits L0 to L7 are assigned to TSVs 50 to 57, respectively. Fig. 6A In the example shown in FIG. 1 , the failure information is not stored in the latch circuits L0 to L7. In this case, the domino switch circuit 42 connects the input / output nodes N0 to N7 and the TSVs 50 to 57, respectively. Therefore, in this case, the spare TSV 58 is not used. In contrast, when the failure information is stored in (for example) Figure 6B , the domino switch circuit 42 respectively connects the input / output nodes N0 to N7 and the TSVs 50 to 52 and the TSVs 54 to 58. Therefore, the TSV 53 corresponding to the latch circuit L3 is invalidated. In this way, the domino switch circuit 42 realizes the recovery of the defect by converting the connection relationship between the input / output nodes N0 to N7 and the TSVs 50 to 58 without simply replacing the TSV to which the failure information is assigned with a spare TSV.

[0027] Failure information generated by the operation test performed during the initialization phase after power activation can also be rewritten to the latch circuit L, and the failure information in the anti-fuse circuit 40 is also loaded into the latch circuit L. The operation of rewriting the failure information by the operation test performed during the initialization phase is called an "automatic repair operation". A defect on the signal path is found in the screening test performed at the manufacturing stage, and failure information is written to the anti-fuse circuit 40 based on the defect. Therefore, the signal path containing the defect is replaced by a spare signal path. However, in rare cases, a defective signal path will newly appear over time after leaving the factory. Finding this defect that occurs later and replacing the defective signal path with a spare signal path is an automatic repair operation.

[0028] exist Figure 1 In the TSV regions TAa and TAb shown in FIG. 1 , a plurality of TSVs penetrating the semiconductor substrate are arranged. The TSVs arranged in the TSV regions TAa and TAb are respectively as shown in FIG. Fig. 7A and 7B Assign as shown in . Fig. 7A and 7B , the TSV areas TAa and TAb include areas 61 to 68 where TSVs for I / O data are arranged, and an area 60 where TSVs to be used for transmission of addresses and commands are arranged. Fig. 7A In the example shown in FIG. 1 , the TSVs of the group DW0 assigned to the channel Ch-A are arranged in the region 61, the TSVs of the group DW0 assigned to the channel Ch-B are arranged in the region 62, the TSVs of the group DW1 assigned to the channel Ch-A are arranged in the region 63, and the TSVs of the group DW1 assigned to the channel Ch-B are arranged in the region 64. Figure 3 As explained, channel Ch-A and channel Ch-B are respectively assigned to different memory core chips, and group DW0 and group DW1 are respectively assigned to different memory core chips. Therefore, only one of regions 61 to 64 is connected to the internal circuit in each of the memory core chips, and the other three regions are bypassed. This is also the case for regions 65 to 68 arranged in the TSV area TAb.

[0029] Figure 8 is a table showing the layout of TSVs arranged in the area 61. Figure 8, the TSVs arranged in region 61 include 32 via conductors corresponding to data DQ0R to DQ31R, respectively, and 32 via conductors corresponding to data DQ0F to DQ31F, respectively. Data DQ0R to DQ31R are 32-bit data that are simultaneously input / output in synchronization with the rising edge of the clock signal, and data DQ0F to DQ31F are 32-bit data that are simultaneously input / output in synchronization with the falling edge of the clock signal. In addition, TSVs corresponding to data mask signals DM0R to DM3R and DM0F to DM3F, TSVs corresponding to read clock signals RCLKT and RCLKF, TSVs corresponding to write clock signals WCLKT and WCLKF, TSVs corresponding to backup signal paths R1 and R2, and TSVs for power supplies VDD and VSS are also included in region 61. In Figure 8 In the example shown in FIG. 1 , pairs of data such as data DQ0R and data DQ0F are arranged adjacent to each other. A spare signal path R1 is assigned to data DQ0R to DQ31R and DQ0F to DQ31F and data mask signals DM0R to Dm3R and DM0F to DM3F. A spare signal path R2 is assigned to TSVs corresponding to read clock signals RCLKT and RCLKF and TSVs corresponding to write clock signals WCLKT and WCLKF.

[0030] Fig. 9 FIG. 1 is a circuit diagram showing an example of the connection relationship between TSV and a memory cell array. Fig. 9 In the example shown in FIG. 1 , a read path 81 including an internal buffer 73, a read FIFO circuit 74, and an output buffer 76 and a write path 82 including an input receiver 77 and an internal buffer 79 are connected in parallel between the TSV 71 corresponding to the data DQ0R and the memory cell array 72. In normal operation, the read path 81 is activated in a read operation, and the write path 82 is activated in a write operation. That is, the read path 81 and the write path 82 are activated mutually exclusively in normal operation. In contrast, both the read path 81 and the write path 82 may be activated in a test operation.

[0031] Figures 10 to 12 A diagram used to explain the flow of test data in a test operation. Figures 10 to 12 The test operation shown in FIG. 1 is performed under the control of the control circuit 90 included in the memory core chips 20 to 27, and data transmission to / reception from the tester is performed through the test pad TP1. Therefore, the test operation can be performed in a wafer state before stacking the memory core chips 20 to 27.

[0032] In the test operation, firstly input the test data TDATA from the test pad TP1, such as Fig.10. The test data TDATA is written to the memory cell array MA via the switch circuit 91 included in the peripheral circuit RIB. At this time, the latch signal LDATA can be input via the test pad TP1. The latch signal LDATA is supplied to the latch control circuit 93 and thus the failure information is written to any one of the latch circuits L respectively assigned to the TSVs. Alternatively, it is possible to test the path assigned to the conventional TSV in the first test without writing the failure information to the latch circuit L and then test the path assigned to the spare TSV by writing the failure information to any one of the latch circuits L.

[0033] Next, the test data TDATA written into the memory cell array MA is read out, as shown in FIG. Fig.11 . The test data TDATA read from the memory cell array MA is transmitted to the selector 94 via the switch circuit 91. The selector 94 is a circuit for switching the connection relationship between the memory cell array MA and the regions 61 to 64, and the selection by the selector 94 is performed based on the selection signals SEL0 to SEL3. For example, when the selection signal SEL0 is activated, the test data TDATA read from the memory cell array MA is supplied to the region 61. In this case, the regions 62 to 64 are separated from the memory cell array MA. In this way, the test data TDATA read from the memory cell array MA can be supplied to any one of the regions 61 to 64 using the selection signals SEL0 to SEL3. Because it is not enough to determine which one of the regions 61 to 64 will be connected to the memory cell array MA in the wafer state and only one of the regions 61 to 64 is connected to the memory cell array MA in actual use and the other three regions are bypassed, this selection is enabled.

[0034] When the test data TDATA is supplied to, for example, the area 61, the test data TDATA is supplied to the area 61 via Fig. 9 The read path 81 shown in FIG. 8 is supplied to each of the corresponding TSVs. As described above, both the read path 81 and the write path 82 are activated at the time of the test operation. Therefore, the test data TDATA supplied to the TSV via the read path 81 is returned to the switch circuit 91 via the write path 82, as shown in FIG. Fig.12. That is, the test data TDATA read from the memory cell array MA is passed through the read path 81, TSV and write path 82. In order to prevent the test data TDATA supplied to the read path 81 and the test data TDATA output from the write path 82 from colliding on the read / write bus, it is sufficient to delay the timing of supplying the clock signal to the read FIFO circuit 72 to delay the output timing of the test data TDATA output from the write path 82. The test data TDATA transmitted to the switch circuit 91 is supplied to the compression circuit 92. The compression circuit 92 compresses the test data TDATA to generate compressed data CDATA. The compressed data CDATA is information indicating whether the test data TDATA contains an error. The compressed data CDATA is output from the test pad TP1 to the outside.

[0035] As described above, in the present embodiment, in the test operation, not only the write operation and the read operation of the test data TDATA are performed on the memory cell array MA, but also the test data TDATA read from the memory cell array MA is supplied to the compression circuit 92 via the read path 81 and the write path 82. Therefore, it is possible to test whether the read path 81 and the write path 82 can operate normally in the wafer state. In addition, since the latch signal LDATA can be input via the test pad TP1, it is also possible to test whether the read path 81 and the write path 82 corresponding to the standby signal path operate normally in the wafer state.

[0036] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and obvious modifications and equivalents thereof. In addition, based on the present invention, it will be readily apparent to those skilled in the art that other modifications within the scope of the present invention are within the scope of the present invention. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still fall within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with one another in order to form different modes of the disclosed invention. Therefore, it is desired that the scope of at least part of the present invention disclosed herein should be limited by the disclosed specific embodiments described above.

Claims

1. A semiconductor chip, include: a memory cell array; Test pads; TSV, which penetrates the semiconductor chip; a read circuit and a write circuit coupled in parallel to the TSV; and A control circuit configured to: transferring data from the memory cell array to the TSVs through the read circuit in a read operation; transferring data from the TSV to the memory cell array through the write circuit in a write operation; and Test data is transferred between the memory cell array and the test pad through the read circuit and the write circuit in a test operation.

2. The semiconductor chip according to claim 1, wherein the test data is input from outside the semiconductor chip.

3. The semiconductor chip according to claim 1, further comprising: include: a switch circuit configured to transfer the test data from the test pad to the memory cell array; and The latch control circuit is configured to receive a latch signal via the test pad. 4 . The semiconductor chip according to claim 3 , wherein the latch signal triggers fail information to be written to a latch circuit corresponding to the TSV. 5 . The semiconductor chip according to claim 4 , wherein the latch signal is supplied from outside the semiconductor device. 6 . The semiconductor chip according to claim 3 , wherein the test data supplied to the TSV via the read circuit is returned to the switch circuit via the write circuit. 7 . The semiconductor chip according to claim 1 , wherein the read circuit further comprises a read FIFO circuit configured to delay an output timing of the test data being output from the write circuit in the test operation. 8 . The semiconductor chip of claim 1 , further comprising a compression circuit configured to generate compressed data indicating whether the test data includes an error.

9. A device, wherein include: Interface chip; and A core chip stacked on the interface chip, the core chip comprising a memory cell array, a test pad, a control circuit, a TSV coupled to the interface chip, and a plurality of data buffers coupled to the TSV, wherein the read path includes a data transmitter and at least one of the plurality of data buffers, and the write path includes a data receiver and at least another one of the plurality of data buffers, wherein the read path and the write path are coupled in parallel, and Wherein the control circuit is configured to transfer test data between the memory cell array and the test pad via the data transmitter and the data receiver in a test operation.

10. The apparatus according to claim 9, further comprising a compression circuit configured to generate compression data based on the test data, wherein the test data read from the memory cell array in the test operation is supplied to the compression circuit via the data transmitter and the data receiver. The apparatus according to claim 10 , wherein the compressed data is output via the test pad. 12 . The apparatus of claim 9 , wherein in an operation other than the test operation, the read path and the write path are activated mutually exclusively.

13. The apparatus of claim 9, wherein the read path and the write path are activated at the time of the test operation.

14. The apparatus of claim 9, wherein the test pad is supplied with test data by probing.

15. A method, the method comprising: include: transferring data from the memory cell array to the TSV via the read path in a read operation; transferring data from the TSV to the memory cell array via a write path in a write operation; inputting test data from outside the semiconductor chip to the test pad; and The test data is transferred between the memory cell array and the test pad via the read path and the write path in a test operation.

16. The method of claim 15, wherein transferring the test data comprises writing the test data to the memory cell array and transferring the test data from the memory cell array to a selector via a switch circuit. 17 . The method of claim 16 , wherein the selector is configured to supply the test data from the memory cell array to a corresponding TSV region based on a selection signal. 18 . The method of claim 17 , wherein the test data is supplied to a corresponding TSV via the read path and returned to the switch circuit via the write path.

19. The method according to claim 15, further comprising: include: inputting a latch signal via the test pad; supplying the latch signal to a latch control circuit; and Fail information is written to a latch circuit assigned to the TSV in response to the latch signal.

20. The method according to claim 15, further comprising: include: compressing the test data to generate compressed data indicating whether the test data contains errors; and The compressed data is supplied to the test pad.

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