Activate circuits and storage devices

Abstract

This application discloses an activation circuit and a storage device. The activation circuit is used to control a storage array. The activation circuit includes: an activation signal generation circuit for generating an initial activation signal and a condition indication signal; a trimming signal generation circuit for receiving the condition indication signal and generating a trimming signal corresponding to the condition indication signal; and a control circuit for trimming the initial activation signal based on the trimming signal to obtain a target activation signal, and controlling the storage array based on the target activation signal. Based on the above method, the reliability of the storage array can be improved.

Description

Technical Field

[0001] This application relates to the field of storage control technology, and in particular to activation circuits and storage devices. Background Technology

[0002] In the prior art, existing storage devices, such as DRAM (Dynamic Random Access Memory) devices or other types of storage devices, typically have pre-stored parameters for generating tuning signals. These tuning signals can be used to tune the pulse width of activation signals input to the storage array of the storage device for activation control (such as row control), thereby making the pulse-width tuned activation signals more suitable for the storage operation of the storage device.

[0003] The drawback of existing technology is that the parameters used to generate the adjustment signal in existing storage devices are fixed parameters that are pre-programmed into the storage device. That is, the adjustment of the activation signal based on the adjustment signal corresponding to the fixed parameters is a fixed adjustment method. As a result, the activation signal has poor adaptability when the storage device is under different operating conditions and has different requirements, which can easily lead to poor stability of the storage array during operation and reduce the reliability of the storage array. Summary of the Invention

[0004] The main technical problem addressed in this application is how to improve the reliability of storage arrays.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: an activation circuit applied to control a memory array; the activation circuit includes: an activation signal generation circuit, which generates an initial activation signal and a condition indication signal; a trimming signal generation circuit, which receives the condition indication signal and generates a trimming signal corresponding to the condition indication signal; and a control circuit, which trims the initial activation signal based on the trimming signal to obtain a target activation signal, and controls the memory array based on the target activation signal.

[0006] The process of receiving a working condition indication signal and generating a trimming signal corresponding to the working condition indication signal includes: generating different trimming signals in response to different received working condition indication signals, so as to trigger the control circuit to generate target activation signals with different intensities or timings.

[0007] The operating condition indication signal includes a first indication signal and a second indication signal, the first indication signal and the second indication signal being generated under different conditions; receiving the operating condition indication signal and generating a correction signal corresponding to the operating condition indication signal includes: generating a first correction signal as a correction signal in response to receiving the first indication signal; generating a second correction signal as a correction signal in response to not receiving the first indication signal but receiving the second indication signal; and generating a third correction signal as a correction signal in response to not receiving either the first indication signal or the second indication signal.

[0008] The first indication signal is generated when the operating mode control command of the storage array is received, and the second indication signal is generated when the environmental sensing data of the storage array meets the preset conditions.

[0009] The tuning signal generation circuit includes: a first data selection unit, wherein a first input terminal of the first data selection unit is used to receive a third tuning signal, a second input terminal of the first data selection unit is used to receive a second tuning signal, a control terminal of the first data selection unit is used to receive a second indication signal, and the first data selection unit is used to output a third tuning signal in response to its control terminal not receiving the second indication signal, and to output a second tuning signal in response to its control terminal receiving the second indication signal; and a second data selection unit, wherein a first input terminal of the second data selection unit is used to receive a signal output by the first data selection unit, a second input terminal of the second data selection unit is used to receive a first tuning signal, a control terminal of the second data selection unit is used to receive a first indication signal, and the second data selection unit is used to output a signal output by the first data selection unit in response to its control terminal not receiving the first indication signal, and to output a first tuning signal in response to its control terminal receiving the first indication signal.

[0010] The control circuit includes at least one signal strength adjustment circuit. The control circuit is used to control the connection or disconnection of each branch of the signal strength adjustment circuit based on the adjustment signal. The signal strength adjustment circuit is used to adjust the signal strength of the initial activation signal.

[0011] The control circuit includes at least one pulse width adjustment circuit. The control circuit is used to control the activation and deactivation of the pulse width adjustment circuit based on the adjustment signal. The pulse width adjustment circuit is used to adjust the pulse width of the initial activation signal when activated and to maintain the pulse width of the initial activation signal when deactivated.

[0012] The adjustment signal includes adjustment data, which has at least two bits. The control circuit includes at least two pulse width adjustment circuits connected in series. Each pulse width adjustment circuit is used to receive a corresponding data control bit in the adjustment data. The pulse width adjustment circuit is used to enable the signal when the received data control bit meets a first condition and to disable the signal when the received data control bit meets a second condition. The input of the first pulse width adjustment circuit in the series-connected circuits receives an initial activation signal, and the output of the last pulse width adjustment circuit in the series-connected circuits sends a target activation signal.

[0013] The pulse width modulation circuit includes: an OR gate unit, the first input of which serves as the input of the pulse width modulation circuit, and the output of which serves as the output of the pulse width modulation circuit; a delay unit, the input of which is connected to the first input of the OR gate unit; and an AND gate unit, the first input of which is connected to the output of the delay unit, the second input of which is used to receive a corresponding data control bit in the modulation data, and the output of which is connected to the second input of the OR gate unit.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: a storage device, including a storage array and the above-mentioned activation circuit, wherein the activation circuit is used to control the storage array, and the target activation signal includes a plurality of signals for controlling the activation operation of the storage array.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the activation circuit in this application includes an activation signal generation circuit, a trimming signal generation circuit, and a control circuit. The activation signal generation circuit generates an initial activation signal and a condition indication signal. The trimming signal generation circuit receives the condition indication signal and generates a trimming signal corresponding to it. The control circuit trims the initial activation signal based on the trimming signal to obtain a target activation signal, and controls the storage array based on the target activation signal. Based on this method, the current operating condition of the storage array can be determined according to the condition indication signal, thereby generating a trimming signal adapted to the current operating condition. This trimming of the initial activation signal improves the compatibility between the trimmed target activation signal and the current operating condition of the storage array, thereby enhancing the stability of the storage array during operation and ultimately improving its reliability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of one embodiment of the activation circuit of this application;

[0018] Figure 2 This is a schematic diagram of another embodiment of the activation circuit of this application;

[0019] Figure 3 This is a schematic diagram of another embodiment of the activation circuit of this application;

[0020] Figure 4 This is a waveform diagram of an embodiment of the pulse width modulation circuit enabled in this application;

[0021] Figure 5 This is a schematic diagram of the waveforms before and after timing adjustment in this application;

[0022] Figure 6 This is a schematic diagram of an embodiment of the third adjustment circuit of this application.

[0023] Reference numerals in the attached figures: 11. Activation signal generation circuit; 12. Adjustment signal generation circuit; 121. First data selection unit; 122. Second data selection unit; 13. Control circuit; 131. Pulse width adjustment circuit; 1311. OR gate unit; 1312. Delay unit; 1313. AND gate unit; 132. Signal strength adjustment circuit; 2. Memory array. Detailed Implementation

[0024] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium. Those skilled in the art will understand the specific meanings of the above terms within the context of this application.

[0027] This application proposes an activation circuit, see [link to relevant documentation] Figures 1 to 3 , Figure 1 This is a schematic diagram of one embodiment of the activation circuit of this application. Figure 2 This is a schematic diagram of another embodiment of the activation circuit of this application. Figure 3 This is a schematic diagram of another embodiment of the activation circuit of this application, as shown below. Figures 1 to 3 As shown, the activation circuit is used to control the storage array 2.

[0028] The activation circuit includes an activation signal generation circuit 11, a trimming signal generation circuit 12, and a control circuit 13.

[0029] The activation signal generation circuit 11 is used to generate an initial activation signal and a working condition indication signal. Specifically, the activation signal generation circuit 11 can be a global control circuit, used to send a corresponding activation signal to the control circuit 13 so that the control circuit 13 activates the corresponding row storage cell in the storage array 2 to refresh the data. It can also be used to trigger the generation of working condition indication signals to characterize different working conditions in response to different preset conditions of the storage array's operating mode and / or environmental factors of the storage array.

[0030] The adjustment signal generation circuit 12 is used to receive the operating condition indication signal and generate an adjustment signal corresponding to the operating condition indication signal. Specifically, the adjustment signal generation circuit 12 can determine the current operating condition of the storage array based on the received operating condition indication signal, so as to generate an adjustment signal corresponding to the current operating condition for adjusting the initial activation signal.

[0031] The control circuit 13 is used to adjust the initial activation signal based on the adjustment signal to obtain the target activation signal, and to control the storage array 2 based on the target activation signal. Specifically, the control circuit 13 can adjust the initial activation signal based on the received adjustment signal that matches the current operating condition to obtain the target activation signal. This makes the target activation signal more suitable for controlling the operation of the storage array under the current operating condition. For example, if the pulse width of the activation signal needed to activate the storage array under the current operating condition is wider than the initial activation signal, the pulse width of the initial activation signal can be increased by the adjustment signal to obtain the target activation signal, which then controls the control circuit 13. The wider pulse width of the target activation signal better matches the operational requirements of the storage array 2 under the current operating condition, allowing the storage array 2 to operate more stably under different operating conditions under the adjustment effect of the corresponding generated adjustment signal, thus improving the reliability of the storage array.

[0032] For example, under the current operating conditions of refresh mode or low temperature mode, different adjustment signals can be generated respectively. Based on these different adjustment signals, the initial activation signal can be adjusted to obtain different target activation signals. Different target activation signals can be more adapted to the operation of storage array 2 under the corresponding operating conditions, thereby improving the reliability of storage array 2 under various types of operating conditions.

[0033] It should be noted that the activation signal specifically refers to the activation signal used to activate each row in the storage array to achieve data refresh during the storage array refresh cycle. For example, the activation signal can be a high-level signal on the word line used to activate the corresponding row storage cell for data refresh.

[0034] Trimming in chip testing is a process that involves sending trimming signals from the outside to the inside of the chip during the testing process before the chip leaves the factory, after chip manufacturing is completed. For example, after testing, the final adjusted trimming signal is burned into the chip's non-volatile memory (such as a fuse) for storage, so as to adjust the behavior corresponding to certain parameters of the chip, or change the connection method and working state of certain devices inside the chip to achieve the effect of changing the chip's performance or function.

[0035] The adjustment signal can specifically be a portion of the trim signal. The trim signal can specifically be a signal used to adjust the signal generated or received during the operation of the storage array. The signal processing adjustment can specifically be an adjustment of the amplitude, pulse width, phase, or other types of adjustment of the corresponding signal. Different parts of the trim signal can be applied to adjust different signals respectively. For example, in the technical solution of this application, a portion of the trim signal generated based on the current operating condition represented by the operating condition indication signal can be used as the adjustment signal to adjust the initial activation signal so that the target activation signal obtained after adjustment can be more adapted to the current operating condition, thereby improving the reliability of the storage array operating based on the target activation signal. The adjustment of the initial activation signal can be an adjustment of at least one of the following characteristics: amplitude, pulse width, phase, and other features. The specific adjustment can be determined according to actual needs and is not limited here.

[0036] Unlike existing technologies, the activation circuit in this application includes an activation signal generation circuit, a trimming signal generation circuit, and a control circuit. The activation signal generation circuit generates an initial activation signal and a condition indication signal. The trimming signal generation circuit receives the condition indication signal and generates a trimming signal corresponding to it. The control circuit trims the initial activation signal based on the trimming signal to obtain a target activation signal and controls the storage array based on the target activation signal. Based on this method, the current operating condition of the storage array can be determined according to the condition indication signal, thereby generating a trimming signal adapted to the current operating condition. This trimming of the initial activation signal improves the compatibility between the trimmed target activation signal and the current operating condition of the storage array, thus enhancing the stability of the storage array during operation and ultimately improving its reliability.

[0037] In one embodiment, adjusting the initial activation signal based on the adjustment signal to obtain the target activation signal may specifically include:

[0038] The target activation signal is obtained by adjusting the intensity, timing, or function of the initial activation signal based on the adjustment signal.

[0039] Specifically, under the current operating conditions of refresh mode or low temperature mode, compared to the current operating conditions of normal mode, the target activation signal used to directly control the storage array 2 usually needs to have a larger pulse width than the initial activation signal. Controlling the storage array 2 based on the target activation signal with a larger pulse width can optimize power consumption, improve speed, and enhance stability.

[0040] Based on the above method, the pulse width, timing or function of the initial activation signal can be adjusted based on the corresponding adjustment signal to obtain the corresponding target activation signal. The different adjustment signals generated under different operating conditions can make the target activation signal have different pulse widths, timings or functions relative to the initial activation signal, so as to better adapt to the storage array 2 under different operating conditions, improve the stability of the storage array 2 during operation, and thus improve the reliability of the storage array 2.

[0041] For example, such as Figure 2 As shown, the control circuit 13 may include at least a first trimming circuit X, a second trimming circuit Y, and a third trimming circuit Z.

[0042] The first adjustment circuit X, the second adjustment circuit Y, and the third adjustment circuit Z can be used to adjust different characteristics of the initial activation signal. For example, the first adjustment circuit X can be used to adjust the pulse width of the initial activation signal, the second adjustment circuit Y can be used to adjust the timing of the initial activation signal, and the third adjustment circuit Z can be used to adjust the intensity of the initial activation signal.

[0043] In practice, the first trimming circuit X can be used to increase or decrease the pulse width of the initial activation signal ACT to obtain the target activation signal ACT_F. That is, it can make the pulse width of the target activation signal ACT_F larger or smaller than the pulse width of the initial activation signal ACT, thus achieving timing trimming. The first trimming circuit X can be based on Trim... <n:0>The first bit group in the signal confirms the pulse width amplitude to be adjusted or the target pulse width to be adjusted, so as to perform corresponding pulse width adjustment on the initial activation signal ACT to obtain the target activation signal ACT_F.

[0044] See Figure 5 , Figure 5 This is a schematic diagram of the waveforms before and after timing adjustment in this application, as shown below. Figure 5 As shown, the second trimming circuit Y can be used to delay the initial activation signal ACT, for example, by a delay of duration D, so that the target activation signal ACT_F has a delay of D relative to the initial activation signal ACT, thus achieving timing trimming. The second trimming circuit Y can be based on Trim... <n:0>The second bit group in the sequence confirms the required delay duration D, so as to perform corresponding timing adjustments on the initial activation signal ACT to obtain the target activation signal ACT_F.

[0045] See Figure 6 , Figure 6 This is a schematic diagram of an embodiment of the third adjustment circuit of this application, as shown below. Figure 6 As shown, the third trimming circuit Z may include at least two switching transistors, and the third trimming circuit Z may receive Trim... <n:0>The third bit group is used to receive corresponding bits from each switch. The first terminal of the switch receives the power supply voltage VIN, and the second terminal outputs a voltage signal VOUT. An initial activation signal or a target activation signal is generated based on the voltage signal VOUT. In other words, the signal strength of the initial activation signal or the target activation signal can be adjusted by controlling the conduction of different numbers of switches. Taking two switches as an example, the driving terminal of one switch can receive Z1 from the third bit group, and the driving terminal of the other switch can receive Z2 from the third bit group. By assigning different combinations of values ​​to Z1 and Z2, different adjustments to the signal strength can be achieved.

[0046] It is worth noting that in other embodiments of the present invention, it may include only one or more of the first trimming circuit X, the second trimming circuit Y, and the third trimming circuit Z, and correspondingly, Trim <n:0>This includes any combination of one or more of the first bit group, the second bit group, and the third bit group; that is, the first bit group, the second bit group, and the third bit group are all Trim. <n:0>In addition, other types of adjustment circuits can be set in the control circuit 13 to perform corresponding adjustment processing based on the sequence of other parts. The specifics can be determined according to the requirements and are not limited here.

[0047] Optionally, such as Figure 6 As shown, the third trimming circuit Z in the control circuit 13 may include at least one signal strength adjustment circuit 132. The control circuit 13 is used to control the connection or disconnection of each branch of the signal strength adjustment circuit 132 based on the trimming signal. The signal strength adjustment circuit 132 is used to adjust the signal strength of the initial activation signal.

[0048] Specifically, for example, such as Figure 6 As shown, a signal strength adjustment circuit 132 may specifically include a switching transistor, and a third trimming circuit Z may receive a Trim transistor. <n:0>The corresponding part of the sequence is used to receive the corresponding bit in the corresponding part of the sequence. The first end of the switch is used to receive the power supply voltage VIN, and the second end of the switch is used to output the voltage signal VOUT. The initial activation signal or the target activation signal is generated based on the voltage signal VOUT. That is, by controlling the on or off of different numbers of switches, the connection or disconnection of each branch of the control signal strength adjustment circuit 132 can be realized, thereby adjusting the signal strength of the initial activation signal or the target activation signal.

[0049] like Figure 6 As shown, taking two switching transistors as an example, the driving terminal of one switching transistor can receive Z1 from the corresponding part of the sequence, and the driving terminal of the other switching transistor can receive Z2 from the corresponding part of the sequence. By assigning different combinations of values ​​to Z1 and Z2, the switching transistors of different combinations can be turned on and off, thereby realizing the connection or disconnection of each branch of the control signal strength adjustment circuit 132, and thus realizing different adjustments to the signal strength.

[0050] Similarly, the third adjustment circuit Z may also include other numbers of switching transistors to adjust the signal strength at more levels; this is not limited here.

[0051] Optionally, such as Figure 3 As shown, the first trimming circuit X in the control circuit 13 may include at least one pulse width trimming circuit 131. The control circuit 13 is used to control the activation and deactivation of the pulse width trimming circuit 131 based on the trimming signal. The pulse width trimming circuit 131 is used to trim the pulse width of the initial activation signal when activated and to maintain the pulse width of the initial activation signal when deactivated.

[0052] Specifically, the pulse width modulation circuit 131 can be used to widen or reduce the pulse width of the passed signal, or to maintain the pulse width. Which of these three processes is performed is determined by the corresponding bits of the modulation data contained in the modulation signal received by the pulse width modulation circuit 131. That is, each pulse width modulation circuit 131 can be controlled by the modulation signal to be in an enabled or disabled state. Therefore, by making the modulation signals different under different operating conditions, the number of pulse width modulation circuits 131 activated and / or the objects of activated pulse width modulation circuits 131 can be different under different operating conditions, thereby making the initial activation signal (such as...) different. Figure 3 The ACT signal shown sequentially passes through all pulse width modulation circuits 131, and then undergoes pulse width modulation processing by the activated pulse width modulation circuits 131, thereby improving the target activation signal obtained after pulse width modulation (such as...). Figure 3 The adaptability of ACT_F shown to the current operating conditions of storage array 2 is improved, thereby enhancing the stability of storage array 2.

[0053] Furthermore, the tuning signal includes tuning data, which has at least two bits.

[0054] like Figure 3 As shown, the control circuit 13 includes:

[0055] At least two pulse width modulation circuits 131 are connected in series. Each pulse width modulation circuit 131 is used to receive a corresponding data control bit in the modulation data. The pulse width modulation circuit 131 is used to enable the pulse width modulation circuit when the received data control bit meets a first condition and to disable the pulse width modulation circuit when the received data control bit meets a second condition. The input terminal of the first pulse width modulation circuit 131 in the at least two pulse width modulation circuits 131 connected in series receives an initial activation signal, and the output terminal of the last pulse width modulation circuit 131 in the at least two pulse width modulation circuits 131 connected in series sends a target activation signal.

[0056] Specifically, as described in the preceding embodiments, the trimming signal can be a portion of the trimming signal. The information contained in this portion of the trimming signal can specifically refer to trimming data with at least two bits. At least two pulse width trimming circuits 131 connected in series receive different bits of this trimming data, such as receiving the trimming signal... <0> Trim <1> ...Trim <n>The data in the data includes a pulse width modulation circuit 131 that can be enabled when the corresponding bit of the received modulation data is 1 to perform pulse width modulation (increase or decrease the pulse width) on the passed signal, and disabled when the corresponding bit of the received modulation data is 0 to perform pulse width maintenance on the passed signal.

[0057] Based on the above method, the initial activation signal (such as...) can be made... Figure 3 The ACT signal shown sequentially passes through all pulse width modulation circuits 131, and then the pulse width of each pulse width modulation circuit 131 is adjusted by the activated pulse width modulation circuits 131 to improve the target activation signal obtained after pulse width modulation (such as...). Figure 3 The adaptability of ACT_F shown to the current operating conditions of storage array 2 is improved, thereby enhancing the stability of storage array 2.

[0058] Furthermore, such as Figure 3 As shown, the pulse width modulation circuit 131 includes an OR gate unit 1311, a delay unit 1312, and an AND gate unit 1313.

[0059] The first input terminal of the OR gate unit 1311 serves as the input terminal of the pulse width adjustment circuit 131, and the output terminal of the OR gate unit 1311 serves as the output terminal of the pulse width adjustment circuit 131.

[0060] The input terminal of the delay unit 1312 is connected to the first input terminal of the OR gate unit 1311.

[0061] The first input terminal of AND gate unit 1313 is connected to the output terminal of delay unit 1312, the second input terminal of AND gate unit 1313 is used to receive a corresponding data control bit in the trimming data, and the output terminal of AND gate unit 1313 is connected to the second input terminal of OR gate unit 1311.

[0062] Specifically, see Figure 4 , Figure 4 This is a waveform diagram of an embodiment of the pulse width modulation circuit enabled in this application.

[0063] like Figure 3 As shown, when the data control bit received at the second input terminal of AND gate unit 1313 is 1, the signal output by the output terminal of AND gate unit 1313, relative to the signal input at the first input terminal of OR gate unit 1311, is a delayed signal, that is, as shown... Figure 4 As shown, taking the first pulse width adjustment circuit 131 as an example, the data control bit received at the second input terminal of the AND gate unit 1313 is 1. After the initial activation signal ACT is input to the delay unit 1312, the signal after the delay processing of the delay unit 1312 can be output as the delayed signal ACT_D through the output terminal of the AND gate unit 1313. The delayed signal ACT_D is the signal obtained after delay processing of the initial activation signal ACT. By inputting the initial activation signal ACT and the delayed signal ACT_D into the two input terminals of the OR gate unit 1311 respectively, the pulse width of the signal output by the OR gate unit 1311 can be increased, and the first pulse width amplification signal ACT_1 obtained after the pulse width amplification processing of the first pulse width adjustment circuit 131 is obtained.

[0064] Subsequently, as the initial activation signal ACT passes through all the pulse width adjustment circuits 131 in sequence, each time it passes through a pulse width adjustment circuit 131, if the pulse width adjustment circuit 131 it passes through is deactivated, the pulse width of the signal remains unchanged; if the pulse width adjustment circuit 131 it passes through is activated, the pulse width of the signal it passes through increases. The final output ACT_F is the target activation signal.

[0065] It should be noted that, in all pulse width modulation circuits 131, the delay time corresponding to the delay unit 1312 of any two pulse width modulation circuits 131 can be different or the same when performing delay processing. That is, after the signal is processed by any two pulse width modulation circuits 131, the increase in pulse width can be different or the same, which is not limited here.

[0066] Based on the above method, the pulse width adjustment circuit 131 can be constructed using simple gate devices, and the function of increasing the pulse width to different degrees based on the adjustment signal can be realized, thereby improving the structural and functional stability of the pulse width adjustment circuit 131.

[0067] In one embodiment, receiving a condition indication signal and generating a trimming signal corresponding to the condition indication signal may specifically include:

[0068] In response to different received operating condition indication signals, different adjustment signals are generated to trigger the control circuit 13 to generate target activation signals with different intensities or timings.

[0069] Specifically, under different operating conditions, such as when storage array 2 is in refresh mode, low temperature mode, or other types of modes, the operating conditions faced by storage array 2 are usually different. In this case, it is usually necessary to use target activation signals generated by different tuning processes to control storage array 2 under different operating conditions in order to meet the activation requirements of the corresponding operating conditions. For example, the timing of the signal may specifically include the pulse width of the signal. That is, a target activation signal with corresponding timing (with corresponding pulse width) can be generated based on the tuning signal. Under one operating condition, the pulse width of the target activation signal may need to be relatively large, while under another operating condition, the pulse width of the target activation signal may need to be relatively small. Therefore, by generating different tuning signals under the indication of the operating condition indication signals corresponding to different operating conditions to adapt to the storage array 2 under the corresponding operating conditions, the stability and reliability of storage array 2 during operation can be effectively improved.

[0070] It should be noted that in other examples, target activation signals of different intensities, or target activation signals of different timing (pulse width or other timing parameters other than pulse width), or target activation signals of different combinations of intensities and timing can be generated based on different operating condition indication signals, without limitation here.

[0071] Optionally, the operating condition indication signal includes a first indication signal and a second indication signal, and the first indication signal and the second indication signal are generated under different conditions.

[0072] Receive operating condition indication signals and generate adjustment signals corresponding to the operating condition indication signals, including:

[0073] In response to receiving the first indication signal, a first adjustment signal is generated as the adjustment signal.

[0074] In response to the absence of a first indication signal and the receipt of a second indication signal, a second adjustment signal is generated as the adjustment signal.

[0075] In response to the absence of both the first and second indication signals, a third adjustment signal is generated as the adjustment signal.

[0076] Specifically, the first indication signal and the second indication signal can be indication signals with different processing priorities. The processing priority of the first indication signal can be higher than that of the second indication signal. If the first indication signal is received, the first adjustment signal is used as the adjustment signal regardless of whether the second indication signal is received. If the first indication signal is not received, the second adjustment signal or the third adjustment signal is used as the adjustment signal by determining whether the second indication signal is received. This enables the generation of different adjustment signals that meet the requirements of the corresponding working conditions based on different combinations of the received first and second indication signals.

[0077] For example, the first indication signal can be a signal generated when the operating mode control command of the storage array 2 is received, such as the refresh mode indication signal REF. The second indication signal can be a signal generated when the environmental sensing data of the storage array 2 meets the preset conditions, such as the low temperature mode indication signal LT. When the refresh mode indication signal REF is received, the adjustment signal is determined directly based on the refresh mode indication signal REF. When the refresh mode indication signal REF is not received, the type of adjustment signal to generate is determined by whether the low temperature mode indication signal LT is received, so that the adjustment signal is more suitable for the storage array 2 operating under the corresponding conditions, thereby improving the stability and reliability of the storage array 2.

[0078] The above are merely illustrative examples. In other examples, the refresh mode indicator signal REF can be replaced with other types of signals related to the operating mode of the storage array 2, such as the self-refresh mode indicator signal, the hibernation mode indicator signal, or other types of operating mode indicator signals. This is not limited here. Similarly, the low temperature mode indicator signal LT can be replaced with other types of signals related to the detection conditions of the environment in which the storage array 2 is located, such as the high temperature mode indicator signal, the low humidity mode indicator signal, the high humidity mode indicator signal, the jitter mode indicator signal, or other types of signals related to the detection conditions of the environment in which the storage array 2 is located. This is not limited here.

[0079] Furthermore, such as Figure 3 As shown, the tuning signal generation circuit 12 includes a first data selection unit 121 and a second data selection unit 122.

[0080] The first input terminal of the first data selection unit 121 is used to receive a third trimming signal, the second input terminal of the first data selection unit 121 is used to receive a second trimming signal, the control terminal of the first data selection unit 121 is used to receive a second indication signal, and the first data selection unit 121 is used to output a third trimming signal in response to its control terminal not receiving a second indication signal, and to output a second trimming signal in response to its control terminal receiving a second indication signal.

[0081] The first input terminal of the second data selection unit 122 is used to receive the signal output by the first data selection unit 121. The second input terminal of the second data selection unit 122 is used to receive the first adjustment signal. The control terminal of the second data selection unit 122 is used to receive the first indication signal. The second data selection unit 122 is used to output the signal output by the first data selection unit 121 in response to its control terminal not receiving the first indication signal, and to output the first adjustment signal in response to its control terminal receiving the first indication signal.

[0082] Specifically, both the first data selection unit 121 and the second data selection unit 122 can be data selectors, which output when the indication signal (such as the refresh mode indication signal REF or the low temperature mode indication signal LT) received at their control terminals is 0. Figure 3 The signal input to the terminal corresponding to the "0" symbol will output a signal when the control terminal receives an indication signal of "1". Figure 3 The signal input to the input terminal corresponds to the symbol "1".

[0083] like Figure 3 As shown, when the refresh mode indicator signal REF is 1 and the low temperature mode indicator signal LT is any value, Trim... <n:0>That is, Trim_REF <n:0>.

[0084] When the refresh mode indicator signal REF is 0 and the low temperature mode indicator signal LT is 1, Trim <n:0>That is, Trim_LT <n:0>.

[0085] When the refresh mode indicator signal REF is 0 and the low temperature mode indicator signal LT is 0, Trim <n:0>That is, Trim_ACT <n:0>.

[0086] Based on the above method, a trimming signal generation circuit 12 with the processing priority related functions described in the previous embodiment can be constructed based on the structure of the cascaded data selector. When the trimming signal generation circuit 12 can generate more types of trimming signals according to more types of indicator signals, more data selection units can be cascaded on the basis of the first data selection unit 121 and the second data selection unit 122. That is, the stability and scalability of the trimming signal generation circuit 12 are both high.

[0087] This application also proposes a storage device, such as Figures 1 to 3 As shown, the storage device includes the activation circuit and storage array 2 described in any of the preceding embodiments, wherein the activation circuit is used to control the storage array 2.

[0088] Specifically, storage devices can refer to DRAM (Dynamic Random Access Memory) devices or other types of storage devices, depending on actual needs, and are not limited here.

[0089] Unlike existing technologies, the activation circuit in this application includes an activation signal generation circuit, a trimming signal generation circuit, and a control circuit. The activation signal generation circuit generates an initial activation signal and a condition indication signal. The trimming signal generation circuit receives the condition indication signal and generates a trimming signal corresponding to it. The control circuit trims the initial activation signal based on the trimming signal to obtain a target activation signal and controls the storage array based on the target activation signal. Based on this method, the current operating condition of the storage array can be determined according to the condition indication signal, thereby generating a trimming signal adapted to the current operating condition. This trimming of the initial activation signal improves the compatibility between the trimmed target activation signal and the current operating condition of the storage array, thus enhancing the stability of the storage array during operation and ultimately improving its reliability.

[0090] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0091] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0092] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0093] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0094] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application. < / n>

Claims

1. An activation circuit, characterized in that, Used to control storage arrays; The activation circuit includes: An activation signal generation circuit is used to generate an initial activation signal and a working condition indication signal. A trimming signal generation circuit, wherein the trimming signal generation circuit is used to receive the operating condition indication signal and generate a trimming signal corresponding to the operating condition indication signal; and A control circuit is configured to adjust the initial activation signal based on the adjustment signal to obtain a target activation signal, and to control the storage array based on the target activation signal. The control circuit includes at least one pulse width adjustment circuit. The control circuit is used to control the activation and deactivation of the pulse width adjustment circuit based on the adjustment signal. The pulse width adjustment circuit is used to adjust the pulse width of the initial activation signal when activated and to maintain the pulse width of the initial activation signal when deactivated.

2. The activation circuit according to claim 1, characterized in that, The step of receiving the operating condition indication signal and generating a trim signal corresponding to the operating condition indication signal includes: In response to different received operating condition indication signals, different adjustment signals are generated to trigger the control circuit to generate target activation signals with different intensities or timings.

3. The activation circuit according to claim 2, characterized in that, The operating condition indication signal includes a first indication signal and a second indication signal, and the first indication signal and the second indication signal are generated under different conditions; The step of receiving the operating condition indication signal and generating a trim signal corresponding to the operating condition indication signal includes: In response to receiving a first indication signal, a first adjustment signal is generated as the adjustment signal; In response to not receiving the first indication signal and receiving the second indication signal, a second adjustment signal is generated as the adjustment signal; In response to the failure to receive the first indication signal and the failure to receive the second indication signal, a third adjustment signal is generated as the adjustment signal.

4. The activation circuit according to claim 3, characterized in that, The first indication signal is generated when the operating mode control command of the storage array is received, and the second indication signal is generated when the environmental sensing data of the storage array meets the preset conditions.

5. The activation circuit according to claim 3 or 4, characterized in that, The adjustment signal generation circuit includes: A first data selection unit, wherein a first input terminal of the first data selection unit is used to receive the third adjustment signal, a second input terminal of the first data selection unit is used to receive the second adjustment signal, a control terminal of the first data selection unit is used to receive the second indication signal, and the first data selection unit is used to output the third adjustment signal in response to its control terminal not receiving the second indication signal, and to output the second adjustment signal in response to its control terminal receiving the second indication signal. The second data selection unit has a first input terminal for receiving the signal output by the first data selection unit, a second input terminal for receiving the first adjustment signal, a control terminal for receiving the first indication signal, and is configured to output the signal output by the first data selection unit in response to its control terminal not receiving the first indication signal, and to output the first adjustment signal in response to its control terminal receiving the first indication signal.

6. The activation circuit according to any one of claims 1 to 4, characterized in that, The control circuit includes at least one signal strength adjustment circuit, which is used to control the connection or disconnection of each branch of the signal strength adjustment circuit based on the adjustment signal. The signal strength adjustment circuit is used to adjust the signal strength of the initial activation signal.

7. The activation circuit according to any one of claims 1 to 4, characterized in that, The adjustment signal includes adjustment data, and the adjustment data has at least two bits. The control circuit includes: At least two pulse width modulation circuits are connected in series. Each pulse width modulation circuit is used to receive a corresponding data control bit in the modulation data. The pulse width modulation circuit is enabled in response to the received data control bit satisfying a first condition and disabled in response to the received data control bit satisfying a second condition. The input terminal of the first pulse width modulation circuit in the at least two pulse width modulation circuits connected in series receives the initial activation signal, and the output terminal of the last pulse width modulation circuit in the at least two pulse width modulation circuits connected in series sends the target activation signal.

8. The activation circuit according to claim 7, characterized in that, The pulse width adjustment circuit includes: An OR gate unit, wherein the first input terminal of the OR gate unit serves as the input terminal of the pulse width adjustment circuit, and the output terminal of the OR gate unit serves as the output terminal of the pulse width adjustment circuit; A delay unit, wherein the input terminal of the delay unit is connected to the first input terminal of the OR gate unit; An AND gate unit is provided, wherein the first input of the AND gate unit is connected to the output of the delay unit, the second input of the AND gate unit is used to receive a corresponding data control bit in the adjustment data, and the output of the AND gate unit is connected to the second input of the OR gate unit.

9. A storage device, characterized in that, The device includes a storage array and an activation circuit as described in any one of claims 1 to 8, the activation circuit being used to control the storage array, wherein the target activation signal includes a plurality of signals for controlling the activation operation of the storage array.

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