Manufacturing method of semiconductor isolation structure

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a method for manufacturing a semiconductor isolation structure, which comprises the following steps of: (1) forming a plurality of shallow isolation corrosion grooves on one surface of a monocrystalline silicon substrate by using an STI (shallow trench isolation) process; forming a plurality of deep isolation corrosion grooves in the other surface of the monocrystalline silicon substrate by using a Trench process; (2) etching and forming an isolation channel with the design thickness of d1 on the monocrystalline silicon substrate with the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves by using a wet etching process, so that the isolation channel, the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves are communicated with one another to form an isolation structure; and (3) putting the monocrystalline silicon substrate with the isolation structure into thermal oxidation equipment, filling the isolation structure with silicon dioxide by using a thermal oxidation process, and expanding the thickness of an isolation channel from a design thickness d1 to a target thickness d2. The isolation structure prepared by the method is good in electrical isolation capability, and can meet the requirements of products with high working voltage and large working current.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor isolation structure. Background Art

[0002] Electrical isolation is the key to the design and manufacture of advanced semiconductor devices. With the development of technology, the current semiconductor isolation structure is prepared by using SOI (Silicon-On-Insulator) chips as substrates and STI (shallow trench isolation) processes. The silicon dioxide insulation layer in the SOI chip isolates the interference and parasitic capacitance of the substrate on the device, and the shallow trenches filled with silicon dioxide separate the adjacent devices from each other to prevent lateral current leakage and signal interference between them. However, since the SOI chip manufacturing method includes oxygen ion implantation and bonding, the former has an incomplete structure, low dielectric strength, and many body defects due to the influence of oxygen ion implantation dose and silicon atom density. High-energy and high-dose implantation also causes many substrate lattice defects and reduces electrical isolation capability. The latter has high impurity content, poor dielectric strength and compactness, and many defects on the contact surface of the two substrates, which reduces the electrical isolation capability. The silicon dioxide insulation layer of the SOI chip is of low quality, resulting in insufficient electrical isolation capability of the current method combining SOI chips and STI processes, which is difficult to meet the isolation requirements of high-power devices and MEMS devices involving working voltages of up to tens of thousands of volts and working currents of tens of thousands of amperes.

[0003] Silicon dioxide obtained by thermal oxidation has the characteristics of complete structure, high purity, high dielectric strength, good compactness and low defect density. Thermal oxidation can be used to prepare high-quality silicon dioxide to improve the electrical isolation capability of SOI substrate. For example, Chinese patent CN103262222B discloses a method for forming a thermal oxide film on a single crystal silicon wafer. Silicon dioxide is grown in stages on the surface of a single crystal silicon wafer through a combination of low-temperature oxidation, cooling and high-temperature oxidation to form a thermal oxide film, and then a SOI chip is formed through a bonding method. However, this method is not suitable for filling silicon dioxide in the isolation structure inside the substrate. On the one hand, large temperature changes will cause the isolation structure to deform, squeeze the space of the surrounding active area or other functional structures, and increase the difficulty of chip design. On the other hand, due to the uneven distribution of oxidants in the isolation structure, the growth rate of silicon dioxide is different, resulting in incomplete filling of the isolation structure, reducing the electrical isolation capability of the chip. Summary of the invention

[0004] In order to solve the technical problem of low electrical isolation capability of the above-mentioned chip, the present invention provides a method for manufacturing a semiconductor isolation structure, which uses a thermal oxidation process to fill silicon dioxide in the isolation structure inside the substrate. The formed silicon dioxide is complete, thereby improving the electrical isolation capability of the chip to meet the needs of high operating voltage and large operating current products.

[0005] The specific technical solution of the present invention is: a method for manufacturing a semiconductor isolation structure, comprising the following steps: (1) using the STI process to open a plurality of shallow isolation etching grooves on one side of the single crystal silicon substrate; using the Trench process to open a plurality of deep isolation etching grooves on the other side of the single crystal silicon substrate; (2) A single crystal silicon substrate having a plurality of shallow isolation etching grooves and a plurality of deep isolation etching grooves is etched to open a design thickness of d by using a wet etching process. 1 The isolation channel, the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves are interconnected to form an isolation structure; (3) The single crystal silicon substrate with the isolation structure is placed in a thermal oxidation device, with the side with several deep isolation etching grooves facing upward, and the isolation structure is filled with silicon dioxide by a thermal oxidation process so that the thickness of the isolation channel is reduced from the designed thickness d 1 Expand to target thickness d 2 , wherein the thermal oxidation process includes: The thermal oxidation equipment is heated to a temperature T 1 , so that the isolation channel forms a thickness x inwardly 1 The silicon dioxide layer extends outward to a thickness of y 1 A silicon dioxide layer; Cool the thermal oxidation equipment to 1000-1100°C and then heat it up to T 2 , T 2 >T 1 , so as to add thickness x inwards 2 The silicon dioxide layer is added with a thickness of y 2 A silicon dioxide layer; Among them, d 1 It is the total thickness of the silicon dioxide layer formed inward from the isolation channel.

[0006] The present invention utilizes an STI process, a trench process, and a wet etching process to form a continuous isolation structure in a single crystal silicon substrate, and adopts a thermal oxidation process to fill a silicon dioxide isolation medium in the isolation structure. During the thermal oxidation process, the trench surface is kept facing upward, and from top to bottom, a deep isolation etching groove, an isolation channel, and a shallow isolation etching groove are formed to form a funnel structure. The oxidant density in the isolation channel in the funnel structure is greater than the oxidant density in the deep isolation etching groove and the shallow isolation etching groove, so that at the same process temperature, the oxidation rate of the isolation channel is faster than the oxidation rate of the deep isolation etching groove and the shallow isolation etching groove, thereby avoiding the deep isolation etching groove and the shallow isolation etching groove from being closed in advance, resulting in incomplete filling of silicon dioxide in the isolation channel. At the same time, the thickness of the initially opened isolation channel is less than the target thickness required in the end, and the segmented growth of silicon dioxide in the isolation structure is controlled by segmented temperature increase. The silicon dioxide generated in the lower temperature segment provides more reactive sites for subsequent reactions, and promotes the silicon dioxide to grow outward along the boundary of the isolation channel, so as to increase the thickness of the isolation channel from the designed thickness d to the desired thickness. 1 Expand to target thickness d 2 , ensuring that silicon dioxide is filled synchronously in the isolation channel, deep isolation etching groove and shallow isolation etching groove. Furthermore, cooling to 1000-1100℃ and then heating up can prevent adhesion between the silicon wafer and the wafer boat, and prevent deformation of the isolation structure due to thermal expansion and contraction, thereby realizing the thermal oxidation process to fill the isolation structure inside the substrate with complete silicon dioxide, improving the electrical isolation capability of the chip to meet the needs of high operating voltage and large operating current products; in addition, the isolation medium fills the funnel-shaped isolation channel at one time, so that a continuous insulating dielectric layer is constructed between the devices and between the device and the substrate. The silicon dioxide in the deep isolation etching groove in the vertical direction, the shallow isolation etching groove and the isolation channel in the horizontal direction jointly construct a full dielectric isolation environment. The formed isolation structure is complete and has no connection gaps, further improving the electrical isolation capability of the chip.

[0007] Preferably, in step (3), d 2 =1.4~1.8d 1 .

[0008] Preferably, in step (3), y 1 0.4~0.8x 1 ,y 2 0.4~0.8x 2 .

[0009] Preferably, in step (3), x 2 0.8~1.2x 1 .

[0010] Preferably, in step (3), T 1 ≥1200℃,T 2 T1 10~20℃ higher.

[0011] Preferably, in step (3), the heating rate is <0.2°C / Min.

[0012] During the growth of silicon dioxide, thermal stress will be generated between the silicon in the substrate and silicon dioxide. When the heating rate is too fast, the stress will accumulate rapidly, causing deformation of the substrate. By precisely controlling the heating rate of the thermal oxidation process, the accumulated heat can be released and the substrate structure can be stabilized.

[0013] Preferably, in step (3), the cooling rate is <0.15°C / Min.

[0014] During the growth of silicon dioxide, thermal stress will be generated between the silicon in the substrate and silicon dioxide. When the cooling rate is too fast, the stress will accumulate rapidly, causing the substrate to crack. By precisely controlling the cooling rate of the thermal oxidation process, the accumulated heat can be released and the substrate structure can be stabilized.

[0015] Preferably, in step (3), the thermal oxidation process further comprises: After cooling to 1000-1100℃, heat the thermal oxidation equipment to temperature T 3 , T 3 >T 2 , so as to add thickness x inwards 3 The silicon dioxide layer, x 3 0.8~1.2x 1 , and add thickness y 3 The silicon dioxide layer, y 3 0.4~0.8x 3 ; After cooling to 1000-1100℃, heat the thermal oxidation equipment to temperature T 4 , T 4 >T 3 , so as to add thickness x inwards 4 The silicon dioxide layer, x 4 0.8~1.2x 1 , and add thickness y 4 Silicon dioxide layer, y4 is 0.4~0.8x 4 .

[0016] Preferably, in step (3), T4≤1260°C.

[0017] Preferably, in step (2), the thickness of the shallow isolation etching groove is d 3 , the thickness of the deep isolation etching groove is d 4 , d 3 =0.6~0.8d 1 , and d4 =0.6~0.8d 1 .

[0018] When the thickness of the shallow isolation etching groove and the deep isolation etching groove is too large, the isolation channel closes before the shallow isolation etching groove and the deep isolation etching groove, and a small amount of gas molecules remain in the structure and gather. The pressure increases under high temperature, which lifts up the isolation channel and deforms the isolation structure. When the thickness of the shallow isolation etching groove and the deep isolation etching groove is too small, the deep isolation etching groove and the shallow isolation etching groove close prematurely, resulting in incomplete filling of silicon dioxide in the isolation channel. When the thickness of the shallow isolation etching groove and the deep isolation etching groove is within the above range, silicon dioxide is filled completely and evenly in the isolation structure and will not deform.

[0019] Compared with the prior art, the present invention has the following advantages: (1) Good electrical isolation capability: The present invention utilizes the STI process, the Trench process, and the wet etching process to form a continuous isolation structure in a single crystal silicon substrate, and uses a thermal oxidation process to fill the isolation structure with silicon dioxide isolation medium, thereby achieving a complete filling of silicon dioxide in the isolation structure inside the substrate by the thermal oxidation process, thereby improving the electrical isolation capability of the chip to meet the requirements of products with high operating voltage and large operating current; (2) One-time filling of the isolation structure: A continuous insulating dielectric layer is constructed between devices and between the device and the substrate. The deep isolation etching grooves in the vertical direction, the shallow isolation etching grooves, and the silicon dioxide in the isolation channels in the horizontal direction jointly construct a fully dielectric isolation environment. The isolation structure formed is complete and has no joint gaps. (3) Low cost: SOI chips are expensive. This solution directly uses ordinary single-crystal silicon chips, reducing chip costs by more than 60%. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a top view of the isolation structure after being filled with silicon dioxide according to the present invention; Figure 2 is a cross-sectional view of the isolation structure after being filled with silicon dioxide according to the present invention; Figure 3 is a schematic diagram of steps 1-6 in Example 1; Figure 4 is a schematic diagram of steps 7-10 in Example 1; Figure 5 This is the electrical test schematic diagram in Comparative Example 4.

[0021] Figure numerals: 1. mask layer; 2. front photoresist; 3. shallow isolation etching window; 4. shallow isolation etching groove; 5. back photoresist; 6. deep isolation etching window; 7. deep isolation etching groove; 8. protective oxide layer; 9. shallow isolation channel etching window; 10. deep isolation channel etching window; 11. isolation channel; 18. device A; 19. device B; 20. electric field concentration area; 21. test circuit external resistor; 22. current loop. DETAILED DESCRIPTION

[0022] The present invention is described below by specific examples. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. Without departing from the spirit and scope of the inventive concept, changes and advantages that can be thought of by those skilled in the art are included in the present invention, and the attached claims and any equivalents thereof are the protection scope of the present invention.

[0023] Unless otherwise defined, all technical terms and scientific terms used in the present invention have the same meanings as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. Unless otherwise specified, the raw materials and equipment used in the present invention are conventional raw materials and equipment in the field and can be obtained from conventional commercial channels; unless otherwise specified, the methods used in the present invention are conventional methods in the field.

[0024] In the present invention, the solution used is as follows: The composition of SC3 solution is H 2 SO 4 :H 2 O 2 =5:1; The composition of DHF solution is HF:H 2 O=1:100; The composition of SC1 solution is NH 4 OH:H 2 O 2 :H 2 O=1:1:7; The composition of SC2 solution is HCL:H 2 O 2 :H 2 O=1:1:7.

[0025] Embodiment 1: Reference Figures 1 to 4 As shown, the present invention provides a method for manufacturing a semiconductor isolation structure, comprising the following steps: Step 1: Place the single crystal silicon substrate into the RCA wet cleaning equipment, clean it with SC3 solution at 120°C for 10 minutes, drain and rinse it, soak it in DHF solution at room temperature for 30 seconds, then rinse it with SC1 solution at 65°C for 10 minutes, and finally rinse it with SC2 solution at 65°C for 10 minutes to complete the cleaning; Step 2: Place the cleaned single crystal silicon substrate into an oxidation furnace, heat the oxidation furnace to 1000°C, and introduce O into the oxidation furnace at a flow rate of 8LSM. 2 , so that SiO with a thickness of 3500A is grown on the front and back surfaces of the substrate 2 layer, serving as a mask layer 1 for subsequent etching; Step 3: Place the single crystal silicon substrate with the mask layer 1 into a coating and developing machine, apply a layer of front photoresist 2 on the front side thereof, and after exposure and development, place the substrate into a photolithography machine for front STI photolithography to open a number of shallow isolation etching windows 3; Step 4: Place a single crystal silicon substrate having a plurality of shallow isolation etching windows 3 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, open each shallow isolation etching window 3, then put it into the Si dry etching machine, through SF 6 With O 2 The combined gas performs Si dry etching on each shallow isolation etching window 3 to form a plurality of shallow isolation etching grooves 4; Step 5: Place the single crystal silicon substrate with several shallow isolation etching grooves 4 into a coating and developing machine, apply a layer of back photoresist 5 on the back side, and after exposure and development, place it into a photolithography machine for back trench lithography to open several deep isolation etching windows 6; Step 6: Place the single crystal silicon substrate with several deep isolation etching windows 6 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, open each deep isolation etching window 6, and then put it into the Si dry etching machine using Bosch technology, through SF 6 With O 2 The combined gas performs Si dry etching on each deep isolation etching window 6 to form a plurality of deep isolation etching grooves 7; Step 7: Place the single crystal silicon substrate having a plurality of shallow isolation etching grooves 4 and a plurality of deep isolation etching grooves 7 into an oxidation furnace, heat the oxidation furnace to 1000° C., and introduce O into the oxidation furnace at a flow rate of 8 LSM. 2 , so that SiO with a thickness of 1000 Å is grown on the surface of each shallow isolation etching groove 4 and each deep isolation etching groove 7 2 Layer, as a protective oxide layer 8 for subsequent wet etching; Step 8: Place the single crystal silicon substrate with protective oxide layer 8 into the SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, EtchBack (reverse etching) removes the protective oxide layer 8 at the bottom of each shallow isolation etching groove 4, opens a plurality of shallow isolation channel 11 etching windows 9, and in the reverse etching process, ions are bombarded vertically under the action of the electric field, so that the etching mainly acts on the protective oxide layer 8 in the vertical direction, and the protective oxide layer 8 on the side wall of the shallow isolation etching groove 4 is less bombarded by ions, so as to remove the protective oxide layer 8 at the bottom of the shallow isolation etching groove 4; Step 9: Turn over the single crystal silicon substrate with the etching windows 9 of the shallow isolation channels 11, remove the protective oxide layer 8 at the bottom of the deep isolation etching groove 7 by EtchBack, and open a plurality of etching windows 10 of the deep isolation channels 11; Step 10: Place the single crystal silicon substrate with a plurality of shallow isolation channels 11 etching windows 9 and a plurality of deep isolation channels 11 etching windows 10 into a wet Si etching machine, heat the wet Si etching machine to 90°C, and etch a designed thickness d on the substrate through 85% KOH solution. 1 The isolation channel 11 is connected to the isolation channel 11, the plurality of shallow isolation etching grooves 4 and the plurality of deep isolation etching grooves 7 to form an isolation structure. The corrosion reaction is divided into two steps: KOH+H 2 O→K + +2(OH-)+H + , 2(OH - )+Si+4H 2 O→[Si(OH) 6 ] 2- +2H 2 ; Step 11: Place the single crystal silicon substrate with the isolation structure on a wafer carrier boat and place it in a thermal oxidation device, with the side with the deep isolation etching grooves 7 facing upward, and heat the thermal oxidation device to a temperature T 1 , T 1 The temperature was 1200℃, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is formed inwardly with a thickness x 1 The silicon dioxide layer extends outward to a thickness of y 1 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1000℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T2 , T 2 The temperature was 1220℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 2 The silicon dioxide layer is added with a thickness of y 2 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1000℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 3 , T 3 The temperature was 1240℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 3 The silicon dioxide layer is added with a thickness of y 3 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1000℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 4 , T 4 The temperature was 1260℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 4 The silicon dioxide layer is added with a thickness of y 4 The silicon dioxide layer is filled with silicon dioxide to fill the isolation structure and make the thickness of the isolation channel 11 by the designed thickness d 1 Expand to target thickness d 2 , forming Figure 1 and 2 The structure shown.

[0026] In this embodiment, the width of the shallow isolation etching window 3 is 5.5 microns, the depth of the shallow isolation etching groove 4 is 15 microns, the width of the deep isolation etching window 6 is 5.5 microns, and the isolation channel 11 is designed to have a thickness d 1 The target thickness is 7.1 μm. 2 The depth of the deep isolation etching groove 7 is 10 microns, and the depth of the deep isolation etching groove 7 is the thickness of the substrate minus the depth of the shallow isolation etching groove 4 and the designed thickness of the isolation channel 11. 1 1.5 microns, y 1 0.6 micron, x 2 1.8 microns, y2 0.7 micron, x 3 1.8 microns, y 3 0.7 micron, x 4 2.0 μm, y 4 It is 0.9 microns.

[0027] In step 11, the purpose of cooling after each layer of silicon dioxide is: on the one hand, the wafer boat is made of silicon carbide, and there is a difference in thermal expansion coefficient between silicon carbide and silicon materials. Cooling can take advantage of this characteristic to prevent the substrate from sticking to the wafer boat; on the other hand, after cooling, the wafer boat is controlled to rotate forward and backward, and N is introduced at the same time. 2 Creating an inert environment pauses the oxidation reaction, further preventing the substrate from sticking to the wafer boat.

[0028] In step 11, O 2 and H 2 As an oxidizing gas, O 2 and H 2 First react to generate H 2 O,H 2 O is thermally ionized into OH at high temperature. - and H + , OH - Compared to O 2- It exhibits more active chemical properties, which makes it more reactive when in contact with Si. On the one hand, it accelerates the oxidation rate of Si, and on the other hand, it allows more Si to participate in the oxidation reaction, allowing silicon dioxide to grow quickly to the target thickness.

[0029] It should be noted that in this embodiment, the isolation structure is filled with silicon dioxide through four thermal oxidations and the thickness of the isolation channel 11 is changed from the designed thickness d to 1 Expand to target thickness d 2 However, the number of thermal oxidations is not limited to four times. It mainly depends on the specific size of the isolation structure. In practical applications, it can be adjusted according to the size of the isolation structure.

[0030] Embodiment 2: Reference Figures 1 to 4 As shown, the present invention provides a method for manufacturing a semiconductor isolation structure, comprising the following steps: Step 1: Place the single crystal silicon substrate into the RCA wet cleaning equipment, clean it with SC3 solution at 120°C for 10 minutes, drain and rinse it, soak it in DHF solution at room temperature for 30 seconds, then rinse it with SC1 solution at 65°C for 10 minutes, and finally rinse it with SC2 solution at 65°C for 10 minutes to complete the cleaning; Step 2: Place the cleaned single crystal silicon substrate into an oxidation furnace, heat the oxidation furnace to 1000°C, and introduce O into the oxidation furnace at a flow rate of 8LSM.2 , so that SiO with a thickness of 3800A is grown on the front and back surfaces of the substrate 2 layer, serving as a mask layer 1 for subsequent etching; Step 3: Place the single crystal silicon substrate with the mask layer 1 into a coating and developing machine, apply a layer of front photoresist 2 on the front side thereof, and after exposure and development, place the substrate into a photolithography machine for front STI photolithography to open a number of shallow isolation etching windows 3; Step 4: Place a single crystal silicon substrate having a plurality of shallow isolation etching windows 3 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, open each shallow isolation etching window 3, then put it into the Si dry etching machine, through SF 6 With O 2 The combined gas performs Si dry etching on each shallow isolation etching window 3 to form a plurality of shallow isolation etching grooves 4; Step 5: Place the single crystal silicon substrate with several shallow isolation etching grooves 4 into a coating and developing machine, apply a layer of back photoresist 5 on the back side, and after exposure and development, place it into a photolithography machine for back trench lithography to open several deep isolation etching windows 6; Step 6: Place the single crystal silicon substrate with several deep isolation etching windows 6 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, open each deep isolation etching window 6, and then put it into the Si dry etching machine using Bosch technology, through SF 6 With O 2 The combined gas performs Si dry etching on each deep isolation etching window 6 to form a plurality of deep isolation etching grooves 7; Step 7: Place the single crystal silicon substrate having a plurality of shallow isolation etching grooves 4 and a plurality of deep isolation etching grooves 7 into an oxidation furnace, heat the oxidation furnace to 1000° C., and introduce O into the oxidation furnace at a flow rate of 8 LSM. 2 , so that SiO with a thickness of 1300 Å is grown on the surface of each shallow isolation etching groove 4 and each deep isolation etching groove 7 2 Layer, as a protective oxide layer 8 for subsequent wet etching; Step 8: Place the single crystal silicon substrate with protective oxide layer 8 into the SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2Dry etching, EtchBack (reverse etching) removes the protective oxide layer 8 at the bottom of each shallow isolation etching groove 4, opens a plurality of shallow isolation channel 11 etching windows 9, and in the reverse etching process, ions are bombarded vertically under the action of the electric field, so that the etching mainly acts on the protective oxide layer 8 in the vertical direction, and the protective oxide layer 8 on the side wall of the shallow isolation etching groove 4 is less bombarded by ions, so as to remove the protective oxide layer 8 at the bottom of the shallow isolation etching groove 4; Step 9: Turn over the single crystal silicon substrate with the etching windows 9 of the shallow isolation channels 11, remove the protective oxide layer 8 at the bottom of the deep isolation etching groove 7 by EtchBack, and open a plurality of etching windows 10 of the deep isolation channels 11; Step 10: Place the single crystal silicon substrate with a plurality of shallow isolation channels 11 etching windows 9 and a plurality of deep isolation channels 11 etching windows 10 into a wet Si etching machine, heat the wet Si etching machine to 90°C, and etch a designed thickness d on the substrate through 85% KOH solution. 1 The isolation channel 11 is connected to the plurality of shallow isolation etching grooves 4 and the plurality of deep isolation etching grooves 7 to form an isolation structure; Step 11: Place the single crystal silicon substrate with the isolation structure on a wafer carrier boat and place it in an oxidation furnace, with the side with the deep isolation etching grooves 7 facing upward, and heat the thermal oxidation equipment to a temperature T 1 , T 1 The temperature was 1210℃, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is formed inwardly with a thickness x 1 The silicon dioxide layer extends outward to a thickness of y 1 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1100℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 2 , T 2 The temperature was 1220℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 2 The silicon dioxide layer is added with a thickness of y 2 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1100℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 3 , T3 The temperature was 1230℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 3 The silicon dioxide layer is added with a thickness of y 3 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1100℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 4 , T 4 The temperature was 1240℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 4 The silicon dioxide layer is added with a thickness of y 4 The silicon dioxide layer is filled with silicon dioxide to fill the isolation structure and make the thickness of the isolation channel 11 by the designed thickness d 1 Expand to target thickness d 2 , forming Figure 1 and 2 The structure shown.

[0031] In this embodiment, the width of the shallow isolation etching window 3 is 5.0 microns, the depth of the shallow isolation etching groove 4 is 15 microns, the width of the deep isolation etching window 6 is 5.0 microns, and the isolation channel 11 is designed to have a thickness d 1 The target thickness is 6 microns. 2 The depth of the deep isolation etching groove 7 is 10 microns, and the depth of the deep isolation etching groove 7 is the thickness of the substrate minus the depth of the shallow isolation etching groove 4 and the designed thickness of the isolation channel 11. 1 1.5 microns, y 1 is 1 micron, x 2 1.5 microns, y 2 is 1 micron, x 3 1.5 microns, y 3 is 1 micron, x 4 1.5 microns, y 4 is 1 micron.

[0032] Embodiment 3: Reference Figures 1 to 4 As shown, the present invention provides a method for manufacturing a semiconductor isolation structure, comprising the following steps: Step 1: Place the single crystal silicon substrate into the RCA wet cleaning equipment, clean it with SC3 solution at 120°C for 10 minutes, drain and rinse it, soak it in DHF solution at room temperature for 30 seconds, then rinse it with SC1 solution at 65°C for 10 minutes, and finally rinse it with SC2 solution at 65°C for 10 minutes to complete the cleaning; Step 2: Place the cleaned single crystal silicon substrate into an oxidation furnace, heat the oxidation furnace to 1000°C, and introduce O into the oxidation furnace at a flow rate of 8LSM. 2 , so that SiO with a thickness of 4000A is grown on the front and back surfaces of the substrate 2 layer, serving as a mask layer 1 for subsequent etching; Step 3: Place the single crystal silicon substrate with the mask layer 1 into a coating and developing machine, apply a layer of front photoresist 2 on the front side thereof, and after exposure and development, place the substrate into a photolithography machine for front STI photolithography to open a number of shallow isolation etching windows 3; Step 4: Place a single crystal silicon substrate having a plurality of shallow isolation etching windows 3 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, opening each shallow isolation etching window 3, and then placing in a Si dry etcher, performing Si dry etching on each shallow isolation etching window 3 by a combination of SF6 and O2 gas, to form a plurality of shallow isolation etching grooves 4; Step 5: Place the single crystal silicon substrate with several shallow isolation etching grooves 4 into a coating and developing machine, apply a layer of back photoresist 5 on the back side, and after exposure and development, place it into a photolithography machine for back trench lithography to open several deep isolation etching windows 6; Step 6: Place the single crystal silicon substrate with several deep isolation etching windows 6 into a SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, open each deep isolation etching window 6, and then put it into the Si dry etching machine using Bosch technology, through SF 6 With O 2 The combined gas performs Si dry etching on each deep isolation etching window 6 to form a plurality of deep isolation etching grooves 7; Step 7: Place the single crystal silicon substrate having a plurality of shallow isolation etching grooves 4 and a plurality of deep isolation etching grooves 7 into an oxidation furnace, heat the oxidation furnace to 1000° C., and introduce O into the oxidation furnace at a flow rate of 8 LSM. 2 , so that SiO with a thickness of 1500 Å is grown on the surface of each shallow isolation etching groove 4 and each deep isolation etching groove 7 2 Layer, as a protective oxide layer 8 for subsequent wet etching; Step 8: Place the single crystal silicon substrate with protective oxide layer 8 into the SiO 2 Dry etcher, by CHF 3 With O 2 Combination of gases for SiO 2 Dry etching, EtchBack (reverse etching) removes the protective oxide layer 8 at the bottom of each shallow isolation etching groove 4, opens a plurality of shallow isolation channel 11 etching windows 9, and in the reverse etching process, ions are bombarded vertically under the action of the electric field, so that the etching mainly acts on the protective oxide layer 8 in the vertical direction, and the protective oxide layer 8 on the side wall of the shallow isolation etching groove 4 is less bombarded by ions, so as to remove the protective oxide layer 8 at the bottom of the shallow isolation etching groove 4; Step 9: Turn over the single crystal silicon substrate with the etching windows 9 of the shallow isolation channels 11, remove the protective oxide layer 8 at the bottom of the deep isolation etching groove 7 by EtchBack, and open a plurality of etching windows 10 of the deep isolation channels 11; Step 10: Place the single crystal silicon substrate with a plurality of shallow isolation channels 11 etching windows 9 and a plurality of deep isolation channels 11 etching windows 10 into a wet Si etching machine, heat the wet Si etching machine to 90°C, and etch a designed thickness d on the substrate through 85% KOH solution. 1 The isolation channel 11 is connected to the plurality of shallow isolation etching grooves 4 and the plurality of deep isolation etching grooves 7 to form an isolation structure; Step 11: Place the single crystal silicon substrate with the isolation structure on a wafer carrier boat and place it in an oxidation furnace, with the side with the deep isolation etching grooves 7 facing upward, and heat the thermal oxidation equipment to a temperature T 1 , T 1 The temperature was 1200℃, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is formed inwardly with a thickness x 1 The silicon dioxide layer extends outward to a thickness of y 1 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1050℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 2 , T 2 The temperature was 1215℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 2 The silicon dioxide layer is added with a thickness of y 2 The silicon dioxide layer is then introduced into N 2, cool the thermal oxidation device to 1050℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 3 , T 3 The temperature was 1230℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 3 The silicon dioxide layer is added with a thickness of y 3 The silicon dioxide layer is then introduced into N 2 , cool the thermal oxidation device to 1050℃, the cooling rate is <0.15℃ / Min, control the wafer boat to rotate clockwise for 3 times @2 turns / Min, and the wafer boat to rotate counterclockwise for 3 times @2 turns / Min, then heat the thermal oxidation device to temperature T 4 , T 4 The temperature was 1245℃, the heating rate was <0.2℃ / Min, and O was introduced at a flow rate of 7SLM. 2 and H 2 , so that the isolation channel 11 is increased inwardly by a thickness x 4 The silicon dioxide layer is added with a thickness of y 4 The silicon dioxide layer is filled with silicon dioxide to fill the isolation structure and make the thickness of the isolation channel 11 by the designed thickness d 1 Expand to target thickness d 2 , forming Figure 1 and 2 The structure shown.

[0033] In this embodiment, the width of the shallow isolation etching window 3 is 3.6 microns, the depth of the shallow isolation etching groove 4 is 15 microns, the width of the deep isolation etching window 6 is 3.6 microns, and the isolation channel 11 is designed to have a thickness d 1 The target thickness is 6 microns. 2 The depth of the deep isolation etching groove 7 is 10 microns, and the depth of the deep isolation etching groove 7 is the thickness of the substrate minus the depth of the shallow isolation etching groove 4 and the designed thickness of the isolation channel 11. 1 1.0 μm, y 1 0.4 μm, x 2 0.8 μm, y 2 0.65 μm, x 3 0.8 μm, y 3 0.65 μm, x 4 1.0 μm, y 4 It is 0.7 microns.

[0034] Comparative Example 1: This comparative example provides a method for manufacturing a semiconductor isolation structure, which differs from Example 1 in that: in step 11, T 1 1050℃, T 2 1200℃, T 3 1230℃, T 4 The temperature is 1260℃, the heating rate is 0.3℃ / Min, and after each layer of silicon dioxide is grown, the temperature is lowered to 900℃, and the cooling rate is 0.3℃ / Min. Its isolation structure is deformed.

[0035] Comparative Example 2: This comparative example provides a method for manufacturing a semiconductor isolation structure, which is different from Example 1 in that the width of the shallow isolation etching window 3 is 3.0 microns, and the width of the deep isolation etching window 6 is 3.0 microns. In step 11, the deep isolation etching groove 7 and the shallow isolation etching groove 4 are closed in advance, and the silicon dioxide filling in the isolation channel 11 is incomplete.

[0036] Comparative Example 3: This comparative example provides a method for manufacturing a semiconductor isolation structure, which is different from Example 1 in that the width of the shallow isolation etching window 3 is 6.5 microns, and the width of the deep isolation etching window 6 is 6.5 microns. In step 11, the isolation channel 11 is closed before the shallow isolation etching groove 4 and the deep isolation etching groove 7 are closed. After the shallow isolation etching groove 4 and the deep isolation etching groove 7 are closed, the isolation structure is slightly deformed.

[0037] Comparative Example 4: In this comparative example, a bonding SOI chip with a thickness of 10 microns is selected as the substrate, and an STI structure is provided. The size design is the same as that of Example 1.

[0038] The isolation structures obtained in Comparative Example 4 and Example 1 were subjected to electrical tests, and the dielectric strength and leakage current at 90% breakdown of the two structures were tested. Figure 5 As shown, the test method is: select two adjacent devices on the same substrate to form a test unit, device A18 and device B19 are a test unit and connected to a test circuit containing an external resistor, a current loop 22 is formed between device A and device B, and an electric field concentration area 20 is formed between the two. At 10A, 50A, 100A and 200A, 50 test units are randomly selected to test the voltage at breakdown, calculate the 90% breakdown value, adjust to the voltage, stabilize for 10 minutes and measure the leakage current detection data. The test results are shown in Tables 1 to 8: Table 1 Test results of Example 1 at 10A Table 2 Test results of Example 1 at 50A Table 3 Test results of Example 1 at 100A Table 4 Test results of Example 1 at 500A Table 5 Test results of comparative example 4 at 10A Table 6 Test results of comparative example 4 at 50A Table 7 Test results of comparative example 4 at 100A Table 8 Test results of comparative example 4 at 200A From the table we can see that: Under the test current of 10A, the breakdown voltage of comparative example 4 is about 51% of the breakdown voltage of embodiment 1, and the leakage at 90% breakdown voltage is about 10 times that of embodiment 1; under the test current of 50A, the breakdown voltage of comparative example 4 is less than 50% of that of embodiment 1, and the leakage at 90% breakdown voltage is about 50 times that of embodiment 1; under the test current of 100A, the breakdown voltage of comparative example 4 is less than 45% of that of embodiment 1, and the leakage at 90% breakdown voltage is about 110 times that of embodiment 1; under the test current of 200A, the breakdown voltage of comparative example 4 is about 40% of that of embodiment 1, and the leakage at 90% breakdown voltage is about 180 times that of embodiment 1, which is close to 10uA. It can be seen that the electrical isolation capability of embodiment 1 is better than that of comparative example 4, indicating that the isolation structure made by the present invention has excellent electrical isolation capability and can better meet the needs of high working voltage and large working current products.

[0039] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0040] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor isolation structure, characterized in that: The following steps are involved: (1) using the STI process to open a plurality of shallow isolation etching grooves on one side of the single crystal silicon substrate; using the Trench process to open a plurality of deep isolation etching grooves on the other side of the single crystal silicon substrate; (2) using a wet etching process to etch an isolation channel with a designed thickness of d1 on a single crystal silicon substrate having a plurality of shallow isolation etching grooves and a plurality of deep isolation etching grooves, so that the isolation channel, the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves are interconnected to form an isolation structure; (3) placing the single crystal silicon substrate with the isolation structure into a thermal oxidation device, with the side with the plurality of deep isolation etching grooves facing upward, and using a thermal oxidation process to fill the isolation structure with silicon dioxide and expand the thickness of the isolation channel from the designed thickness d1 to the target thickness d2, wherein the thermal oxidation process includes: The thermal oxidation device is heated to a temperature T1 so that the isolation channel forms a silicon dioxide layer with a thickness of x1 inwardly and expands a silicon dioxide layer with a thickness of y1 outwardly; After cooling the thermal oxidation device to 1000-1100° C., heating it up to temperature T2, where T2>T1, so as to add a silicon dioxide layer with a thickness of x2 inside and a silicon dioxide layer with a thickness of y2 outside; Wherein, d1 is the total thickness of the silicon dioxide layer formed inwardly from the isolation channel.

2. The method for manufacturing a semiconductor isolation structure according to claim 1, characterized in that: In step (3), d2=1.4~1.8d1.

3. The method for manufacturing a semiconductor isolation structure according to claim 1, characterized in that: In step (3), y1 is 0.4 to 0.8x1, and y2 is 0.4 to 0.8x2.

4. The method for manufacturing a semiconductor isolation structure according to claim 1, characterized in that: In step (3), x2 is 0.8 to 1.2x1.

5. The method for manufacturing a semiconductor isolation structure according to claim 1, characterized in that: In step (3), T1≥1200°C, and T2 is 10-20°C higher than T1.

6. The method for manufacturing a semiconductor isolation structure according to claim 5, characterized in that: In step (3), the heating rate is <0.2°C / Min.

7. The method for manufacturing a semiconductor isolation structure according to claim 1, characterized in that: In step (3), the cooling rate is <0.15°C / Min.

8. A method for manufacturing a semiconductor isolation structure according to any one of claims 1 to 7, characterized in that: In step (3), the thermal oxidation process further comprises: After cooling to 1000-1100°C, the thermal oxidation device is heated to a temperature T3, T3>T2, so as to add a silicon dioxide layer with a thickness of x3 inwardly, x3 being 0.8-1.2x1, and to add a silicon dioxide layer with a thickness of y3 outwardly, y3 being 0.4-0.8x3; After cooling to 1000-1100°C, the thermal oxidation equipment is heated to temperature T4, T4>T3, so as to add a silicon dioxide layer with a thickness of x4 inwardly, x4 is 0.8-1.2x1, and to add a silicon dioxide layer with a thickness of y4 outwardly, y4 is 0.4-0.8x4.

9. The method for manufacturing a semiconductor isolation structure according to claim 8, characterized in that: In step (3), T4≤1260°C.

10. The method for manufacturing a semiconductor isolation structure according to any one of claims 1 to 7, characterized in that: In step (2), the thickness of the shallow isolation etching groove is d3, and the thickness of the deep isolation etching groove is d4, d3=0.6~0.8d1, and d4=0.6~0.8d1.

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