FBAR cavity structure optimization method and FBAR cavity structure
By using silicon nitride cutoff layer and wet corrosion technology in the FBAR cavity structure, the cavity structure is optimized, the problem of excessive Dishing depth is solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202510056154.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-06-06
AI Technical Summary
After the sacrificial layer is filled, the existing FBAR cavity structure is easily flattened by chemical mechanical polishing process, which can easily form a large depressed depth (Dishing) defect, affecting the stress, adhesion and crystal direction of the subsequent deposited layer, thereby reducing device performance and reliability.
A silicon nitride film is used as the silicon nitride cutoff layer, and the cavity of a preset depth is deposited and etched, the sacrificial layer is filled and planarized, and the silicon nitride cutoff layer is then removed by wet corrosion to optimize the FBAR cavity structure.
It effectively reduces the Dishing depth, improves the adhesion and crystalline consistency of the subsequent deposition layer, and improves the performance and reliability of the FBAR device.
Smart Images
Figure CN120110348A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an FBAR cavity structure optimization method and an FBAR cavity structure. Background Art
[0002] Film Bulk Acoustic Resonator (FBAR) is a device based on the theory of bulk acoustic waves, which uses acoustic resonance to achieve electrical frequency selection. Its principle is to select the frequency through the resonance of the piezoelectric material between the upper and lower thin-layer electrodes in the vertical direction, and then form a filter structure through the combination of multiple resonators. Compared with traditional LC filters, surface acoustic wave filters and dielectric filters, it has the advantages of high frequency (0.5-10GHz), small size, low power consumption, good rectangularity, low insertion loss, etc. At the same time, its manufacturing process is compatible with complementary metal oxide semiconductor (CMOS) technology, and it has been widely used in the field of mobile communications.
[0003] There are three mainstream FBAR structures at present: back-etched, cavity and solid-state assembly. The back-etched structure greatly reduces the reliability of the device due to the large amount of substrate removed from the back. The solid-state assembly requires the preparation of multi-layer thin films, and has high requirements for film thickness and uniformity. The process is cumbersome and complex, and the cost is high. Therefore, from the perspective of cost and process, the cavity FBAR structure has been generally recognized by the industry. It is the most widely used and commercially successful structure in the market, and will become the best choice for RF filters in the future.
[0004] The cavity structure FBAR forms a sandwich structure of Mo bottom electrode-AlN / ScAlN piezoelectric layer-Mo top electrode on a silicon wafer with a cavity through semiconductor processes such as dry etching and thin film deposition. The processes involved are: 1) silicon cavity production; 2) sacrificial layer filling; 3) sacrificial layer flattening; 4) sputtering Mo bottom electrode-AlN / ScAlN piezoelectric layer-Mo top electrode sandwich structure and subsequent processes; 5) sacrificial layer release to form a cavity. The first three steps are the key to making the FBAR cavity structure, and the surface flatness control determines the performance of the subsequent device. After the sacrificial layer is filled, the sacrificial layer needs to be thinned to expose the wafer surface through the chemical-mechanical polishing (CMP) process, and the entire wafer surface is flattened at the same time. During the flattening process, since the removal rate of the sacrificial layer material inside the cavity by the grinding fluid is generally faster than that of silicon, a large depression depth is often formed at the edge of the silicon cavity, also known as a butterfly defect. After CMP is completed, the height difference of the silicon cavity step and the surface roughness of the sacrificial layer inside the silicon cavity need to be inspected. Too deep Dishing and too large surface roughness of the sacrificial layer will affect the stress, adhesion and crystal orientation of the subsequently deposited bottom electrode and piezoelectric layer and other thin films, thereby affecting the performance and reliability of the device. Excessive surface roughness of the sacrificial layer can be solved by using a polishing liquid with a small particle size, but it cannot be effectively solved if Dishing is too large.
[0005] Therefore, it is urgent to provide a technical solution to solve the above problems. Summary of the invention
[0006] In order to solve the above technical problems, the present invention provides a FBAR cavity structure optimization method and a FBAR cavity structure.
[0007] In a first aspect, the present invention provides a method for optimizing a FBAR cavity structure, and the technical solution of the method is as follows:
[0008] Depositing a silicon nitride film as a silicon nitride cutoff layer onto an original substrate to obtain a target substrate, and etching a target cavity of a preset depth on the target substrate to obtain a first cavity structure;
[0009] Depositing a sacrificial layer material of a target thickness and completely filling the first cavity structure to obtain a second cavity structure, and performing a planarization and rough polishing process on the sacrificial layer material on the second cavity structure by using a chemical mechanical polishing process until the wafer is completely exposed from the silicon nitride cut-off layer of the second cavity structure to obtain a third cavity structure;
[0010] The remaining silicon nitride stop layer on the third cavity structure is removed by a wet etching method to obtain a fourth cavity structure and then the wafer is cleaned to obtain an optimized FBAR cavity structure.
[0011] The beneficial effects of the FBAR cavity structure optimization method of the present invention are as follows:
[0012] The method of the present invention can effectively solve the problem of excessive Dishing depth of the FBAR cavity structure, obtain a cavity structure with a smaller Dishing depth, ensure the problems caused by stress, adhesion and crystal orientation of thin films such as the bottom electrode and piezoelectric layer subsequently deposited on the FBAR device, and improve the performance and reliability of the device.
[0013] Based on the above solution, the FBAR cavity structure optimization method of the present invention can also be improved as follows.
[0014] In an optional manner, before the wafer cleaning is performed, the method further includes:
[0015] The sacrificial layer material on the fourth cavity structure is planarized and polished by chemical mechanical polishing process.
[0016] In an optional manner, the original substrate is: a silicon wafer, a silicon carbide substrate or a composite substrate.
[0017] In an optional manner, the deposition thickness of the silicon nitride stop layer is 100nm-500nm.
[0018] In an optional manner, the preset depth is 1 μm-10 μm.
[0019] In an optional manner, the sacrificial layer material is silicon oxide, phosphosilicate glass or polysilicon, and the target thickness is 1.5 μm-10.5 μm.
[0020] In an optional manner, the butterfly defect depth of the third cavity structure is 100nm-300nm.
[0021] In an optional manner, the wet etching method is: etching with a hot phosphoric acid solution, and the etching condition of the hot phosphoric acid solution is 80°C-200°C.
[0022] In an optional manner, the particle size of the polishing liquid used in the planarization fine polishing process is not greater than 150 nm.
[0023] In a second aspect, the present invention provides a FBAR cavity structure, which is manufactured by the FBAR cavity structure optimization method of the present invention.
[0024] In a third aspect, the present invention provides a thin film bulk acoustic wave filter, which adopts the FBAR cavity structure of the present invention.
[0025] In a fourth aspect, the present invention provides a thin film bulk acoustic wave resonator, wherein the thin film bulk acoustic wave resonator adopts the FBAR cavity structure of the present invention.
[0026] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:
[0028] Figure 1 It is a schematic flow chart of a first embodiment of a method for optimizing a FBAR cavity structure of the present invention;
[0029] Figure 2 It is a schematic flow chart of a second embodiment of a method for optimizing a FBAR cavity structure of the present invention;
[0030] Figure 3 This is a schematic diagram of a Dishing defect;
[0031] Figure 4 Schematic diagram of the process flow for optimizing the FBAR cavity structure;
[0032] Figure 5 This is a comparison chart of the butterfly defect depth step meter data before and after optimization. DETAILED DESCRIPTION
[0033] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.
[0034] Figure 1 FIG. 2 is a flow chart of a first embodiment of a method for optimizing a FBAR cavity structure provided by the present invention. Figure 1 As shown, the following steps are included:
[0035] S1. Using a silicon nitride film as a silicon nitride cut-off layer and depositing it on an original substrate to obtain a target substrate, and etching a target cavity of a preset depth on the target substrate to obtain a first cavity structure.
[0036] The original substrate is a silicon wafer, a silicon carbide substrate or a composite substrate, and the composite substrate is a composite of a silicon wafer and a silicon carbide substrate. The deposition thickness of the silicon nitride cutoff layer (silicon nitride film) is 100nm-500nm. The preset depth is 1μm-10μm, and the number of target cavities is multiple.
[0037] S2. Deposit a sacrificial layer material of target thickness and completely fill the first cavity structure to obtain a second cavity structure, and use a chemical mechanical polishing process to planarize and rough-polish the sacrificial layer material on the second cavity structure until the wafer is completely exposed from the silicon nitride cutoff layer of the second cavity structure to obtain a third cavity structure.
[0038] The sacrificial layer material is silicon oxide, phosphosilicate glass or polysilicon, and the phosphorus content of phosphosilicate glass is 2%-8%. The target thickness is higher than the preset depth, and the target thickness is 1.5μm-10.5μm. The sacrificial layer material is prepared by chemical vapor deposition, magnetron sputtering deposition or plasma enhanced chemical vapor deposition, and the obtained sacrificial layer material film thickness uniformity is less than ±5%. The butterfly defect depth of the third cavity structure is 100nm-300nm.
[0039] S3. Using a wet etching method, remove the remaining silicon nitride stop layer on the third cavity structure to obtain a fourth cavity structure and perform wafer cleaning to obtain an optimized FBAR cavity structure.
[0040] The wet etching method is: using hot phosphoric acid solution for etching, and the etching conditions of the hot phosphoric acid solution are: 80°C-200°C.
[0041] Optionally, before wafer cleaning, the method further includes:
[0042] The sacrificial layer material on the fourth cavity structure is planarized and polished by chemical mechanical polishing process.
[0043] The particle size of the polishing liquid used in the planarization fine polishing process is not greater than 150 nm.
[0044] It should be noted that the technical solution of this embodiment is to optimize the first three steps of manufacturing the FBAR cavity structure. After the wafer is cleaned, the process of optimizing the FBAR cavity structure also includes: sputtering the sandwich structure of Mo bottom electrode-AlN / ScAlN piezoelectric layer-Mo top electrode and subsequent processes, as well as the release of the sacrificial layer to form a cavity and other operating steps, and finally the optimized FBAR cavity structure is obtained.
[0045] The technical solution of this embodiment can effectively solve the problem of excessive Dishing depth of the FBAR cavity structure, obtain a cavity structure with a smaller Dishing depth, and ensure the problems caused by stress, adhesion and crystal orientation of thin films such as the bottom electrode and piezoelectric layer subsequently deposited in the FBAR device, thereby improving the performance and reliability of the device.
[0046] Figure 2 FIG. 2 is a flow chart of a second embodiment of a method for optimizing a FBAR cavity structure provided by the present invention. Figure 2 As shown, the following steps are included:
[0047] S10, using a silicon nitride film as a silicon nitride stop layer and depositing it on an original substrate to obtain a target substrate, and etching a target cavity of a preset depth on the target substrate to obtain a first cavity structure.
[0048] The original substrate is a silicon wafer, and the deposition thickness of the silicon nitride stop layer (silicon nitride film) is 200 nm. The preset depth is 3 μm.
[0049] S20, depositing a sacrificial layer material of a target thickness and completely filling the first cavity structure to obtain a second cavity structure, and using a chemical mechanical polishing process to planarize and rough-polish the sacrificial layer material on the second cavity structure until the wafer is completely exposed from the silicon nitride cutoff layer of the second cavity structure to obtain a third cavity structure.
[0050] The sacrificial layer material is phosphosilicate glass (PSG), with a phosphorus content of 5%. Figure 3 As shown, the sacrificial layer material on the second cavity structure is planarized and rough polished by chemical mechanical polishing (CMP) until the wafer is completely exposed from the silicon nitride cut-off layer of the second cavity structure, and at this time, the depth of the butterfly defect is controlled at 200nm±10nm.
[0051] S30, using a wet etching method to remove the remaining silicon nitride stop layer on the third cavity structure to obtain a fourth cavity structure, and using a chemical mechanical polishing process to perform a planarization and fine polishing process on the sacrificial layer material on the fourth cavity structure to obtain a fifth cavity structure.
[0052] The remaining silicon nitride stop layer on the third cavity structure is removed by phosphoric acid wet etching in a water bath heated to 95°C.
[0053] S40, performing wafer cleaning on the fifth cavity structure, sputtering a sandwich structure of Mo bottom electrode-AlN / ScAlN piezoelectric layer-Mo top electrode and subsequent processes, and releasing the sacrificial layer to form a cavity, thereby obtaining an optimized FBAR cavity structure.
[0054] It should be noted that Figure 4 The flowchart of the FBAR cavity structure optimization process of this embodiment is shown. Figure 5 The following figure shows the comparison of the butterfly defect depth profiler data before and after optimization. Figure 5 (a) is the depth profiler data of the butterfly defect before optimization. Figure 5 (b) is the optimized butterfly (Dishing) defect depth step meter data. The Dishing depth of the silicon cavity edge is reduced from 30 to 45nm to less than 5nm by the method of this embodiment, and the in-plane uniformity is improved from 12.3% to 3.8%. The polishing liquid with a particle size of 35 to 45nm is used for polishing. After flattening, the surface roughness of the sacrificial layer on the surface of the cavity structure is 0.17nm. Therefore, according to the method of this embodiment, the uniformity of the Dishing depth of the silicon cavity edge can be improved, and the Dishing depth of the silicon cavity edge is less than 5nm, so that a smooth and uniform PSG surface is obtained, and the step height difference of the FBAR silicon cavity edge is low.
[0055] The technical solution of this embodiment can effectively solve the problem of excessive Dishing depth of the FBAR cavity structure, obtain a cavity structure with a smaller Dishing depth, and ensure the problems caused by stress, adhesion and crystal orientation of thin films such as the bottom electrode and piezoelectric layer subsequently deposited in the FBAR device, thereby improving the performance and reliability of the device.
[0056] An embodiment of the present invention provides a FBAR cavity structure, which is manufactured using the technical solution of the embodiment of the FBAR cavity structure optimization method provided by the present invention. For details, reference may be made to the steps and parameters in the embodiment of the FBAR cavity structure optimization method described above, which will not be described in detail here.
[0057] An embodiment of the present invention provides a thin film bulk acoustic wave filter, which adopts the FBAR cavity structure provided by the present invention.
[0058] In addition, the present invention also provides a thin film bulk acoustic wave resonator, which adopts the FBAR cavity structure provided by the present invention.
[0059] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. Similarly, in order to simplify the present invention and help understand one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Wherein, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself is a separate embodiment of the present invention.
[0060] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be understood as limitations on the order of execution.
Claims
1. A method for optimizing a FBAR cavity structure, characterized in that: include: Depositing a silicon nitride film as a silicon nitride cutoff layer onto an original substrate to obtain a target substrate, and etching a target cavity of a preset depth on the target substrate to obtain a first cavity structure; Depositing a sacrificial layer material of a target thickness and completely filling the first cavity structure to obtain a second cavity structure, and performing a planarization and rough polishing process on the sacrificial layer material on the second cavity structure by using a chemical mechanical polishing process until the wafer is completely exposed from the silicon nitride cut-off layer of the second cavity structure to obtain a third cavity structure; The remaining silicon nitride stop layer on the third cavity structure is removed by a wet etching method to obtain a fourth cavity structure and then the wafer is cleaned to obtain an optimized FBAR cavity structure.
2. The FBAR cavity structure optimization method according to claim 1, characterized in that: Before wafer cleaning, it also includes: The sacrificial layer material on the fourth cavity structure is planarized and polished by chemical mechanical polishing process.
3. The FBAR cavity structure optimization method according to claim 1, characterized in that: The original substrate is: a silicon wafer, a silicon carbide substrate or a composite substrate.
4. The FBAR cavity structure optimization method according to claim 1, characterized in that: The deposition thickness of the silicon nitride stop layer is 100nm-500nm.
5. The FBAR cavity structure optimization method according to claim 1, characterized in that: The preset depth is 1 μm-10 μm.
6. The FBAR cavity structure optimization method according to claim 1, characterized in that: The sacrificial layer material is: silicon oxide, phosphosilicate glass or polysilicon, and the target thickness is: 1.5μm-10.5μm.
7. The FBAR cavity structure optimization method according to claim 1, characterized in that: The butterfly defect depth of the third cavity structure is 100nm-300nm.
8. The FBAR cavity structure optimization method according to claim 1, characterized in that: The wet etching method is: using hot phosphoric acid solution for etching, and the etching condition of the hot phosphoric acid solution is 80° C.-200° C.
9. The FBAR cavity structure optimization method according to claim 2, characterized in that: The particle size of the polishing liquid used in the flattening fine polishing process is not greater than 150 nm.
10. A FBAR cavity structure, characterized in that: The FBAR cavity structure is manufactured by the FBAR cavity structure optimization method as described in any one of claims 1 to 9.