Switch, switch management method, equipment and medium

Abstract

The invention discloses a switch, a switch management method, equipment and a medium, and relates to the technical field of computers, the switch comprises a processor, a master / slave controller and peripheral equipment, the processor reads equipment information of the peripheral equipment of the switch through a first bus, and provides a high-speed access interface for the master / slave controller through a second bus; the equipment information of the peripheral equipment is managed through the independent hardware module, and the access channels are provided for the master controller and the slave controller at the same time, so that the technical problem of low access efficiency of the controllers can be solved, and the internal stability of the switch is improved. And the technical effect of sharing the equipment information of the peripheral equipment between the master controller and the slave controller in real time is realized.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to switches, switch management methods, devices and media. Background Art

[0002] There are differences in the management plane division of labor modes of current switches. Controllers such as CPU and BMC can be used as management controllers, resulting in inconsistent switch hardware solutions. In addition, as the number of peripherals such as optical modules increases, the speed at which the controller reads peripheral information decreases, resulting in a long response time.

[0003] Therefore, there is an urgent need for a switch and a switch management method that can improve controller access efficiency to solve the above technical problems. Summary of the invention

[0004] The present application provides a switch, a switch management method, a device and a medium to at least solve the problem of low controller access efficiency in the related art.

[0005] The present application provides a switch, including:

[0006] Processor, master controller, slave controller, multiple peripheral devices;

[0007] The processor is connected to a plurality of peripheral devices via a first bus, so that the processor reads device information in the peripheral devices via the first bus;

[0008] The processor is connected to the master controller and the slave controller respectively through the second bus, so that the master controller and the slave controller read the device information cached in the processor through the second bus.

[0009] The present application also provides a switch management method, including:

[0010] Generate first device information according to the read device information of the peripheral device and a preset management information format;

[0011] synchronizing the first device information to generate the second device information;

[0012] storing the first device information in a first cache, and storing the second device information in a second cache;

[0013] In response to a received data transfer request sent by the master controller or the slave controller, first device information or second device information matching the data transfer request is retrieved and fed back to the master controller or the slave controller.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above switch management methods when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above switch management methods are implemented.

[0016] The switch disclosed in the present application includes a processor, a master / slave controller and a peripheral device. The processor is connected to the peripheral device and the master / slave controller, so that the processor can directly read the device information of the switch peripheral device through a first bus, and provide a high-speed access interface to the master and slave controllers through a second bus. That is, the present application manages the device information of the peripheral device through an independent hardware module, and provides access channels to the master controller and the slave controller at the same time. Therefore, the technical problem of low controller access efficiency can be solved, the internal stability of the switch is improved, and the technical effect of achieving real-time sharing of the device information of the peripheral device between the master controller and the slave controller is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A switch hardware architecture diagram provided in an embodiment of the present application;

[0019] Figure 2 A diagram of another switch hardware architecture provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a main controller configuration provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a master-slave controller switching provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of a switch software architecture provided in an embodiment of the present application;

[0023] Figure 6 An interactive diagram of a switch management method provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a management information format provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0028] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0029] As mentioned in the background technology, current switches have differences in the division of labor mode of the management plane, and the traditional method of obtaining peripheral device information for compatibility with different types of controllers is mainly to reserve hardware channels for peripheral devices for both the master and slave controllers, but this solution has problems such as complex hardware wiring, poor access real-time performance, low efficiency, and difficulty in switching access paths. Therefore, this application provides a new type of switch and switch management method to solve the above problems.

[0030] The embodiment of the present application provides a switch, such as Figure 1 As shown, its hardware structure includes: a processor, a main controller, a slave controller, and multiple peripheral devices; the processor is connected to the multiple peripheral devices through a first bus to enable the processor to read device information in the peripheral devices through the first bus; the processor is connected to the main controller and the slave controller respectively through a second bus to enable the main controller and the slave controller to read the device information cached in the processor through the second bus.

[0031] Specifically, the above processor is preferably set to FPGA (Field Programmable Gate Array); of course, it can also be set to CPLD (Complex Programming logic device); in some scenarios where the response efficiency is not required, MCU (Microcontroller Unit, MCU) can also be used. This application does not limit the specific processor type.

[0032] The above-mentioned master controller can be a CPU or a BMC, and the above-mentioned slave controller can also be a CPU or a BMC. It can be understood that among switch customers, there are differences in the management plane division of labor mode. Some customers use the CPU for management, and some customers use the BMC for management, that is, the type of controller used for management in the switch can be a CPU or a BMC; in the embodiments disclosed in the present application, the master controller and the slave controller can both be set to the CPU, or both be set to the BMC, or the master controller can be set to the CPU and the slave controller can be set to the BMC, or the master controller can be set to the BMC and the slave controller can be set to the CPU. In the switch disclosed in the embodiments of the present application, any of the above-mentioned master-slave controller type settings can operate normally.

[0033] The above-mentioned peripheral devices include but are not limited to peripheral devices such as fans, power supplies, indicator lights and optical modules of the switch; the processor reads device information of peripheral devices such as fans, power supplies, indicator lights and optical modules of the switch through the physical channel provided by the first bus; the above-mentioned first bus can be I2C (Inter-Integrated Circuit, low-speed management bus), or it can be SMBus (System Management Bus) and PMBus (Power Management Bus) and other serial bus, this application does not limit this, and technical personnel in this field will select it according to the market scenario.

[0034] After the processor reads the device information of the peripheral device through the first bus, it caches the acquired device information of the peripheral device, and then feeds back the cached device information to the master controller and the slave controller through the second bus; that is, in the embodiment of the present application, the master and slave controllers read the device information of the peripheral device cached in the processor through the physical channel provided by the second bus. The second bus is preferably set to PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus), and of course it can also be set to a USB bus (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) bus, etc., which can provide a high-speed access interface; the present application does not limit the specific type of the second bus, and it is selected by those skilled in the art according to the actual scenario.

[0035] The embodiment of the present application is based on the above-disclosed hardware architecture. The processor directly reads the device information of the switch peripheral devices through the first bus, and provides a high-speed access interface to the master-slave controller through the second bus, thereby realizing the master-slave controller's access to the device information of the peripheral devices; that is, the device information of the peripheral devices is managed through an independent hardware module (i.e., the processor), thereby improving the internal stability of the switch; and providing access channels to the master controller and the slave controller at the same time, thereby realizing real-time sharing of the device information of the peripheral devices between the master controller and the slave controller.

[0036] In some implementation scenarios, such as Figure 2 As shown in the hardware architecture diagram, the master controller is interconnected with the slave controller through a general input and output interface to realize the transmission of heartbeat signals between the master controller and the slave controller.

[0037] It is understandable that since there is only one set of peripheral hardware, all switches can only be controlled by one controller at the same time, so it involves the setting of the master controller and the slave controller, that is, which controller is selected as the master controller. By default, user configuration selection is supported. The specific configuration process is as follows Figure 3 As shown in the configuration flow diagram, when the switch system starts, it reads the user configuration and selects the main controller according to the user configuration. After the main controller is selected, the subsequent configuration of the switch system is implemented by the main controller by default, and the slave controller has no authority to issue configuration instructions until there is a new configuration or the main controller is detected to have an abnormal operation. That is, when the switch system issues control to the peripherals, it supports manual configuration of the type of the main controller.

[0038] The master controller and the slave controller use the universal input and output interface as a physical communication channel to transmit heartbeat information. Figure 4 The master controller abnormality detection and controller switching process shown is that after the switch system is started, the master controller sends heartbeat information to the slave controller through the general input and output interface; the slave controller detects whether the received heartbeat information has timed out; if it has not timed out, it is determined that the master controller is working normally, and the slave controller does not need to take over at this time; if it times out, it is determined that the master controller is working abnormally, and the slave controller is enabled to take over at this time, that is, the slave controller is enabled to send configuration. That is, when the master controller sends heartbeat information abnormally, the slave controller will take over the control and send authority, and provide information acquisition and sending. The switch disclosed in the embodiment of the present application supports a heartbeat detection arbitration mechanism, which further ensures that when the master controller is abnormal, the slave controller can send configuration to the peripheral device and obtain peripheral information, thereby improving the fault tolerance of the entire switch system.

[0039] In some implementation scenarios, the processor also includes a data handling module for carrying the device information cached in the processor to the main controller and the slave controller. The above-mentioned data handling module is preferably set to DMA (Direct Memory Access, direct memory access). DMA, as a device for automatic data handling, can realize sending data directly from an attached device to the computer's memory. In the embodiment of the present application, in order to improve data transmission efficiency and throughput, the processor uses DMA to directly carry the cached device data to the main controller and the slave controller without the need for controller intervention, which greatly saves controller resources and further reduces the controller load. Among them, the process of DMA carrying data mainly includes: driving to allocate physical memory space, driving to initialize DMA module, driving to issue DMA descriptors, driving to start DMA engine and DMA engine to start carrying data. The DMA working engine will move data according to the DMA descriptor linked list, and the DMA descriptor generally includes the original address of the data to be carried, the destination address of the data to be carried, the size of the data to be carried, and the position of the next DMA descriptor.

[0040] The present application also provides a switch management method, which is applied to the switch disclosed in the above embodiment 1. Figure 5 As shown in the disclosed software block diagram, the switch includes a processor, a master controller, a slave controller and peripheral devices, and a driver and a first cache and a second cache are deployed in the processor. Of course, those skilled in the art can also make adaptive changes to the switch management method to apply it to the scenario of peripheral device management in the server.

[0041] In this embodiment, the processor is used as the main body to execute the above switch management method, specifically, Figure 6 As shown, the method includes:

[0042] Generate the first device information according to the read device information of the peripheral device and the preset management information format; synchronize the first device information to generate the second device information; store the first device information in the first cache, and store the second device information in the second cache; in response to the received data transfer request issued by the master controller or the slave controller, retrieve the first device information or the second device information that matches the data transfer request and feed it back to the master controller or the slave controller. It can be understood that after the first device information or the second device information is fed back to the corresponding master controller or the slave controller, it is parsed by the corresponding master controller or the slave controller according to the preset management information format, and then the parsed data is given to the application in the controller. This application uses a processor to read and process the peripheral device, and performs dual storage cache, so that the master controller and the slave controller can read the device information stored independently, and realize that the master controller and the slave controller obtain the device information of the peripheral device independently and do not interfere with each other from the physical hardware to the driver layer to the application.

[0043] The preset management information format is designed when programming the driver in the processor, for example, Figure 7 As shown, the embodiment of the present application discloses a management information format, which is involved according to the custom communication protocol provided by the processor, removing the details of optical module management and serial interface communication. Only the parsing format and parsing scheme need to be considered during design, and the maintenance workload is reduced through reasonable hierarchical division. The above management information format is mainly divided into two main fields; one is the HEADER field (header field), which is used to indicate the type and length of this information; the other is the DATA field (data field), which is mainly used to store actual data:

[0044] MESSAGE TYPE: refers to the type of this message, which is currently divided into WRITE, READ, and ILLEGAL. ILLEGAL is mainly used to indicate that the read data is unusable when reading data. The application layer needs to filter it and do not continue to parse its specific data content.

[0045] MESSAGE HEADER LENGTH: Indicates the length of the HEADER.

[0046] MESSAGE OFFSET ADDR: represents the actual offset address of the actual data.

[0047] MESSAGE LENGTH: Indicates the actual data length.

[0048] MESSAGE HEADER USER DEFINE DATA: used for the reserved user-defined HEADER field.

[0049] BYTE OFFSET: Indicates the actual data content.

[0050] It is understandable that the processor can trigger the reading of the device information of the peripheral device when the switch system is started, which can be achieved specifically by sending a data acquisition request to the peripheral device; the timing of sending the data acquisition request can be that the processor receives the configuration request sent to the peripheral device when the controller sends it, triggering the reading of the device information of the peripheral device; it can even send a data acquisition request to the peripheral device when the controller sends a data transfer request, triggering the reading of the device information of the peripheral device; of course, it is also possible to send a data acquisition request to the peripheral device when a change in the peripheral device is detected, triggering the reading of the device information of the peripheral device; the specific node sent to the peripheral device to read the device information of the peripheral device is not limited in this application and is set by those skilled in the art. Among them, the first cache and the second cache are independent storage spaces in the processor. After the processor correctly reads the device information, it synchronizes the device information and stores it in the first cache and the second cache respectively for subsequent data transfer to the controller.

[0051] In some implementation scenarios, the above-mentioned calling of the first device information or the second device information matching the data transfer request and feeding back to the main controller or the slave controller includes: in response to detecting the data transfer request issued by the main controller, notifying the data transfer module to read the first device information in the first cache and transfer the first device information to the first designated storage space in the main controller; in response to detecting the data transfer request issued by the slave controller, notifying the data transfer module to read the second device information in the second cache and transfer the second device information to the second designated space in the slave controller. That is, after receiving the data transfer request issued by the controller, the processor transfers the corresponding device information from the corresponding first cache or second cache according to the type of controller, for example, the main controller can be set to correspond to the first cache, and the slave controller can correspond to the second cache; of course, in other implementation scenarios, those skilled in the art can also set the main controller to correspond to the second cache, and the slave controller to correspond to the first cache. By using DMA data to directly transfer data to the corresponding storage space in the controller, the data transfer efficiency is greatly improved, and the controller's data access efficiency is further improved. Among them, the above-mentioned first cache and second cache are specific storage spaces divided in the processor, which are used to store first device information and second device information respectively; the first designated space is a memory that can be directly read in the main controller, and similarly, the second designated space is a memory that can be directly read from the controller.

[0052] Normally, when the master controller or the slave controller initializes the driver program, it also initializes the data handling module. As a module that can independently handle data, the data handling module is controlled by the master controller and the slave controller (i.e., sends data handling requests). After the master controller and the slave controller send the data handling requests, they can continue to do other things. After completing the task corresponding to the data handling request, the data handling module will notify the master controller or the slave controller through an interrupt. Then the master controller or the slave controller determines whether to continue to require the data handling module to handle new data or to complete the data handling according to the actual situation. If the data handling is completed, the data handling module does not need to do any other work.

[0053] It is understandable that in some implementation scenarios, in order to further improve the data access efficiency, in the embodiment, the present application also proposes to deploy a supplementary data handling module in the processor, wherein the supplementary data handling module can be implemented using MMIO (Memory-Mapped I / O) technology, or can be implemented using PIO (Programmed I / O) technology; the present application does not limit this. In this implementation scenario, after detecting the data handling request sent by the main controller, the processor obtains the storage state of the first cache matching the main controller, and the above storage state includes an idle state, a normal state, and a tense state; in response to detecting that the storage state of the first cache is a normal state, the supplementary data handling module is notified to carry the first device information in the first cache state to the main controller; in response to detecting that the storage state of the first cache is a tense state, the data handling module is notified to carry the first device information in the first cache to the main controller; in response to detecting that the storage state of the first cache is a space state, a storage abnormality alarm is generated and fed back to the main controller to notify the staff to repair the processor, and the supplementary data handling module is notified to carry the first device information in the first cache to the main controller. Similarly, after detecting the data transfer request sent from the slave controller, the processor obtains the storage status of the second cache that matches the slave controller; in response to detecting that the storage status of the second cache is in a normal state, the processor notifies the supplementary data transfer module to transfer the second device information in the second cache state to the main controller; in response to detecting that the storage status of the second cache is in a tense state, the processor notifies the data transfer module to transfer the second device information in the second cache to the main controller; in response to detecting that the storage status of the second cache is in a space state, the processor generates a storage abnormality alarm and feeds it back to the main controller to notify the staff to repair the processor, and notifies the supplementary data transfer module to transfer the second device information in the second cache to the main controller. By setting the supplementary data transfer module, when the amount of data is relatively small (that is, when the storage status of the cache is in an idle state or a normal state), the supplementary data transfer module is preferentially enabled to realize fast transfer of lightweight data; when the amount of data in the cache is large, the data transfer module is enabled to realize data transfer; in addition, when the cache status is detected to be in an idle state, an alarm is issued to promptly handle the problem of being unable to obtain device information of peripheral devices that may be caused by processor failure.

[0054] In some implementation scenarios, the first device information is generated according to the device information of the acquired peripheral device and the preset management information format, including: in response to detecting that the device information of the target peripheral device is read abnormally, re-reading the device information of the target peripheral device after reaching a preset time period and updating the number of reads, that is, delaying and re-reading the data, the preset time period can be set to 1ms, or can be set according to actual conditions, and this application does not limit this. In response to detecting that the number of reads exceeds the first preset threshold, the target byte value corresponding to the target peripheral device is set to a preset fault value; the first preset threshold can be set to 3 times, of course, this application does not limit this, and can be set by a person skilled in the art, and the preset fault value can be set to OXFF for example, and of course it can also be customized by a person skilled in the art. In response to detecting that the legal check passes, the target byte value is added to the first device information; in response to detecting that the legal check fails, the header field in the first device information is set to an illegal identifier (ie, ILLEGAL), and the data field in the first device information is set to a preset fault value, that is, the data field in the entire first device information is set to OXFF.

[0055] Among them, the legal verification specifically includes: in response to detecting that the number of preset fault values ​​contained in the first device information is equal to the second preset threshold, determining that the legal verification has not passed; in response to detecting that the number of preset fault values ​​contained in the first device information is less than the second preset threshold, determining that the legal verification has passed. Preferably, the above-mentioned second preset threshold can be set to 4. In the preferred implementation scenario, when the target byte value is currently set to the preset fault value, the number of preset fault values ​​contained in the cached first device information is checked. If it is equal to 4, then if the target byte value is written into the first device information at this time, it will cause the acquisition of five consecutive byte values ​​in the first device information to fail. At this time, the first device information has a high risk of abnormality and poor availability, and it is determined that the legal verification has not passed; so at this time, all the cached first device information is set to the preset fault value, and the corresponding header field is set to an illegal flag. When checking that the number of preset fault values ​​contained in the cached first device information is less than 4, the number of byte values ​​in the first device information that failed to be acquired is within the allowable range. At this time, the first device information is transferred to the main controller for parsing and most of the valid data can still be obtained. In order to speed up data access efficiency, the legal verification is determined to have passed at this time.

[0056] That is, the present application adds a series of data verification logic when the processor reads the device information of the peripheral device, ensures the accuracy of the peripheral device read by the processor, and allows the device information to be transferred to the master-slave controller within the allowable range when some device information is read incorrectly, thereby ensuring the response speed to the data transfer request initiated by the master-slave controller, and further improving the access efficiency of the master-slave controller to the peripheral device information while ensuring the accuracy of data reading.

[0057] In some implementation scenarios, after the processor completes reading the device information of the peripheral device and completing the synchronization of the data, the processor transmits the first device information or the second device information to the corresponding master controller or slave controller through the data handling module. At this time, there is a situation where a data transmission error is caused by a failure of the data handling module. Therefore, the embodiment of the present application also proposes that in response to detecting that there is a data transmission error in the data handling module, the driver is triggered to generate a fault prompt based on the detected data transmission error; the fault prompt is fed back to the master controller and / or the slave controller to notify the staff to repair the data handling module. It is understandable that when a data transmission error occurs in the data handling module, the driver will process this error information. Generally, the hardware itself has a fault; for the application layer, the data obtained may not meet the format requirements, so an error will be reported during the parsing process, and it will not have an uncontrollable impact on the application logic; that is, it can be judged whether an error is reported during the data parsing process to determine whether a data transmission error caused by the data handling module occurs.

[0058] In the embodiment of the present application, the peripheral devices are managed by independent hardware only, and the hardware module is used to further process information, so as to perform double cache, and then the master controller and the slave controller can read their own independent device information, which reduces the hardware wiring complexity and improves the software access efficiency.

[0059] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0060] An embodiment of the present application further provides an electronic device, comprising: one or more processors; and a memory associated with the one or more processors, the memory being used to store program instructions, and the program instructions, when read and executed by the one or more processors, perform the following operations:

[0061] Generate first device information according to the read device information of the peripheral device and a preset management information format;

[0062] synchronizing the first device information to generate the second device information;

[0063] storing the first device information in a first cache, and storing the second device information in a second cache;

[0064] In response to a received data transfer request sent by the master controller or the slave controller, first device information or second device information matching the data transfer request is retrieved and fed back to the master controller or the slave controller.

[0065] In some implementation scenarios, the memory is used to store program instructions. When the program instructions are read and executed by one or more processors, the following operations are also performed:

[0066] In response to detecting that the device information reading of the target peripheral device is abnormal, re-reading the device information of the target peripheral device after a preset time period has elapsed and updating the number of readings;

[0067] In response to detecting that the number of reads exceeds a first preset threshold, setting a target byte value corresponding to the target peripheral device to a preset fault value;

[0068] In response to detecting that the legality check passes, adding the target byte value to the first device information;

[0069] In response to detecting that the legality check fails, a header field in the first device information is set to an illegal flag, and a data field in the first device information is set to a preset fault value.

[0070] In some implementation scenarios, the memory is used to store program instructions. When the program instructions are read and executed by one or more processors, the following operations are also performed:

[0071] In response to detecting that the device information reading of the target peripheral device is abnormal, re-reading the device information of the target peripheral device after a preset time period has elapsed and updating the number of readings;

[0072] In response to detecting that the number of reads exceeds a first preset threshold, setting a target byte value corresponding to the target peripheral device to a preset fault value;

[0073] In response to detecting that the legality check passes, adding the target byte value to the first device information;

[0074] In response to detecting that the legality check fails, a header field in the first device information is set to an illegal flag, and a data field in the first device information is set to a preset fault value.

[0075] In some implementation scenarios, the memory is used to store program instructions. When the program instructions are read and executed by one or more processors, the following operations are also performed:

[0076] Detecting the number of preset fault values ​​included in the first device information;

[0077] In response to detecting that the number of preset fault values ​​included in the first device information is equal to a second preset threshold, determining that the legality check has failed;

[0078] In response to detecting that the number of preset fault values ​​included in the first device information is less than a second preset threshold, it is determined that the legality check has passed.

[0079] In some implementation scenarios, the memory is used to store program instructions. When the program instructions are read and executed by one or more processors, the following operations are also performed:

[0080] In response to detecting a data transmission error in the data handling module, triggering the driver to generate a fault prompt based on the detected data transmission error;

[0081] The fault prompt is fed back to the main controller and / or the slave controller to notify the staff to inspect the data handling module.

[0082] in, Figure 8 The architecture of the electronic device is shown exemplarily, and may specifically include a processor 810, a video display adapter 811, a disk drive 812, an input / output interface 813, a network interface 814, and a memory 820. The processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 814, and the memory 820 may be communicatively connected via a bus 830.

[0083] Among them, the processor 810 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in this application.

[0084] The memory 820 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 820 can store an operating system 821 for controlling the execution of the electronic device 800, and a basic input and output system (BIOS) 822 for controlling the low-level operations of the electronic device 800. In addition, a web browser 823, a data storage management system 824, and an icon font processing system 825, etc. can also be stored. The above-mentioned icon font processing system 825 can be an application program that specifically implements the operations of the aforementioned steps in the embodiment of the present application. In short, when the technical solution provided in the present application is implemented by software or firmware, the relevant program code is stored in the memory 820 and is called and executed by the processor 810.

[0085] The input / output interface 813 is used to connect the input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0086] The network interface 814 is used to connect to a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0087] The bus 830 comprises a pathway for transmitting information between the various components of the device (eg, the processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 814, and the memory 820).

[0088] In addition, the electronic device 800 can also obtain information on specific collection conditions from the virtual resource object collection condition information database for use in condition judgment, etc.

[0089] It should be noted that, although the above device only shows a processor 810, a video display adapter 811, a disk drive 812, an input / output interface 813, a network interface 814, a memory 820, a bus 830, etc., in the specific implementation process, the device may also include other components necessary for normal execution. In addition, it can be understood by those skilled in the art that the above device may also only include components necessary for implementing the solution of the present application, and does not necessarily include all the components shown in the figure.

[0090] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above switch management method embodiments when running.

[0091] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0092] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0093] The above is a detailed introduction to a switch and a switch management method provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A switch, characterized in that: The switch comprises: Processor, master controller, slave controller, multiple peripheral devices; The processor is connected to the plurality of peripheral devices via a first bus, so that the processor reads device information in the peripheral devices via the first bus; The processor is connected to the master controller and the slave controller respectively through the second bus, so that the master controller and the slave controller read the device information cached in the processor through the second bus.

2. A switch according to claim 1, characterized in that: The processor also includes a data transfer module for transferring the device information cached in the processor to the master controller and the slave controller.

3. A switch according to claim 1 or 2, characterized in that: The master controller is interconnected with the slave controller via a universal input / output interface to achieve the transmission of heartbeat signals between the master controller and the slave controller.

4. A switch management method, applied to the switch according to claim 2 or 3, characterized in that: The processor in the switch is used to: Generate first device information according to the read device information of the peripheral device and a preset management information format; synchronize the first device information to generate second device information; storing the first device information in a first cache, and storing the second device information in a second cache; In response to a received data transfer request sent by a master controller or a slave controller, first device information or second device information matching the data transfer request is retrieved and fed back to the master controller or the slave controller.

5. A switch management method according to claim 4, characterized in that: The retrieving the first device information or the second device information matching the data transfer request and feeding back to the master controller or the slave controller includes: In response to detecting a data transfer request sent by the main controller, instructing a data transfer module to read the first device information in the first cache and transfer the first device information to a first designated storage space in the main controller; In response to detecting the data transfer request sent by the slave controller, the data transfer module is notified to read the second device information in the second cache and transfer the second device information to a second designated space in the slave controller.

6. A switch management method according to claim 4, characterized in that: The generating of the first device information according to the acquired device information of the peripheral device and the preset management information format includes: in response to detecting that the device information reading of the target peripheral device is abnormal, re-reading the device information of the target peripheral device after reaching a preset time period and updating the reading times; In response to detecting that the number of reads exceeds a first preset threshold, setting the target byte value corresponding to the target peripheral device to a preset fault value; In response to detecting that the legality check passes, adding the target byte value to the first device information; In response to detecting that the legality check fails, the header field in the first device information is set to an illegal flag, and the data field in the first device information is set to the preset fault value.

7. A switch management method according to claim 6, characterized in that: The legal verification includes: Detecting the number of preset fault values ​​included in the first device information; In response to detecting that the number of preset fault values ​​included in the first device information is equal to a second preset threshold, determining that the legality check has failed; In response to detecting that the number of preset fault values ​​included in the first device information is less than the second preset threshold, it is determined that the legality check has passed.

8. A switch management method according to any one of claims 4 to 7, characterized in that: The method further comprises: In response to detecting a data transmission error in the data handling module, triggering the driver to generate a fault prompt based on the detected data transmission error; The fault prompt is fed back to the main controller and / or the slave controller to notify the staff to inspect the data handling module.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the switch management method according to any one of claims 4 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the switch management method according to any one of claims 4 to 8 when executed by a processor.

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