Substrate thinning method of backside illuminated CMOS chip, chip and electronic equipment
By combining integrity detection, wet corrosion and dry etching on the back-illuminated CMOS chip, the problem of difficulty in thinning the back-illuminated CMOS chip substrate in the prior art is solved, and the chip charge collection efficiency is improved and the damage rate is reduced.
Patent Information
- Application Number
- CN202510285318.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-06-06
AI Technical Summary
The prior art is difficult to effectively thin the substrate of the back-illuminated CMOS chip, which makes it difficult to eliminate the impact of the passivation layer on the gain performance of the device.
Intact chips were obtained through integrity detection, wet corrosion was initially thinned by using fixtures, and then dry etching was used to further thin them, and an oxide layer was formed at the etching.
Effective thinning of the back-illuminated CMOS chip substrate is achieved, the thickness of the passivation layer is reduced, the charge collection efficiency is improved, and the substrate thinning of the back-illuminated CMOS chip is achieved, and the damage rate to the chip is extremely low.
Smart Images
Figure CN120111974A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of image sensors, and in particular to a substrate thinning method for a back-illuminated CMOS chip, a chip and an electronic device. Background Art
[0002] There is a passivation layer tens of nanometers thick on the silicon substrate of the back-illuminated CMOS image sensor. Although the passivation layer plays a protective role and can extend the service life of the chip, it has an impact on the device gain performance and other aspects.
[0003] In order to reduce the influence of the passivation layer on the gain performance of the EBCMOS device and obtain better imaging effects, it is necessary to thin the back passivation layer (substrate) of the CMOS image sensor. Therefore, it is very important to choose a suitable thinning method, but there is no detailed report on the back thinning of CMOS image sensors. Most of the thinning processes mentioned the methods for realizing the back thinning process of silicon wafers, mainly physical mechanical grinding, chemical wet etching and chemical mechanical polishing.
[0004] However, the existing methods are not suitable for substrate thinning of back-illuminated CMOS chips. For example, the mechanical grinding method has poor process stability and is easy to damage the silicon wafer surface; for example, the chemical wet etching method has a fast etching rate but is easy to damage the chip circuit; for example, the chemical mechanical polishing method can well thin the silicon wafer surface, but for back-illuminated sensors, such as the Sony IMX183 chip, the internal circuit pins of the chip will cause great interference to the mechanical polishing, making the chip unsuitable for thinning using this method.
[0005] Therefore, there is an urgent need to develop a substrate thinning method for a back-illuminated CMOS chip to be suitable for substrate thinning of a back-illuminated CMOS image sensor. Summary of the invention
[0006] In view of the above problems, the present invention provides a substrate thinning method for a back-illuminated CMOS chip, a chip and an electronic device.
[0007] The technical solution adopted by the present invention to solve the technical problem is as follows:
[0008] In a first aspect, the present invention provides a method for thinning a substrate of a back-illuminated CMOS chip, characterized by comprising:
[0009] Conduct integrity test on the chip;
[0010] Using a fixture to hold the intact chip, wet etching is performed on the area of the substrate that needs to be thinned to initially thin the area that needs to be thinned, and the fixture can prevent the etching liquid from exceeding the area that needs to be thinned;
[0011] Etching the area to be thinned by using a dry etching process to further thin the area to be thinned;
[0012] An oxide layer is formed at the etched area.
[0013] In a preferred embodiment, before performing the wet etching, the function of the fixture to prevent the etching liquid from exceeding the area to be thinned is checked. After performing the wet etching, the chip is cleaned and dried, and the surface of the dried chip is observed using an optical microscope. If there are contaminants, the chip is cleaned and dried again until there are no contaminants on the chip surface.
[0014] In a preferred embodiment, the dry etching process for etching the area to be thinned is specifically as follows: using an inductively coupled plasma etcher to dry etch the area to be thinned, the etching gas and gas flow rate are 40 sccm of SF6 and 5 sccm of O2, the pressure in the chamber is 1 Pa, the excitation power supply power is 300 W, the bias power supply power is 50 W, and the etching time is 10 s.
[0015] In a preferred embodiment, the integrity detection includes at least one of whether the chip imaging is normal, whether the chip is defective, and whether the circuit of the chip is complete.
[0016] In a preferred embodiment, the integrity inspection of the unpackaged chip includes whether the chip is defective and whether the circuit of the chip is complete; the integrity inspection of the packaged chip includes whether the chip imaging is normal.
[0017] In a preferred embodiment, the clamp includes a base and an upper cover, the base is provided with a groove for placing the chip, the upper cover and / or the base is provided with a sealing ring, the upper cover and the base are correspondingly arranged to jointly clamp the chip, the upper cover is provided with a hole for passing the corrosive liquid, and the sealing ring is used to prevent the corrosive liquid from diffusing to the area of the chip that does not need to be thinned, and the material of the upper cover and the base can both be polytetrafluoroethylene.
[0018] In a preferred embodiment, before the packaged chip is subjected to the wet etching, a step of de-packaging using an etching solution is performed.
[0019] In a preferred embodiment, forming an oxide layer at the etched location comprises placing the dry-etched chip in the air until an oxide layer is formed at the etched location on the substrate.
[0020] In a second aspect, the present invention provides a thinned chip, wherein the thinned chip is prepared by using the substrate thinning method of the back-illuminated CMOS chip described in the first aspect.
[0021] In a third aspect, the present invention provides an electronic device, characterized in that it comprises: the thinned chip described in the second aspect.
[0022] The substrate thinning method of the back-illuminated CMOS chip of the present invention obtains a good chip through integrity detection, and limits the etching liquid through a fixture to avoid corrosion of other areas that do not need to be corroded, thereby protecting the structure of the chip and ensuring that the chip functions well; dry etching is used for secondary thinning on the basis of wet etching. Wet etching can achieve rapid thinning, uniform surface and low cost. Based on this, dry etching is performed to accurately control thinning. The substrate of the back-illuminated CMOS chip is thinned by the process method, which reduces the thickness of the chip passivation layer and improves the charge collection efficiency of the CMOS chip. The method is suitable for substrate thinning of back-illuminated CMOS chips, and the damage rate to the chip is extremely low. The charge collection efficiency of the chip after thinning is high, thereby improving the performance of electronic devices using the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 A flow chart of a method for thinning a substrate of a back-illuminated CMOS chip;
[0025] Figure 2 This is the imaging picture of the back-illuminated CMOS chip before thinning;
[0026] Figure 3 The image of the IMX183 chip after removing the glass package, cleaning and drying;
[0027] Figure 4 A three-dimensional diagram of the protective fixture;
[0028] Figure 5 To protect the base structure diagram of the fixture;
[0029] Figure 6 The structural diagram of the upper cover for protecting the fixture;
[0030] Figure 7 (a) is the imaging picture after removing part of the film under high illumination conditions;
[0031] Figure 7 (b) is the imaging picture under low illumination and one-way occlusion conditions;
[0032] Figure 8 These are the images taken without light before and after the oxide layer is formed after thinning. DETAILED DESCRIPTION
[0033] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.
[0035] See also Figure 1 This embodiment provides a method for thinning a substrate of a back-illuminated CMOS chip, comprising:
[0036] Perform integrity test on back-illuminated CMOS chips to obtain intact chips;
[0037] The intact chip is clamped by a fixture, and the substrate area of the intact chip clamped by the fixture is wet-etched to preliminarily thin the area to be thinned, so as to obtain a chip with a preliminarily thinned substrate, wherein the fixture can prevent the etching liquid from diffusing to the area of the clamped chip that does not need to be thinned, that is, limit the etching range;
[0038] Etching the substrate of the preliminarily thinned chip by dry etching to thin the substrate, wherein the etching position is the area processed by wet etching, that is, etching the area to be thinned to further thin the area to be thinned;
[0039] After dry etching, an oxide layer is formed at the etched portion on the chip substrate.
[0040] The method thins only the intact chips through integrity detection. The intact chips have areas that need to be thinned and areas that do not need to be thinned. The areas that need to be thinned are located on the substrate, that is, the substrate thinning is achieved. In the substrate thinning method, dry etching is performed on the wet-etched area. For the same area on the substrate that needs to be thinned, thinning is performed twice, the first time is wet etching, and the second time is dry etching.
[0041] The following is an exemplary description of the specific implementation of the present invention by taking the thinning of the IMX183 chip as an example, and it can be understood that the substrate thinning method provided by the present invention is also applicable to other types of back-illuminated CMOS chips. Here, the substrate of the chip is a silicon substrate.
[0042] S1. Obtain a back-illuminated CMOS chip and perform integrity test on the chip to exclude damaged or destroyed chips and obtain intact chips through integrity test.
[0043] It can be understood that the results of the integrity test are divided into chips that pass the integrity test and chips that fail the integrity test.
[0044] The integrity inspection includes at least one of whether the imaging is normal, whether there is a defect, and whether the line is complete.
[0045] For bare chip, the integrity test includes whether there are defects and whether the circuit is complete. Specifically, an optical microscope can be used to check whether the overall circuit structure of the chip is complete, whether there are missing corners, and whether the surface pad is scratched.
[0046] For packaged chips, the integrity test is an imaging test. For chips that do not have imaging problems, they are considered to be intact chips. The chips need to be de-packaged before S2. Here, hydrofluoric acid solution is used to remove the quartz glass package of the intact chip, that is, wet etching is used to remove the package. Here, a de-packaging fixture is used for de-packaging. The de-packaging fixture can not only clamp the chip, but also prevent the corrosive liquid from diffusing to the part of the chip that does not need to be thinned, and prevent the corrosive solution from accidentally damaging the internal circuits of the chip and the electronic components of the driver board. After corrosion, the chip is cleaned and dried, and an optical microscope is used to observe whether there are still contaminants on the surface of the chip. If there are still contaminants, it needs to be cleaned again and blown dry with nitrogen.
[0047] As a specific embodiment, Figure 2 (a) and (b) are the images of the MV-CE200-11UM camera under low illumination and high illumination respectively when the camera is not equipped with a focusing lens. It can be seen that the images taken by the camera can correctly reflect the illumination at the time of shooting, proving that the image acquisition function of the back-illuminated CMOS chip and the camera image processing and data transmission functions are normal. Through integrity testing, the back passivation layer of the IMX183 chip can be corroded and thinned. If imaging problems occur in the subsequent chip and camera, it can be explained that it is not related to the quality of the chip and camera itself.
[0048] like Figure 3 The image shown is of the IMX183 chip after the glass package was removed, cleaned and dried. The irregular shadow part above the image is the glass package that was not removed by the tweezers. The chip can still be imaged after the glass package is removed, and even the edge of the glass can be captured. It can be seen that the use of chemical etching to remove the chip glass package did not cause damage to the chip, proving that this method is feasible.
[0049] S2. Clamp the chip with a fixture (called a protective fixture) and wet-etch the passivation layer of the chip;
[0050] It is understandable that the chip includes areas that need to be thinned and areas that do not need to be thinned. The areas that need to be thinned are located on the substrate. The protective fixture can not only clamp the chip, but also prevent the corrosive liquid from spreading to the areas of the chip that do not need to be thinned, specifically by using a rubber sealing ring to prevent the corrosive liquid from spreading.
[0051] See also Figures 4 to 6 The protective fixture includes a base and an upper cover. The upper cover and the base are arranged correspondingly. When the upper cover and the base form a fixture, there is a chip cavity between the upper cover and the base. Figure 4 The upper cover and the base are connected by screws to clamp the chip. Figure 5 The base is provided with a groove for placing the chip; the upper cover and / or the base is provided with the sealing ring; see Figure 6 The upper cover is provided with an etching liquid through hole, and the wet etching etching liquid enters the chip cavity through the etching liquid through hole, and the range of the etching liquid is limited by the sealing ring to the chip to prevent the etching liquid from spreading. Here, the area to be thinned corresponds to the etching liquid through hole, and specifically, the areas of the two can be almost the same).
[0052] Here, the material of the protective fixture (upper cover and base) is polytetrafluoroethylene material, which has good acid resistance and can protect the chip driver board to prevent accidental damage to the internal circuits of the chip and the electronic components of the driver board when the hydrofluoric acid solution thins the passivation layer.
[0053] The etching liquid is hydrofluoric acid etching liquid. Before etching, the protective fixture is cleaned once. After the chip is fixed in the fixture, the water tightness of the protective fixture is checked before etching, that is, the sealing and isolation effect of the sealing ring is checked. After passing the inspection, the IMX183 chip is corroded.
[0054] After etching, the chip needs to be cleaned and dried, and an optical microscope is used to observe whether there are any contaminants on the chip surface. If there are still contaminants, it needs to be cleaned again and blown dry with nitrogen.
[0055] In some embodiments, the depackaging jig and the wet etching jig are the same jig.
[0056] S3. For the chip with the initially thinned substrate obtained in S2, the chip substrate is etched by dry etching to further thin the substrate.
[0057] S4. After dry etching, place the chip in the air until an oxide layer is formed on the substrate.
[0058] Based on the thinning results of S2, the IMX183 chip substrate is further etched and thinned by dry etching in the area that needs to be thinned. Here, the equipment used is an inductively coupled plasma etcher ICP-98A. The etching gas is a mixed gas, and the etching gas and the gas flow rate are 40sccm SF 6 and 5 sccm of O 2, chamber pressure 1Pa, excitation power 300W, bias power 50W, etching time 10s. After etching, the dark current of the chip will be large, resulting in too bright imaging. After etching by the etcher, the chip needs to be placed in the air for a period of time to wait for a natural oxide layer to form at the etched area, and the imaging function can be restored to normal. At this point, a chip with a thinned substrate is obtained.
[0059] S5. Detect the imaging capability of the chip after dry etching thinning.
[0060] The chip obtained by S4 was tested and found that the chip can still be imaged and even the edge of the substrate can be captured. It can be seen that the thinning method of this embodiment does not cause damage to the chip, and the chip can still be imaged normally after thinning the back, which proves the feasibility of the method.
[0061] The chips that pass the S5 test are retained, and the chips that fail the test are discarded.
[0062] Based on the imaging picture after removing the package, see Figure 3 During the subsequent wet etching of the chip surface, it was found that there was a thin film on the chip surface that was insoluble in the etching solution. Figure 7 (a) is the image after only part of the film is removed from the chip (the middle part, i.e., the red circle), it can be seen that the surface scratches are distributed in the area where the film exists, and the image of the area where the film is removed is brighter than the area where the film remains. Figure 7 (b) The image after reducing the illumination and adding a shield. It can be found that the chip imaging can reflect the level of ambient light illumination during shooting, and the imaging function is normal. Therefore, the removal of the film does not affect the imaging function of the chip, and the chip back thinning operation can continue.
[0063] Figure 8 This is the image when there is no light, Figure 8 (a) is the image of the IMX183 chip when the back substrate is thinned but no oxide layer is formed. Figure 8 (b) is the image after the oxide layer has been formed. It can be seen that the chip can still be imaged normally after thinning the back. However, by comparison, it is found that Figure 8 (a) Brightness (see Figure 8 (a) The circular area in the center, where no oxide layer is formed) is higher than Figure 8 (b) is the imaging picture, which is caused by the noise current caused by the surface state after the passivation layer is removed.
[0064] The substrate thinning method of the back-illuminated CMOS chip of the present invention obtains a good chip through integrity detection, and limits the etching liquid through a fixture to avoid corrosion of other areas that do not need to be corroded, thereby protecting the structure of the chip and ensuring that the function of the chip is intact; further thinning is performed on the basis of wet etching, and dry etching is used for secondary thinning. Wet etching is fast thinning, the surface is uniform and the cost is low, and dry etching is performed based on this to accurately control thinning. The process method combining wet etching and dry etching realizes thinning of the substrate of the back-illuminated CMOS chip. Based on this method, the thickness of the chip passivation layer is reduced, and the number of electrons collected in the pixel area is increased under the same incident electron energy, thereby improving the charge collection efficiency of the CMOS chip. The method is suitable for substrate thinning of back-illuminated CMOS chips, and the damage rate to the chip is extremely low. The method also takes into account the accuracy and rapidity of thinning. The chip charge collection efficiency after thinning is high, thereby improving the performance of electronic equipment using the chip.
[0065] This embodiment provides a chip, referred to as a thinned chip, which is prepared by using the substrate thinning method of the back-illuminated CMOS chip.
[0066] This embodiment also provides an electronic device, including the thinned chip. The electronic device also includes a power supply module and other structures, a storage module, a processing module, a control module and other structures as needed.
[0067] Here, the electronic device is a camera.
[0068] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for thinning a substrate of a back-illuminated CMOS chip, characterized in that: include: Conduct integrity test on the chip; Using a fixture to hold the intact chip, wet etching is performed on the area of the substrate that needs to be thinned to initially thin the area that needs to be thinned, and the fixture can prevent the etching liquid from exceeding the area that needs to be thinned; Etching the area to be thinned by using a dry etching process to further thin the area to be thinned; An oxide layer is formed at the etched area.
2. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, wherein: Before the wet etching, check the function of the fixture to prevent the etching liquid from exceeding the area to be thinned. After the wet etching, clean and dry the chip, and observe the surface of the dried chip with an optical microscope. If there are contaminants, clean and dry again until there are no contaminants on the chip surface.
3. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, characterized in that: The method of etching the area to be thinned by dry etching process is specifically as follows: using an inductively coupled plasma etcher to dry etch the area to be thinned, the etching gas and gas flow rate are 40 sccm SF6 and 5 sccm O2, the pressure in the chamber is 1 Pa, the excitation power supply power is 300 W, the bias power supply power is 50 W, and the etching time is 10 s.
4. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, wherein: The integrity detection includes at least one of whether the chip imaging is normal, whether the chip is defective, and whether the circuit of the chip is complete.
5. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 4, characterized in that: The integrity test of unpackaged chips is to check whether the chip is defective and whether the chip circuit is complete; the integrity test of packaged chips is to check whether the chip imaging is normal.
6. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, wherein: The clamp includes a base and an upper cover. The base is provided with a groove for placing the chip. The upper cover and / or the base are provided with a sealing ring. The upper cover and the base are correspondingly arranged to jointly clamp the chip. The upper cover is provided with a hole for passing the corrosive liquid. The sealing ring is used to prevent the corrosive liquid from diffusing to the area of the chip that does not need to be thinned. The materials of the upper cover and the base can both be polytetrafluoroethylene.
7. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, wherein: Before the packaged chip is subjected to the wet etching, a step of de-packaging using an etching solution is performed.
8. The method for thinning the substrate of a back-illuminated CMOS chip according to claim 1, wherein: The step of forming an oxide layer at the etched location specifically includes placing the dry-etched chip in the air until an oxide layer is formed at the etched location on the substrate.
9. A thinned chip, wherein the thinned chip is prepared by the substrate thinning method of a back-illuminated CMOS chip according to any one of claims 1 to 8.
10. An electronic device, characterized in that: include: The thinned chip as claimed in claim 9.