Page buffer, memory device, and method of operating page buffer

Abstract

The present disclosure may provide a page buffer, a memory device, and a method of operating the page buffer. The page buffer includes: a sensing node connected to a bit line; a bit line voltage control circuit configured to pre-charge the bit line during a verify operation; a sensing node voltage controller configured to pre-charge the sensing node when the bit line is pre-charged; a first latch connected to the sensing node and configured to store, after the sensing node is pre-charged, a first bit value determined based on a first evaluation operation among bit values corresponding to a voltage level of the sensing node; and a second latch connected to the sensing node and configured to store a second bit value determined based on a second evaluation operation after the first bit value is stored. The first latch stores a first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0177437, filed with the Korean Intellectual Property Office on December 8, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a page buffer related to performing a programming operation, a memory device including the page buffer, and a method of operating the page buffer. Background art

[0004] A memory device may be a device for storing data and may be classified into a volatile memory device and a non - volatile memory device.

[0005] Each memory device may include a page buffer. The page buffer may sense data stored in memory cells through bit lines connected to the memory cells and store the data during a read operation or a verify operation.

[0006] During a verify operation, when using one verify voltage to verify the programming state, the range of the threshold voltage distribution becomes wider according to the different programming speeds of the memory cells. Therefore, the memory device may perform a programming operation according to the triple verify program (TPGM) method to form a narrower range of the threshold voltage distribution and increase the speed of the programming operation. The triple verify programming method may be an operation of performing verify operations using three sequentially increasing verify voltages or an operation of sensing the memory cells three times by differently setting time based on one verify voltage.

[0007] On the other hand, in the case of the triple verify programming method, three latches may be required in the page buffer to store verify data. However, when the number of latches increases, the size of the page buffer also increases, so a scheme for performing the triple verify programming method and at the same time reducing the number of latches is needed. Summary of the invention

[0008] Embodiments of the present disclosure may provide a page buffer connected to memory cells via bit lines. The page buffer may include: a sense node connected to the bit lines; a bit line voltage control circuit configured to pre-charge the bit lines during a verify operation; a sense node voltage controller configured to pre-charge the sense node when the bit lines are pre-charged; a first latch connected to the sense node and configured to store a first bit value determined based on a first evaluation operation among a plurality of bit values corresponding to the voltage level of the sense node after the sense node is pre-charged; and a second latch connected to the sense node and configured to store a second bit value determined based on a second evaluation operation among the plurality of bit values after the first bit value is stored in the first latch, wherein the first latch stores the first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.

[0009] Embodiments of the present disclosure may provide a memory device. The memory device may include: memory cells each included in any one of a plurality of threshold voltage regions divided by a plurality of reference voltages according to a programming operation; a page buffer connected to the memory cells via bit lines; and a programming operation controller configured to control the programming operation, wherein the page buffer may include: a first latch configured to store a first bit value among a plurality of bit values indicating one threshold voltage region during a verify operation included in the programming operation; a second latch configured to store a second bit value among the plurality of bit values during the verify operation; and a bit line voltage control circuit configured to control a voltage applied to the bit lines based on the first bit value and the second bit value during a programming voltage application operation after the verify operation included in the programming operation.

[0010] Embodiments of the present disclosure may provide a method of operating a page buffer connected to memory cells via bit lines. The method may include: pre-charging the bit lines and the sense node; performing a first evaluation operation on the sense node based on a first evaluation time; storing a first bit value determined based on the first evaluation operation in a first latch; performing a second evaluation operation based on a second evaluation time longer than the first evaluation time; storing a second bit value determined based on the second evaluation operation in a second latch; performing a third evaluation operation based on a third evaluation time longer than the second evaluation time; storing the first bit value determined based on the third evaluation operation in the first latch; determining whether a verify operation passes based on the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation; and controlling a voltage applied to the bit lines based on the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram showing a threshold voltage region of a memory cell according to an embodiment of the present disclosure.

[0013] Figure 3 is a diagram showing an example of performing a triple-verification programming operation according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram showing an example of performing a triple-verification programming operation according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram showing bit values stored in a first latch and a second latch based on a triple-verification programming operation according to an embodiment of the present disclosure.

[0016] Figure 6 is a timing diagram showing a bit line setting operation according to an embodiment of the present disclosure.

[0017] Figure 7 is a diagram showing an example of controlling a bit line voltage of a memory cell included in a fourth threshold voltage region according to an embodiment of the present disclosure.

[0018] Figure 8 is a diagram showing an example of changing a bit value stored in a first latch before controlling a bit line voltage of a memory cell included in a third threshold voltage region according to an embodiment of the present disclosure.

[0019] Figure 9 is a diagram showing an example of controlling a bit line voltage of a memory cell included in a third threshold voltage region according to an embodiment of the present disclosure.

[0020] Figure 10 is a diagram showing an example of changing a bit value stored in a first latch before controlling a bit line voltage of a memory cell included in any one of a first threshold voltage region and a second threshold voltage region according to an embodiment of the present disclosure.

[0021] Figure 11 is a diagram showing an example of controlling a bit line voltage of a memory cell included in any one of a first threshold voltage region and a second threshold voltage region according to an embodiment of the present disclosure.

[0022] Figure 12 is a diagram showing an example of a page buffer according to an embodiment of the present disclosure.

[0023] Figure 13 is a diagram showing a method of performing a triple-verification programming operation according to an embodiment of the present disclosure.

[0024] Figure 14It is a diagram showing a memory device according to an embodiment of the present disclosure. Detailed Description

[0025] A specific structural or functional description in the embodiments of the present disclosure introduced in this specification or this application is provided as an example to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be construed as limited to the embodiments described in this specification or this application. It should be understood that when an element or layer is referred to as "on", "connected to", or "coupled to" another element or layer, it can be directly located, connected, or coupled to the other element or layer, or there may be intermediate elements or layers. In contrast, when an element is referred to as "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. When describing the time flow relationship, operation method, or manufacturing method of components, in the case of describing the front-back relationship in terms of time or the front-back relationship in terms of process (e.g., through "after", "subsequently", "then", or "before"), unless "immediately" or "directly" is used, it may also include discontinuous cases. In addition, when describing the components, signals, values of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only used to distinguish one component, signal, value, etc. from another component, signal, value, etc., but do not limit the substance, order, sequence, or quantity of the components, signals, values, etc.

[0026] Various embodiments of the present disclosure relate to a page buffer, a memory device including the page buffer, and a method of operating the page buffer, which can improve the threshold voltage distribution of memory cells and reduce the circuit size.

[0027] Figure 1 It is a diagram showing a page buffer according to an embodiment of the present disclosure.

[0028] Referring to Figure 1 , the page buffer 100 can be coupled to the memory cells through the bit lines BL. The page buffer 100 can sense the data stored in the memory cells through the bit lines BL and store the data during a read operation or a verify operation. In addition, the page buffer 100 can store the write data provided from an external system during a programming operation.

[0029] In an embodiment, the page buffer 100 may include a bit line voltage control circuit 110, a sense node (SO) voltage control circuit 120, a first latch 130, a second latch 140, and a data latch 150. In addition, the page buffer 100 may further include a common sense node CSO connected to the bit line BL, a sense node SO connected to the bit line BL through the common sense node CSO, and a twenty-first transistor T21.

[0030] In an embodiment, the twenty-first transistor T21 may be connected to the ground voltage (ground) GND, the eleventh transistor T11, the fourteenth transistor T14, the seventeenth transistor T17, and the twentieth transistor T20. The twenty-first transistor T21 may connect the ground voltage GND to the eleventh transistor T11, the fourteenth transistor T14, the seventeenth transistor T17, or the twentieth transistor T20 in response to the voltage level of the sense node SO. The twenty-first transistor T21 may be implemented as an NMOS transistor.

[0031] In an embodiment, the bit line voltage control circuit 110 may control the voltage applied to the bit line BL. For example, the bit line voltage control circuit 110 may pre-charge the bit line BL to a pre-charge voltage, or may set the voltage of the bit line BL according to the verification state of the memory cell when applying a programming voltage to the memory cell.

[0032] In an embodiment, the bit line voltage control circuit 110 may include a first transistor T1 to an eighth transistor T8.

[0033] The first transistor T1 may be connected to the bit line and the common sense node. The first transistor T1 may electrically connect the bit line BL to the common sense node CSO in response to the page buffer sense signal PBS. The first transistor T1 may be implemented as an NMOS transistor.

[0034] The second transistor T2 may be connected to the common sense node CSO and the sense node SO. The second transistor T2 may electrically connect the common sense node CSO to the sense node SO in response to the sense node sense signal TRANSO. The second transistor T2 may be implemented as an NMOS transistor.

[0035] The third transistor T3 may be connected to the source of the power supply voltage VCC and the fourth transistor T4. The third transistor T3 may transfer the power supply voltage VCC to the fourth transistor T4 in response to the first bit value LC1 stored in the first latch 130. The third transistor T3 may be implemented as a PMOS transistor.

[0036] The fourth transistor T4 can be connected to the third transistor T3 and the common sensing node CSO. The fourth transistor T4 can transmit a voltage corresponding to the first bit line voltage control signal BLT to the common sensing node CSO in response to the first bit line voltage control signal BLT. The fourth transistor T4 can be implemented as an NMOS transistor.

[0037] The fifth transistor T5 can be connected to the source of the power supply voltage VCC and the sixth transistor T6. The fifth transistor T5 can transmit the power supply voltage VCC to the sixth transistor T6 in response to the second bit value LC2 stored in the second latch 140. The fifth transistor T5 can be implemented as a PMOS transistor.

[0038] The sixth transistor T6 can be connected to the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8. The sixth transistor T6 can transmit the power supply voltage VCC received from the fifth transistor T5 to the seventh transistor T7 or the eighth transistor T8 in response to the first inverted bit value LC1B, where the first inverted bit value LC1B is the inverted value of the first bit value LC1 stored in the first latch 130. The sixth transistor T6 can be implemented as a PMOS transistor.

[0039] The seventh transistor T7 can be connected to the sixth transistor T6 and the common sensing node CSO. The seventh transistor T7 can transmit a voltage corresponding to the second bit line voltage control signal BLD to the common sensing node CSO in response to the second bit line voltage control signal BLD. The seventh transistor T7 can be implemented as an NMOS transistor.

[0040] The eighth transistor T8 can be connected to the sixth transistor T6 and the sensing node SO. The eighth transistor T8 can transmit a voltage corresponding to the third bit line voltage control signal BLM to the common sensing node CSO in response to the third bit line voltage control signal BLM. The eighth transistor T8 can be implemented as a PMOS transistor.

[0041] In an embodiment, the sense node voltage control circuit 120 can control the voltage of the sense node SO. For example, the sense node voltage control circuit 120 can pre-charge the sense node SO to a pre-charge voltage.

[0042] In an embodiment, the first latch 130 can store the first bit value LC1 among a plurality of bit values indicating a threshold voltage region of a memory cell during a verification operation.

[0043] In an embodiment, the first latch 130 can include the ninth transistor T9 to the fourteenth transistor T14.

[0044] The ninth transistor T9 can be connected to the sense node SO and the tenth transistor T10. The ninth transistor T9 can electrically connect the sense node SO to the tenth transistor T10 in response to a first latch connection signal TL1. The ninth transistor T9 can be implemented as an NMOS transistor.

[0045] The tenth transistor T10 can be connected to the ninth transistor T9 and the ground voltage GND. The tenth transistor T10 can electrically connect the ninth transistor T9 to the ground voltage GND in response to a first bit value LC1. The tenth transistor T10 can be implemented as an NMOS transistor.

[0046] The eleventh transistor T11 can be connected to the twenty - first transistor T21 and the node storing the first bit value LC1. The eleventh transistor T11 can electrically connect the node storing the first bit value LC1 to the twenty - first transistor T21 in response to a first latch reset signal RST1 among the latch control signals for controlling the first latch 130. The eleventh transistor T11 can be implemented as an NMOS transistor.

[0047] The twelfth transistor T12 can be connected to the sense node SO and the thirteenth transistor T13. The twelfth transistor T12 can electrically connect the sense node SO to the thirteenth transistor T13 in response to a second latch connection signal TL2. The twelfth transistor T12 can be implemented as an NMOS transistor.

[0048] The thirteenth transistor T13 can be connected to the twelfth transistor T12 and the ground voltage GND. The thirteenth transistor T13 can electrically connect the twelfth transistor T12 to the ground voltage GND in response to a first inverted bit value LC1B. The thirteenth transistor T13 can be implemented as an NMOS transistor.

[0049] The fourteenth transistor T14 can be connected to the twenty - first transistor T21 and the node storing the first inverted bit value LC1B. The fourteenth transistor T14 can electrically connect the node storing the first inverted bit value LC1B to the twenty - first transistor T21 in response to a first latch set signal SET1 among the latch control signals for controlling the first latch 130. The fourteenth transistor T14 can be implemented as an NMOS transistor.

[0050] In an embodiment, the second latch 140 can store a second bit value LC2 among a plurality of bit values indicating a threshold voltage region of a memory cell during a verification operation.

[0051] In an embodiment, the second latch 140 can include the fifteenth transistor T15 to the twentieth transistor T20.

[0052] The fifteenth transistor T15 may be connected to the sense node SO and the sixteenth transistor T16. The fifteenth transistor T15 may electrically connect the sense node SO to the sixteenth transistor T16 in response to a third latch connection signal TL3. The fifteenth transistor T15 may be implemented as an NMOS transistor.

[0053] The sixteenth transistor T16 may be connected to the fifteenth transistor T15 and the ground voltage GND. The sixteenth transistor T16 may electrically connect the fifteenth transistor T15 to the ground voltage GND in response to a second bit value LC2. The sixteenth transistor T16 may be implemented as an NMOS transistor.

[0054] The seventeenth transistor T17 may be connected to the twenty - first transistor T21 and the node storing the second bit value LC2. The seventeenth transistor T17 may electrically connect the node storing the second bit value LC2 to the twenty - first transistor T21 in response to a second latch reset signal RST2 among the latch control signals for controlling the second latch 140. The seventeenth transistor T17 may be implemented as an NMOS transistor.

[0055] The eighteenth transistor T18 may be connected to the sense node SO and the nineteenth transistor T19. The eighteenth transistor T18 may electrically connect the sense node SO to the nineteenth transistor T19 in response to a fourth latch connection signal TL4. The eighteenth transistor T18 may be implemented as an NMOS transistor.

[0056] The nineteenth transistor T19 may be connected to the eighteenth transistor T18 and the ground voltage GND. The nineteenth transistor T19 may electrically connect the eighteenth transistor T18 to the ground voltage GND in response to a second inverted bit value LC2B, where the second inverted bit value LC2B is the inverted value of the second bit value LC2. The nineteenth transistor T19 may be implemented as an NMOS transistor.

[0057] The twentieth transistor T20 may be connected to the twenty - first transistor T21 and the node storing the second inverted bit value LC2B. The twentieth transistor T20 may electrically connect the node storing the second inverted bit value LC2B to the twenty - first transistor T21 in response to a second latch set signal SET2 among the latch control signals for controlling the second latch 140. The twentieth transistor T20 may be implemented as an NMOS transistor.

[0058] In an embodiment, the data latch 150 may store data read from the memory cell.

[0059] Figure 2 is a diagram showing the threshold voltage regions of a memory cell according to an embodiment of the present disclosure. Figure 2The horizontal axis of the graph shown in can represent the magnitude of the potential difference in volts, and the vertical axis of the graph can represent the number of memory cells.

[0060] Referring to Figure 2 , after applying a programming voltage, each memory cell can correspond to any one of a plurality of threshold voltage regions AREA1 to AREA4. The memory cells can be slow cells or fast cells. When the same programming voltage is applied to slow cells and fast cells, the change in the threshold voltage of the fast cells can be greater than the change in the threshold voltage of the slow cells. Therefore, the threshold voltage region containing the memory cells can vary depending on whether the memory cells are slow cells or fast cells.

[0061] In an embodiment, a plurality of threshold voltage regions AREA1 to AREA4 can be divided based on a plurality of reference voltages Vref1 to Vref3. The first threshold voltage region AREA1 can be a region below the first reference voltage Vref1. The second threshold voltage region AREA2 can be a region above the first reference voltage Vref1 and below the second reference voltage Vref2. The third threshold voltage region AREA3 can be a region above the second reference voltage Vref2 and below the third reference voltage Vref3. The fourth threshold voltage region AREA4 can be a region above the third reference voltage Vref3.

[0062] In an embodiment, the verification operation can be performed based on a triple verification method. For example, the verification operation can consist of three verification operations, and the threshold voltage region containing the memory cells among the plurality of threshold voltage regions AREA1 to AREA4 can be determined by the three verification operations. Examples of performing the verification operation will be described in detail later with reference to Figure 3 and Figure 4 .

[0063] In an embodiment, when a memory cell is included in the fourth threshold voltage region, it can be determined that the memory cell has passed the verification operation (i.e., verification passed). Conversely, when the memory cell is not included in the fourth threshold voltage region, it can be determined that the memory cell has not passed the verification operation, and the next programming cycle can be executed.

[0064] During the programming voltage application operation in the next programming cycle after the verification operation, the voltage to be applied to the bit line can be determined based on the threshold voltage region containing the memory cell. This will be described in detail later with reference to Figures 6 to 11 .

[0065] Figure 3 is a diagram showing an example of performing a triple verification programming operation according to an embodiment of the present disclosure. Figure 3The horizontal axis of the curve shown may represent time in seconds S, and the vertical axis of the curve may represent the magnitude of the potential difference in volts.

[0066] Referring to Figure 1 and Figure 3 , the programming operation may include a plurality of programming cycles PL1 to PLn. Each of the selected memory cells may be programmed through the plurality of programming cycles PL1 to PLn to have a threshold voltage corresponding to any one of the plurality of programming states.

[0067] Each of the plurality of programming cycles PL1 to PLn may include a programming voltage application operation (PGM operation) for applying a programming voltage and a verification operation for applying a verification voltage and verifying whether the memory cell is programmed.

[0068] For example, when the first programming cycle PL1 is executed, after applying the first programming voltage in the programming voltage application operation (PGM operation), the verification voltage may be sequentially applied in the verification operation to verify the programming states of the plurality of memory cells.

[0069] The memory cells that pass the verification operation by the corresponding verification voltage may be determined to have the target programming state and then may be prohibited from being programmed in the subsequent second programming cycle PL2. In order to program the remaining memory cells other than the memory cells prohibited from programming in the second programming cycle PL2, a second programming voltage higher than the first programming voltage by a unit (step) voltage may be applied. Thereafter, the verification operation may be performed in the same manner as the verification operation performed in the first programming cycle PL1. In the example, the term "verification passed" may indicate that the memory cell is read as a cut-off cell by the corresponding verification voltage.

[0070] During the programming voltage application operation (PGM operation), when a programming voltage is applied to the selected word line, the page buffer 100 may transfer the data received through the input / output circuit to the selected memory cell through the bit line BL. The memory cells in the selected page may be programmed based on the transferred data. The threshold voltage of the memory cell connected to the bit line BL to which a programming enable voltage (e.g., ground voltage or a voltage higher than the ground voltage) is applied may be increased. The threshold voltage of the memory cell connected to the bit line BL to which a programming prohibition voltage (e.g., power supply voltage) is applied may remain unchanged.

[0071] During the verification operation, the verification voltage may be applied to the selected word line connected to the selected memory cell, and the page buffer 100 may sense the current or voltage flowing through the bit line BL connected to the selected memory block, respectively.

[0072] For example, the page buffer 100 may store the state of the memory cell according to the voltage of the corresponding bit line BL. Here, the state of the memory cell may be a state corresponding to any one of "verification passed" and "verification failed". When the threshold voltage of the memory cell is higher than the verification voltage applied to the selected word line, the memory cell may be read as a cutoff cell, and the memory cell read as a cutoff cell may correspond to a passed state. On the other hand, when the threshold voltage of the memory cell is lower than the verification voltage applied to the selected word line, the memory cell may be read as a conducting cell, and the memory cell read as a conducting cell may correspond to a failed state.

[0073] In an embodiment, according to the triple verification programming method, the verification operation may include a first verification operation based on a first evaluation operation, a second verification operation based on a second evaluation operation, and a third verification operation based on a third evaluation operation. Here, each of the first verification operation, the second verification operation, and the third verification operation may include a precharge operation, an evaluation operation, and a sensing operation.

[0074] The precharge operation may be an operation of precharging the bit line BL and the sense node SO.

[0075] In an embodiment, the bit line voltage control circuit 110 may precharge the bit line BL. In addition, the sense node voltage control circuit 120 may precharge the sense node SO when the bit line BL is precharged.

[0076] The evaluation operation may be an operation of evaluating the threshold voltage of the memory cell according to the voltage or current of the bit line BL. The evaluation time of the evaluation operation may be set to the time when the threshold voltage of the memory cell can be reflected in the bit line BL.

[0077] In an embodiment, the first evaluation operation may be performed based on the first evaluation time tEV1. The second evaluation operation may be performed based on a second evaluation time tEV2 longer than the first evaluation time tEV1. The third evaluation operation may be performed based on a third evaluation time tEV3 longer than the second evaluation time tEV2.

[0078] The sensing operation can be the following operation: sensing data based on the voltage or current of the bit line BL when a verification voltage is applied to the memory cell, and storing the sensed data in the first latch 130 and the second latch 140 of the page buffer 100. For example, when the change in the voltage or current of the bit line BL is reflected in the sense node SO, the first latch 130 can store the first bit value LC1 among a plurality of bit values corresponding to the voltage level of the sense node SO in response to the latch control signal, and the second latch 140 can store the second bit value LC2 among a plurality of bit values corresponding to the voltage level of the sense node SO in response to the latch control signal.

[0079] In an embodiment, the bit line BL and the sense node SO can be precharged. Thereafter, a first evaluation operation can be performed during a first evaluation time tEV1 starting from the time point when the precharging of the sense node SO is completed. Thereafter, the first latch 130 can store the first bit value LC1 determined based on the first evaluation operation. For example, the first latch 130 can store the first bit value LC1 determined based on the first evaluation operation in response to the first latch reset signal RST1 after the first evaluation operation is completed.

[0080] In addition, the sense node voltage control circuit 120 can recharge the sense node SO after the first bit value LC1 is stored in the first latch 130. Thereafter, a second evaluation operation can be performed during a second evaluation time tEV2 starting from the time point when the re-precharging of the sense node SO is completed after the first bit value LC1 is stored in the first latch 130. Thereafter, the second latch 140 can store the second bit value LC2 determined based on the second evaluation operation. For example, the second latch 140 can store the second bit value LC2 determined based on the second evaluation operation in response to the second latch reset signal RST2 after the second evaluation operation is completed.

[0081] In addition, the sense node voltage control circuit 120 can recharge the sense node SO after the second bit value LC2 is stored in the second latch 140. Thereafter, a third evaluation operation can be performed during a third evaluation time tEV3 starting from the time point when the re-precharging of the sense node SO is completed after the second bit value LC2 is stored in the second latch 140. Thereafter, the first latch 130 can store the first bit value LC1 determined based on the third evaluation operation. For example, the first latch 130 can store the first bit value LC1 determined based on the third evaluation operation in response to the first latch set signal SET1 after the third evaluation operation is completed.

[0082] Figure 4 It is a diagram showing an example of performing a triple verification programming operation according to an embodiment of the present disclosure.Figure 4 The horizontal axis of the graph shown in can represent time in seconds S, and the vertical axis of the graph can represent the magnitude of the potential difference in volts. Specifically, compared with Figure 3 the triple verification programming operation shown, Figure 4 the triple verification programming operation shown is configured to perform only one pre-charge operation.

[0083] Referring to Figure 1 and Figure 4 , in an embodiment, the bit line BL and the sense node SO can be pre-charged. Thereafter, a first evaluation operation can be performed during a first evaluation time tEV1 starting from the time point when the pre-charge of the sense node SO is completed. Thereafter, the first latch 130 can store a first bit value LC1 determined based on the first evaluation operation. For example, the first latch 130 can store the first bit value LC1 determined based on the first evaluation operation in response to a first latch reset signal RST1 after the first evaluation operation is completed.

[0084] In addition, a second evaluation operation can be performed during a second evaluation time tEV2 starting from the time point when the pre-charge of the sense node SO is completed. Thereafter, the second latch 140 can store a second bit value LC2 determined based on the second evaluation operation. For example, the second latch 140 can store the second bit value LC2 determined based on the second evaluation operation in response to a second latch reset signal RST2 after the second evaluation operation is completed.

[0085] In addition, a third evaluation operation can be performed during a third evaluation time tEV3 starting from the time point when the pre-charge of the sense node SO is completed. Thereafter, the first latch 130 can store a first bit value LC1 determined based on the third evaluation operation. For example, the first latch 130 can store the first bit value LC1 determined based on the third evaluation operation in response to a first latch set signal SET1 after the third evaluation operation is completed.

[0086] Figure 5 is a diagram showing bit values stored in the first latch and the second latch based on a triple verification programming operation according to an embodiment of the present disclosure.

[0087] Referring to Figure 1 , Figure 2 and Figure 5 , the first latch status information Latch Status1 can be status information indicating the bit values stored in the first latch 130 and the second latch 140 after performing the first evaluation operation and the sense operation based on the first evaluation operation.

[0088] In an embodiment, before performing an evaluation operation, page buffer 100 may store an initial logic value in first latch 130 and second latch 140. Here, the initial logic value may indicate '1'. In an embodiment, the first logic value may be the initial logic value indicating '1', and the second logic value may indicate the inverted value '0' of the first logic value.

[0089] For example, first latch 130 and second latch 140 may turn off ninth transistor T9, twelfth transistor T12, fifteenth transistor T15, and eighteenth transistor T18. In addition, sense node voltage control circuit 120 may pre-charge sense node SO to have a high voltage level. In addition, first latch 130 and second latch 140 may store the first bit value and the second bit value as '1', i.e., the initial logic value, in response to first latch set signal SET1 and second latch set signal SET2.

[0090] On the other hand, in this specification, it is assumed that the initial logic value is '1', but the present disclosure is not limited thereto. According to an embodiment, the first logic value as the initial logic value may indicate '0', and the second logic value may indicate '1'.

[0091] In an embodiment, when the memory cell is included in the first threshold voltage region AREA1, the first bit value LC1 may be maintained as the first logic value as the initial logic value according to the sense operation based on the first evaluation operation. In contrast, when the memory cell is included in any one of the second threshold voltage region AREA2, the third threshold voltage region AREA3, and the fourth threshold voltage region AREA4, the first bit value LC1 may change from the first logic value to the second logic value according to the sense operation based on the first evaluation operation.

[0092] The second latch status information Latch Status2 may be status information indicating the bit values stored in first latch 130 and second latch 140 after performing the second evaluation operation and the sense operation based on the second evaluation operation.

[0093] In an embodiment, when the memory cell is included in any one of the first threshold voltage region AREA1 and the second threshold voltage region AREA2, the second bit value LC2 may be maintained as the first logic value as the initial logic value according to the sense operation based on the second evaluation operation. In contrast, when the memory cell is included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4, the second bit value LC2 may change from the first logic value to the second logic value according to the sense operation based on the second evaluation operation.

[0094] The third latch status information Latch Status3 may be status information indicating the bit values stored in the first latch 130 and the second latch 140 after performing a third evaluation operation and a sensing operation based on the third evaluation operation.

[0095] In an embodiment, when the memory cell is included in any one of a first threshold voltage region AREA1, a second threshold voltage region AREA2, and a third threshold voltage region AREA3, the first bit value LC1 may be maintained as a previous logic value according to a sensing operation based on the third evaluation operation. For example, when the memory cell is included in the first threshold voltage region AREA1, the first bit value LC1 may correspond to a first logic value. In addition, when the memory cell is included in any one of the second threshold voltage region AREA2 and the third threshold voltage region AREA3, the first bit value LC1 may correspond to a second logic value. Conversely, when the memory cell is included in a fourth threshold voltage region AREA4, the first bit value LC1 may change from the second logic value to the first logic value according to a sensing operation based on the third evaluation operation.

[0096] In an embodiment, when, according to the third latch status information Latch Status3, the first bit value LC1 corresponds to a first logic value and the second bit value LC2 corresponds to a second logic value, the memory cell may be included in the fourth threshold voltage region to pass a verification operation. In this case, the data latch 150 may store data indicating whether the verification operation has passed. Accordingly, the corresponding memory cell may be set as a programming prohibited cell.

[0097] Figure 6 is a timing diagram showing a bit line setting operation according to an embodiment of the present disclosure.

[0098] Referring to Figure 1 and Figure 6 , the bit line voltage control circuit 110 may control the voltage applied to the bit line BL during a programming voltage application operation after a verification operation based on the first bit value LC1 and the second bit value LC2. For example, the bit line voltage control circuit 110 may apply any one of a ground voltage GND, a first programming enable voltage, a second programming enable voltage, and a programming prohibited voltage to the bit line BL according to whether each of the first bit value LC1 and the second bit value LC2 corresponds to any one of a first logic value and a second logic value.

[0099] The first programming enable voltage may be a voltage corresponding to a first bit line voltage control signal BLT and may be higher than the ground voltage GND. For example, the first programming enable voltage may be represented by the difference between a voltage VREFT applied to the fourth transistor T4 in response to the first bit line voltage control signal BLT and the threshold voltage VTH of the fourth transistor T4.

[0100] The second programming enable voltage can be a voltage corresponding to the second bit line voltage control signal BLD, and can be higher than the first programming enable voltage. For example, the second programming enable voltage can be represented by the difference between the voltage VREFD applied to the seventh transistor T7 in response to the second bit line voltage control signal BLD and the threshold voltage VTH of the seventh transistor T7.

[0101] The programming inhibit voltage can be a voltage corresponding to the third bit line voltage control signal BLM, and can be higher than the second programming enable voltage. For example, the programming inhibit voltage can indicate the power supply voltage VCC applied to the eighth transistor T8 in response to the third bit line voltage control signal BLM.

[0102] The following will refer to Figure 7 、 Figure 9 and Figure 11 to describe the signals corresponding to the respective time points shown in Figure 6 .

[0103] Figure 7 is a diagram showing an example of controlling the bit line voltage of a memory cell included in the fourth threshold voltage region according to an embodiment of the present disclosure.

[0104] Referring to Figure 5 、 6 and 7, when the memory cell is included in the fourth threshold voltage region AREA4, according to the third latch status information Latch Status3, the first bit value LC1 can correspond to the first logical value, and the second bit value LC2 can correspond to the second logical value.

[0105] During time periods T1 to T3, the bit line voltage control circuit 110 can apply the programming inhibit voltage corresponding to the third bit line voltage control signal BLM to the bit line BL by turning on the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8.

[0106] For example, during time periods T1 to T2, the first transistor T1 can receive the voltage VON in response to the page buffer sense signal PBS, and connect the bit line BL to the common sense node CSO.

[0107] The second transistor T2 can receive the voltage VON in response to the sense node sense signal TRANSO, and connect the common sense node CSO to the sense node SO.

[0108] When the second bit value LC2 corresponds to the second logical value, the fifth transistor T5 can transfer the power supply voltage VCC to the sixth transistor T6.

[0109] Since the first inverted bit value LC1B corresponds to the second logic value when the first bit value LC1 corresponds to the first logic value, the sixth transistor T6 can transfer the power supply voltage VCC received from the fifth transistor T5 to the eighth transistor T8.

[0110] The eighth transistor T8 can receive the power supply voltage VCC in response to the third bit line voltage control signal BLM and transfer the power supply voltage VCC to the sense node SO.

[0111] Therefore, the bit line voltage control circuit 110 can apply the power supply voltage VCC corresponding to the programming inhibit voltage to the bit line BL through path ①.

[0112] In addition, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be turned off.

[0113] On the other hand, the twelfth transistor T12 and the fifteenth transistor T15 can be turned on in response to the second latch connection signal TL2 and the third latch connection signal TL3, and the ninth transistor T9 and the eighteenth transistor T18 can be turned off in response to the first latch connection signal TL1 and the fourth latch connection signal TL4.

[0114] In this case, when the memory cell is included in the fourth threshold voltage region AREA4, the thirteenth transistor T13 and the sixteenth transistor T16 can be turned off by receiving a low-level signal according to the third latch status information Latch Status3. Therefore, the ground voltage GND connected to the thirteenth transistor T13 and the sixteenth transistor T16 may not be transferred to the sense node SO, and the programming inhibit voltage can be applied to the bit line BL through path ①.

[0115] In contrast, when the memory cell is included in any one of the first threshold voltage region AREA1, the second threshold voltage region AREA2, and the third threshold voltage region AREA3, at least one of the thirteenth transistor T13 and the sixteenth transistor T16 can be turned on by receiving a high-level signal. Therefore, the sense node SO can receive the ground voltage GND through at least one of the thirteenth transistor T13 and the sixteenth transistor T16, and the ground voltage GND can be applied to the bit line BL through the sense node SO.

[0116] During the time period T2 to T3, the second transistor T2 can receive the ground voltage GND in response to the sense node sense signal TRANSO and can disconnect the common sense node CSO from the sense node SO.

[0117] The twelfth transistor T12 and the fifteenth transistor T15 can be turned off in response to the second latch connection signal TL2 and the third latch connection signal TL3.

[0118] Figure 8 is a diagram showing an example of changing a bit value stored in a first latch before controlling a bit line voltage of a memory cell included in a third threshold voltage region according to an embodiment of the present disclosure. Although Figure 6 not shown in Figure 8 the example shown in Figure 7 can be performed after controlling the bit line voltage of the memory cell included in the fourth threshold voltage region AREA4 described above with reference to

[0119] Referring to Figure 1 and Figure 8 , before controlling the bit line voltage of the memory cell included in the third threshold voltage region AREA3, the page buffer 100 corresponding to the memory cell included in the third threshold voltage region AREA3 may change the first bit value LC1 stored in the first latch 130.

[0120] For example, the sense node voltage control circuit 120 may pre-charge the sense node SO to a high level. In addition, the second latch 140 may turn on the fifteenth transistor T15. The ninth transistor T9, the twelfth transistor T12, and the eighteenth transistor T18 may be turned off.

[0121] Here, in the case of the page buffer 100 in which the memory cell is included in any one of the first threshold voltage region AREA1 and the second threshold voltage region AREA2, the sixteenth transistor T16 may be turned on by receiving a high level signal, so that the sense node SO may be discharged through the ground voltage GND.

[0122] In contrast, in the case of the page buffer 100 in which the memory cell is included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4, the sixteenth transistor T16 may be turned off by receiving a low level signal. Since the ground voltage GND connected to the sixteenth transistor T16 is not transmitted to the sense node SO, the sense node SO may be maintained at a high level. In this case, when the first latch set signal SET1 is activated to a high level, the page buffer 100 in which the memory cell is included in the third threshold voltage region AREA3 may operate such that the first bit value LC1 becomes a first logic value. In the case of the page buffer 100 in which the memory cell is included in the fourth threshold voltage region AREA4, the first bit value LC1 may be maintained as the first logic value.

[0123] The fourth latch status information, Latch Status4, may be status information indicating the status of the bit values stored in the first latch 130 and the second latch 140 after the page buffer 100 in which the memory cell is included in the third threshold voltage region AREA3 changes the first bit value LC1 to the first logic value.

[0124] Figure 9 FIG. is a diagram illustrating an example of controlling a bit line voltage of a memory cell included in a third threshold voltage region according to an embodiment of the present disclosure.

[0125] Referring to Figure 6 、 Figure 8 and Figure 9 , when the memory cell is included in the third threshold voltage region AREA3, according to the fourth latch status information Latch Status4, the first bit value LC1 may correspond to the first logic value, and the second bit value LC2 may correspond to the second logic value.

[0126] During time periods T3 to T4, the bit line voltage control circuit 110 may apply a second programming enable voltage corresponding to the second bit line voltage control signal BLD to the bit line BL by turning on the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0127] For example, the first transistor T1 may receive the voltage VON in response to the page buffer sense signal PBS and connect the bit line BL to the common sense node CSO.

[0128] When the second bit value LC2 corresponds to the second logic value, the fifth transistor T5 may transfer the power supply voltage VCC to the sixth transistor T6.

[0129] Since when the first bit value LC1 corresponds to the first logic value, the first inverted bit value LC1B corresponds to the second logic value, the sixth transistor T6 may transfer the power supply voltage VCC received from the fifth transistor T5 to the seventh transistor T7.

[0130] The seventh transistor T7 may receive the voltage VREFD in response to the second bit line voltage control signal BLD and transfer the voltage VREFD to the common sense node CSO.

[0131] Therefore, the bit line voltage control circuit 110 may apply a voltage VREFD-VTH corresponding to the second programming enable voltage to the bit line BL through path ②.

[0132] In addition, the third transistor T3, the fourth transistor T4, and the eighth transistor T8 may be turned off.

[0133] On the other hand, the second transistor T2 can receive the voltage VON in response to the sense node sense signal TRANSO and connect the common sense node CSO to the sense node SO. The fifteenth transistor T15 can be turned on in response to the third latch connection signal TL3, and the ninth transistor T9, the twelfth transistor T12, and the eighteenth transistor T18 can be turned off in response to the first latch connection signal TL1, the second latch connection signal TL2, and the fourth latch connection signal TL4.

[0134] In this case, when the memory cell is included in either the third threshold voltage region AREA3 or the fourth threshold voltage region AREA4, the sixteenth transistor T16 can be turned off by receiving a low-level signal according to the fourth latch status information LatchStatus4. Therefore, the ground voltage GND connected to the sixteenth transistor T16 may not be transmitted to the sense node SO, and the second programming enable voltage can be applied to the bit line BL through path ②. When the memory cell is included in the fourth threshold voltage region AREA4, a programming prohibition voltage higher than the second programming enable voltage is applied to the bit line BL, so that the bit line BL can be maintained at the programming prohibition voltage.

[0135] In contrast, when the memory cell is included in either the first threshold voltage region AREA1 or the second threshold voltage region AREA2, the sixteenth transistor T16 can be turned on by receiving a high-level signal. Therefore, the sense node SO can receive the ground voltage GND through the sixteenth transistor T16, and the ground voltage GND can be applied to the bit line BL through the sense node SO.

[0136] Figure 10 is a diagram showing an example of changing the bit value stored in the first latch before controlling the bit line voltage of the memory cell included in either the first threshold voltage region or the second threshold voltage region according to an embodiment of the present disclosure. Although Figure 6 not shown in Figure 10 the example shown in Figure 8 can be performed after controlling the bit line voltage of the memory cell included in the third threshold voltage region AREA3 described above with reference to

[0137] In addition, Figure 10 the example shown in Figure 6 can be performed within a short time (e.g., 1 to 2 μs) before T4 of Figure 6 . For example, although Figure 10 not shown in

[0138] a ground voltage GND can be applied in response to the sense node sense signal TRANSO within a short time before T4, and the operations described with reference toFigure 1 and Figure 10 Before controlling the bit line voltage of the memory cells included in any one of the first threshold voltage region AREA1 and the second threshold voltage region AREA2, the page buffer 100 corresponding to the memory cells included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4 may change the first bit value LC1 stored in the first latch 130.

[0139] For example, the sense node voltage control circuit 120 may pre-charge the sense node SO to a high level. In addition, the second latch 140 may turn on the fifteenth transistor T15. The ninth transistor T9, the twelfth transistor T12, and the eighteenth transistor T18 may be turned off.

[0140] Here, in the case of the page buffer 100 in which the memory cells are included in any one of the first threshold voltage region AREA1 and the second threshold voltage region AREA2, the sixteenth transistor T16 may be turned on by receiving a high level signal, so that the sense node SO may be discharged through the ground voltage GND.

[0141] In contrast, in the case of the page buffer 100 in which the memory cells are included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4, the sixteenth transistor T16 may be turned off by receiving a low level signal. Since the ground voltage GND connected to the sixteenth transistor T16 is not transmitted to the sense node SO, the sense node SO may be maintained at a high level. In this case, when the first latch reset signal RST1 is activated to a high level, the page buffer 100 in which the memory cells are included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4 may operate such that the first bit value LC1 becomes a second logic value.

[0142] The fifth latch status information Latch Status5 may be status information indicating the bit values stored in the first latch 130 and the second latch 140 after the page buffer 100 in which the memory cells are included in any one of the third threshold voltage region AREA3 and the fourth threshold voltage region AREA4 changes the first bit value LC1 to a second logic value.

[0143] Figure 11 is a diagram showing an example of controlling the bit line voltage of the memory cells included in any one of the first threshold voltage region and the second threshold voltage region according to an embodiment of the present disclosure.

[0144] Refer to Figure 6 、 10When the memory cell is included in the second threshold voltage region AREA2, according to the fifth latch status information Latch Status5, the first bit value LC1 may correspond to the second logic value, and the second bit value LC2 may correspond to the first logic value.

[0145] During the time period T4 to T5, the bit line voltage control circuit 110 may apply a first programming enable voltage corresponding to the first bit line voltage control signal BLT to the bit line BL by turning on the first transistor T1, the third transistor T3, and the fourth transistor T4.

[0146] For example, the first transistor T1 may receive the voltage VON in response to the page buffer sense signal PBS and connect the bit line BL to the common sense node CSO.

[0147] When the first bit value LC1 corresponds to the second logic value, the third transistor T3 may transfer the power supply voltage VCC to the fourth transistor T4.

[0148] The fourth transistor T4 may receive the voltage VREFT in response to the first bit line voltage control signal BLT and transfer the voltage VREFT to the common sense node CSO.

[0149] Therefore, the bit line voltage control circuit 110 may apply a voltage VREFT - VTH corresponding to the first programming enable voltage to the bit line BL through path ③.

[0150] In addition, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be turned off.

[0151] On the other hand, the second transistor T2 may receive the voltage VON in response to the sense node sense signal TRANSO and connect the common sense node CSO to the sense node SO. The ninth transistor T9 may be turned on in response to the first latch connection signal TL1, and the twelfth transistor T12, the fifteenth transistor T15, and the eighteenth transistor T18 may be turned off in response to the second latch connection signal TL2, the third latch connection signal TL3, and the fourth latch connection signal TL4.

[0152] In this case, when the memory cell is included in any one of the first threshold voltage region AREA1, the third threshold voltage region AREA3, and the fourth threshold voltage region AREA4, the ninth transistor T9 can be turned off by receiving a low-level signal according to the fifth latch status information Latch Status5. Therefore, the ground voltage GND connected to the ninth transistor T9 may not be transmitted to the sense node SO, and the first programming enable voltage can be applied to the bit line BL through path ③. When the memory cell is included in the third threshold voltage region AREA3 or the fourth threshold voltage region AREA4, a second programming enable voltage or a programming inhibit voltage higher than the first programming enable voltage is applied to the bit line BL, so that the bit line BL can be held at the second programming enable voltage or the programming inhibit voltage.

[0153] In contrast, when the memory cell is included in the first threshold voltage region AREA1, the ninth transistor T9 can be turned on by receiving a high-level signal. Therefore, the sense node SO can receive the ground voltage GND through the ninth transistor T9. In addition, the third transistor T3 and the fifth transistor T5 can be turned off, so that the supply of the power voltage connected to the third transistor T3 and the fifth transistor T5 can be interrupted. Therefore, the ground voltage GND can be applied to the bit line BL through path ④.

[0154] Figure 12 is a diagram showing an example of a page buffer according to an embodiment of the present disclosure.

[0155] Referring to Figure 12 , compared with the page buffer 100 of Figure 1 , the page buffer 200 can be configured such that the third transistor T3 is implemented as an NMOS transistor. Therefore, when the first bit value LC1 corresponds to the first logical value, the third transistor T3 can transmit the power voltage VCC to the fourth transistor T4.

[0156] On the other hand, in an embodiment, when the third transistor T3 is implemented as an NMOS transistor, the third transistor T3 and the fourth transistor T4 can share a source-drain region without using a separate n-well, and the overall size of the page buffer 200 can be reduced.

[0157] In addition, in an embodiment, the sense node voltage control circuit 120 can be connected to the sense node SO. Therefore, in an embodiment, the sense node voltage control circuit 120 can provide a precharge voltage to the sense node SO without passing through the eighth transistor T8.

[0158] Except for the above differences, the descriptions made above with reference to Figures 1 to 11 can equally apply to the remaining components and their operation methods.

[0159] Figure 13 is a diagram showing a method of performing a triple verification programming operation according to an embodiment of the present disclosure. Figure 13 The method shown can be performed by, for example, Figure 1 the page buffer 100 shown. In an embodiment, Figure 13 the method shown can be performed by, for example, Figure 12 the page buffer 200 shown.

[0160] Referring to Figure 13 , in step S1301, the page buffer 100 can pre-charge the bit line BL and the sense node SO.

[0161] In step S1303, the page buffer 100 can perform a first evaluation operation based on a first evaluation time.

[0162] In step S1305, the page buffer 100 can store a first bit value LC1 determined based on the first evaluation operation in the first latch 130.

[0163] In step S1307, the page buffer 100 can perform a second evaluation operation based on a second evaluation time.

[0164] In step S1309, the page buffer 100 can store a second bit value LC2 determined based on the second evaluation operation in the second latch 140.

[0165] In step S1311, the page buffer 100 can perform a third evaluation operation based on a third evaluation time.

[0166] In step S1313, the page buffer 100 can store the first bit value LC1 determined based on the third evaluation operation in the first latch 130.

[0167] In step S1315, the page buffer 100 can determine whether the verification operation passes based on the first bit value LC1 determined based on the third evaluation operation and the second bit value LC2 determined based on the second evaluation operation.

[0168] In step S1317, the page buffer 100 can control the voltage applied to the bit line BL based on the first bit value LC1 determined based on the third evaluation operation and the second bit value LC2 determined based on the second evaluation operation.

[0169] Figure 14 is a diagram showing a memory device according to an embodiment of the present disclosure.

[0170] Referring to Figure 14, the memory device 1000 may include a memory cell array 1100, a peripheral circuit 1200, and a control logic 1300. The control logic 1300 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 1300 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0171] The memory cell array 1100 includes a plurality of memory blocks BLK1 to BLKz.

[0172] The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 1210 through row lines RL. Here, the row lines RL may include at least one source selection line SSL, a plurality of word lines WL1 to WLm, and at least one drain selection line DSL.

[0173] Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells MC1 to MCm. The plurality of memory cells MC1 to MCm may be connected to a page buffer group 1230 through a plurality of bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cell strings ST connected between the bit lines BL1 to BLm and a source line SL. Each of the memory cell strings ST may include at least one source selection transistor SST, a plurality of memory cells MC1 to MCm, and at least one drain selection transistor DST connected in series between the source line SL and a corresponding one of the bit lines BL1 to BLm.

[0174] Memory cells connected to the same word line may be defined as one page PG. Each of the memory cells MC1 to MCm may store a plurality of data bits.

[0175] The peripheral circuit 1200 may perform a programming operation, a read operation, or an erase operation on a selected area of the memory cell array 1100 under the control of the control logic 1300.

[0176] The peripheral circuit 1200 may include a row decoder 1210, a voltage generator 1220, a page buffer group 1230, a column decoder 1240, an input / output circuit 1250, and a sensing circuit 1260.

[0177] The row decoder 1210 may decode a row address RADD received from the control logic 1300. The row decoder 1210 selects at least one of the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 1210 may select at least one word line of the selected memory block according to the decoded address. The row decoder 1210 may apply a voltage Vop generated by the voltage generator 1220 to the selected word line.

[0178] The voltage generator 1220 can generate multiple voltages using an external power supply voltage provided to the memory device 1000. For example, the voltage generator 1220 can generate various operation voltages Vop for programming operations, read operations, and erase operations in response to an operation signal OPSIG. The multiple generated voltages Vop can be provided by the row decoder 1210 to the memory cell array 1100.

[0179] The page buffer group 1230 can include multiple page buffers PB1 to PBm. Figure 1 and Figure 12 Each of the page buffers 100 and 200 shown in can correspond to any one of the multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm can store data received through multiple bit lines BL1 to BLm in response to page buffer control signals PBSIGNALS, or sense the voltage or current of the multiple bit lines BL1 to BLm during read or verify operations.

[0180] Each of the multiple page buffers PB1 to PBm can include a first latch and a second latch. The first latch stores a first bit value among multiple bit values indicating the threshold voltage region of a selected memory cell, and the second latch stores a second bit value among the multiple bit values.

[0181] The column decoder 1240 can transfer data between the input / output circuit 1250 and the page buffer group 1230 in response to a column address CADD.

[0182] The input / output circuit 1250 can send a command CMD and an address ADDR received from a memory controller (not shown) to the control logic 1300, or can exchange data DATA with the column decoder 1240.

[0183] The sense circuit 1260 can determine whether a verify operation for a specific programming state passes by applying a verify voltage.

[0184] In an example, during a verify operation, the sense circuit 1260 can generate a reference current in response to an enable bit signal VRYBIT, and can compare a sense voltage VPB received from the page buffer group 1230 with a reference voltage generated by the reference current, and then output a pass signal PASS or a fail signal FAIL. In an example, during a verify operation, the sense circuit 1260 can generate a reference voltage in response to an enable bit signal VRYBIT, and can compare a sense current IPB received from the page buffer group 1230 with a reference current generated by the reference voltage, and then output a pass signal PASS or a fail signal FAIL.

[0185] The control logic 1300 may control the peripheral circuit 1200 by outputting an operation signal OPSIG, a row address RADD, and page buffer control signals PBSIGNALS in response to a command CMD and an address ADDR.

[0186] In an embodiment, the control logic 1300 may include a programming operation controller 1310.

[0187] The programming operation controller 1310 may control the programming operation of the memory device 1000. For example, the programming operation controller 1310 may provide an operation signal OPSIG for controlling the generation of a programming voltage and a verification voltage to the voltage generator 1220, and may generate a row address RADD by decoding the address ADDR of the word line of the data DATA to be stored.

[0188] In an embodiment, the programming operation controller 1310 may determine whether a verification operation passes based on whether the first bit value and the second bit value stored in each of the plurality of page buffers PB1 to PBm correspond to a first logic value or a second logic value.

[0189] In an embodiment, the programming operation controller 1310 may control the voltage applied to the plurality of bit lines BL1 to BLm during a programming voltage application operation based on whether the first bit value and the second bit value stored in each of the plurality of page buffers PB1 to PBm correspond to a first logic value or a second logic value.

[0190] According to an embodiment of the present disclosure, there are provided a page buffer, a memory device including the page buffer, and a method of operating the page buffer, which may improve the threshold voltage distribution of memory cells and reduce the circuit size.

Claims

1. A page buffer, the page buffer being connected to a memory cell via a bit line, the page buffer comprising: a sensing node connected to the bit line; a bit line voltage control circuit to precharge the bit line during a verify operation; a sensing node voltage controller, configured to precharge the sensing node when the bit line is precharged; a first latch connected to the sensing node and storing a first bit value determined based on a first evaluation operation among a plurality of bit values ​​corresponding to a voltage level of the sensing node after the sensing node is precharged; as well as a second latch connected to the sensing node and storing a second bit value determined based on a second evaluation operation among the plurality of bit values ​​after the first bit value is stored in the first latch, The first latch stores a first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.

2. The page buffer according to claim 1, wherein: The verification operation is performed based on a triple verification programming method including a first verification operation based on the first evaluation operation, a second verification operation based on the second evaluation operation, and a third verification operation based on the third evaluation operation.

3. The page buffer according to claim 1, wherein: performing the first evaluation operation based on a first evaluation time, performing the second evaluation operation based on a second evaluation time that is longer than the first evaluation time, and The third evaluation operation is performed based on a third evaluation time that is longer than the second evaluation time.

4. The page buffer according to claim 3, wherein: The sense node voltage control circuit re-precharges the sense node after the first bit value is stored and the second bit value is stored.

5. The page buffer according to claim 4, wherein: The first evaluation operation is performed during a first evaluation time starting from a time point when precharging of the sensing node is completed, The second evaluation operation is performed during a second evaluation time starting from a time point when re-precharging of the sensing node is completed after the first bit value is stored, and The third evaluation operation is performed during a third evaluation time starting from a time point when re-precharging of the sense node is completed after the second bit value is stored.

6. The page buffer according to claim 3, wherein: The first evaluation operation is performed during a first evaluation time starting from a time point when precharging of the sensing node is completed, The second evaluation operation is performed during a second evaluation time starting from a time point when precharging of the sensing node is completed, and The third evaluation operation is performed during a third evaluation time starting from a time point when precharging of the sensing node is completed.

7. The page buffer according to claim 1, wherein: The first latch: After the first evaluation operation is completed, storing a first bit value determined based on the first evaluation operation in response to a first latch control signal for controlling the first latch, and After the third evaluation operation is completed, a first bit value determined based on the third evaluation operation is stored in response to a second latch control signal for controlling the first latch.

8. The page buffer according to claim 1, wherein: After the second evaluation operation is completed, the second latch stores a second bit value determined based on the second evaluation operation in response to a third latch control signal for controlling the second latch.

9. The page buffer according to claim 1, wherein: The first latch and the second latch store a first logic value, which is an initial logic value before the first evaluation operation is performed.

10. The page buffer according to claim 9, wherein: During a program voltage applying operation performed after the verification operation, the bit line voltage control circuit applies any one of a ground voltage, a first program enable voltage higher than the ground voltage, a second program enable voltage higher than the first program enable voltage, and a program inhibit voltage higher than the second program enable voltage to the bit line according to whether each of the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation corresponds to any one of the first logic value and a second logic value which is an inversion value of the first logic value.

11. The page buffer according to claim 10, wherein: The bit line voltage control circuit applies the ground voltage to the bit line when the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation correspond to the first logic value.

12. The page buffer according to claim 10, wherein: The bit line voltage control circuit applies the first program enable voltage to the bit line when the first bit value determined based on the third evaluation operation corresponds to the second logic value and the second bit value determined based on the second evaluation operation corresponds to the first logic value.

13. The page buffer according to claim 10, wherein: The bit line voltage control circuit applies the second program enable voltage to the bit line when the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation correspond to the second logic value.

14. The page buffer according to claim 10, wherein: The bit line voltage control circuit applies the program inhibition voltage to the bit line when the first bit value determined based on the third evaluation operation corresponds to the first logic value and the second bit value determined based on the second evaluation operation corresponds to the second logic value. 15 . The page buffer of claim 14 , further comprising a data latch storing data indicating whether the verification operation is passed.

16. A memory device comprising: a memory cell included in any one of a plurality of threshold voltage regions divided by a plurality of reference voltages according to a programming operation; a page buffer connected to the memory cell via a bit line; as well as a programming operation controller, controlling the programming operation, Wherein, the page buffer comprises: a first latch storing a first bit value among a plurality of bit values ​​indicating a threshold voltage region during a verification operation included in the programming operation; a second latch that stores a second bit value among the plurality of bit values ​​during the verify operation; and The bit line voltage control circuit controls a voltage applied to the bit line based on the first bit value and the second bit value during a program voltage applying operation after a verification operation included in the program operation.

17. The memory device of claim 16, wherein: The first latch stores a first bit value determined based on a first evaluation time in response to a first latch control signal.

18. The memory device of claim 17, wherein: After the first bit value is stored in the first latch, the second latch stores a second bit value determined based on a second evaluation time longer than the first evaluation time in response to a second latch control signal.

19. The memory device of claim 18, wherein: After the second bit value is stored in the second latch, the first latch stores a first bit value determined based on a third evaluation time that is longer than the second evaluation time in response to a third latch control signal.

20. The memory device of claim 16, wherein: The plurality of threshold voltage regions include a first threshold voltage region, a second threshold voltage region, a third threshold voltage region, and a fourth threshold voltage region which are successively higher.

21. The memory device of claim 20, wherein: The bit line voltage control circuit comprises: a first transistor connected to the bit line and a common sensing node; a second transistor connected to the common sensing node and the sensing node; a third transistor connected to a source of a power supply voltage and transmitting the power supply voltage when the first bit value corresponds to a first logic value as an initial logic value or a second logic value as an inversion value of the first logic value; a fourth transistor connected to the third transistor and the common sensing node and controlled in response to a first bit line voltage control signal; a fifth transistor connected to a source of the supply voltage and transmitting the supply voltage when the second bit value corresponds to the second logic value; a sixth transistor connected to the fifth transistor and transmitting a power supply voltage received through the fifth transistor when the first bit value corresponds to the first logic value; a seventh transistor connected to the sixth transistor and the common sensing node and controlled in response to a second bit line voltage control signal; and An eighth transistor is connected to the sixth transistor and the sensing node and is controlled in response to a third bit line voltage control signal.

22. The memory device of claim 21, wherein: When the one threshold voltage region corresponds to the first threshold voltage region, the first bit value and the second bit value correspond to the first logic value.

23. The memory device of claim 22, wherein: The first latch provides a ground voltage to the sensing node, and The bit line voltage control circuit interrupts supply of the power supply voltage by turning off the third transistor and the fifth transistor, and applies the ground voltage to the bit line by turning on the first transistor and the second transistor.

24. The memory device of claim 21, wherein: When the one threshold voltage region corresponds to the second threshold voltage region, the first bit value corresponds to the second logic value, and The second bit value corresponds to the first logic value.

25. The memory device of claim 24, wherein: The bit line voltage control circuit applies a first program enable voltage corresponding to the first bit line voltage control signal to the bit line by turning on the first transistor, the third transistor, and the fourth transistor.

26. The memory device of claim 21, wherein: When the one threshold voltage region corresponds to the third threshold voltage region, the first bit value and the second bit value correspond to the second logic value.

27. The memory device of claim 26, wherein: The second latch changes the first bit value to the first logic value, and The bit line voltage control circuit applies a second program enable voltage corresponding to the second bit line voltage control signal to the bit line by turning on the first transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

28. The memory device of claim 21, wherein: When the one threshold voltage region corresponds to the fourth threshold voltage region, the first bit value corresponds to the first logic value, and The second bit value corresponds to the second logic value.

29. The memory device of claim 28, wherein: The bit line voltage control circuit applies a program inhibition voltage corresponding to the third bit line voltage control signal to the bit line by turning on the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor.

30. A method of operating a page buffer, the page buffer being connected to a memory cell via a bit line, the method comprising: precharging the bit line and the sensing node; performing a first evaluation operation on the sensing node based on a first evaluation time; storing a first bit value determined based on the first evaluation operation in a first latch; performing a second evaluation operation based on a second evaluation time that is longer than the first evaluation time; storing a second bit value determined based on the second evaluation operation in a second latch; performing a third evaluation operation based on a third evaluation time that is longer than the second evaluation time; storing a first bit value determined based on the third evaluation operation in the first latch; determining whether the verification operation is passed according to the first bit value determined based on the third evaluation operation and the second bit value determined based on the second evaluation operation; as well as A voltage applied to the bit line is controlled according to a first bit value determined based on the third evaluation operation and a second bit value determined based on the second evaluation operation.

Images