Method of operating a storage system and storage system

Abstract

The application provides an operating method of a storage system, comprising: accumulating individual operation times of a plurality of storage blocks in a storage device to generate a plurality of accumulated values respectively corresponding to the plurality of storage blocks; judging a difference between two of the plurality of accumulated values corresponding to more accumulated operation times and less accumulated operation times; and performing a refresh operation on a longer idle storage block corresponding to the less accumulated operation times when the difference is equal to a preset value. The method and system of the application can reduce the drift caused by bias, help to reduce the data reading error caused by bias drift, and support longer power-on data maintenance time.

Description

Technical Field

[0001] This application relates generally to the field of electronic devices, and more particularly to a method of operating a storage system and the storage system itself. Background Technology

[0002] Memory is the foundation of information technology. As a candidate for next-generation non-volatile semiconductor memory, phase-change random access memory (PCM) has attracted widespread attention due to its advantages such as high-speed read / write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation, especially 3D PCM. Therefore, with the increase in storage capacity and the development of PCM technology, using PCM as the storage unit in large-capacity storage systems has become a trend.

[0003] However, how to ensure that the stored data in PCM is not affected by read and write operations of adjacent memory cells is an important issue, and therefore there is a need to propose an operating method that can solve these problems. Summary of the Invention

[0004] The purpose of this application is to provide an operation method and a storage system for solving the problem of data drift caused by read / write bias of storage cells.

[0005] In a first aspect, this application provides a method for operating a storage system, the method comprising:

[0006] The number of individual operations on multiple memory blocks in the cumulative memory is accumulated to generate multiple cumulative values ​​corresponding to the multiple memory blocks respectively;

[0007] Determine the difference between the two cumulative values ​​corresponding to the larger number of cumulative operations and the smaller number of cumulative operations among the plurality of cumulative values; and

[0008] When the difference equals a preset value, a refresh operation is performed on the longer idle storage block corresponding to the fewer cumulative operation counts.

[0009] Optionally, the method further includes: forming a stack table for storing the plurality of cumulative values ​​corresponding to the plurality of storage blocks respectively.

[0010] Optionally, the method further includes: after performing the refresh operation on the longer idle storage block, repeating the accumulation and the judgment to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and performing the refresh operation on the longer idle storage block.

[0011] Optionally, the method further includes: after performing the refresh operation on the longer idle storage block, updating the cumulative value corresponding to the longer idle storage block to the cumulative value corresponding to the more cumulative operation count, as the refreshed cumulative value.

[0012] Optionally, the method further includes: after performing the refresh operation on the longer idle storage blocks, removing the longer idle storage blocks from the judgment until the refresh status of the multiple storage blocks meets a predetermined condition before they are included in the judgment again.

[0013] Optionally, the method further includes:

[0014] Set initial values ​​for the plurality of cumulative values ​​corresponding to the plurality of storage blocks; and,

[0015] When the plurality of storage blocks includes N storage blocks, and N-1 storage blocks are refreshed, the cumulative values ​​corresponding to each of the individual storage blocks are reset to the initial values.

[0016] Optionally, the method further includes: setting the initial value of the accumulated value to 0, and incrementing the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed, wherein the operation includes either a write operation or a read operation.

[0017] Optionally, the method further includes: setting the initial value of the accumulated value to be greater than or equal to the preset value; decrementing the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed; and the operation includes either a write operation or a read operation.

[0018] Optionally, the method further includes: setting the storage block as an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage units in the memory, wherein N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0019] Optionally, the operation method further includes: setting the plurality of storage blocks to be located on the same bit line or word line.

[0020] Secondly, this application provides a storage system, the storage system comprising:

[0021] The memory has multiple storage blocks;

[0022] A controller, connected to the memory, is configured to control the memory and perform the following actions:

[0023] The number of individual operations on multiple memory blocks in the cumulative memory is accumulated to generate multiple cumulative values ​​corresponding to the multiple memory blocks respectively;

[0024] Determine the difference between the two cumulative values ​​corresponding to the larger number of cumulative operations and the smaller number of cumulative operations among the plurality of cumulative values; and

[0025] When the difference equals a preset value, a refresh operation is performed on the longer idle storage block corresponding to the fewer cumulative operation counts.

[0026] Optionally, the controller further includes a system memory for storing a stack table, which stores the plurality of cumulative values ​​corresponding to the plurality of storage blocks respectively.

[0027] Optionally, the controller is further configured to: after performing the refresh operation on the longer idle storage block, repeat the accumulation and the judgment to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and perform the refresh operation on the longer idle storage block.

[0028] Optionally, the controller is further configured to: after performing the refresh operation on the longer idle storage block, update the cumulative value corresponding to the longer idle storage block to the cumulative value corresponding to the more cumulative operation count, as the refreshed cumulative value.

[0029] Optionally, the controller is further configured to: after performing the refresh operation on the longer idle storage blocks, exclude the longer idle storage blocks from the judgment until the refresh status of the multiple storage blocks meets a predetermined condition, and then include them in the judgment again.

[0030] Optionally, the storage controller is further configured to: set initial values ​​for the plurality of cumulative values ​​corresponding to the plurality of storage blocks respectively; and, when the plurality of storage blocks includes N storage blocks and N-1 storage blocks are refreshed, reset the cumulative values ​​corresponding to each of the storage blocks to the initial values.

[0031] Optionally, the controller is further configured to: set the initial value of the accumulated value to 0, and increment the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed, wherein the operation includes either a write operation or a read operation.

[0032] Optionally, the controller is further configured to: set the initial value of the accumulated value to be greater than or equal to the preset value, and decrement the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed, wherein the operation includes either a write operation or a read operation.

[0033] Optionally, the storage block is an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage units in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0034] Optionally, the plurality of storage blocks are located on the same bit line or word line.

[0035] The operation method and storage system provided in this application can effectively reduce the impact of bias drift on system storage blocks, prevent read errors caused by excessive drift due to bias, and improve power-on data retention time.

[0036] The storage system operation method and storage system provided in this application can reduce the difference in the maximum number of writes of storage blocks on the same word line (WL) or bit line (BL) by configuring storage blocks and cooperating with wear leveling operations. Attached Figure Description

[0037] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0038] Figure 1 This is a functional block diagram of a storage system provided according to some embodiments of this application.

[0039] Figure 2 This is a functional block diagram of the peripheral circuitry of a memory provided according to some embodiments of this application.

[0040] Figure 3a This is a circuit diagram of a memory array according to some embodiments of the present application.

[0041] Figure 3b This is a schematic diagram of the structure of a phase-change memory cell provided according to some embodiments of this application.

[0042] Figure 4 This is a schematic diagram showing the distribution of threshold voltage drift in a memory cell according to some embodiments of this application.

[0043] Figure 5 This is a schematic diagram illustrating the steps of an operation method for a storage system provided according to some embodiments of this application.

[0044] Figure 6 This is a schematic diagram of a storage block in a memory according to some embodiments of this application.

[0045] Figure 7 This is a schematic diagram of a memory block under secondary addressing in a memory according to some embodiments of this application.

[0046] Figure 8 This is a schematic representation of a stack provided according to some embodiments of this application.

[0047] Figure 9 This is a schematic diagram illustrating further steps of the operation method of a storage system provided according to some embodiments of this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0049] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0050] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0051] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0052] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] This paper uses Cartesian coordinates to represent directions. With the substrate as the reference, "Z" represents the first direction, which is perpendicular to the substrate; "X" represents the second direction, which is parallel to the substrate; and "Y" represents the third direction, which is parallel to the substrate and perpendicular to X.

[0054] First, please refer to Figure 1 , Figure 1 A functional schematic block diagram of a storage system provided according to some embodiments of this application.

[0055] like Figure 1 As shown, a storage system 1 according to some embodiments of this application includes a controller 100 and a memory 200; the controller 100 is electrically connected to the memory 200 and is used to control the memory 200. The memory 200 then controls the storage array 10 in the memory through peripheral circuits 20 in the memory 200, and can perform various operations on each storage cell (not shown) in the storage array.

[0056] In some implementations, the storage system 1 may be implemented as a memory module, a high-end SSD, high-width memory (HBM), a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a PCMCIA card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0057] like Figure 2 As shown, the memory 200 mainly includes a memory array 10 and peripheral circuitry 20 connected to and controlling the memory array 10. The peripheral circuitry 20 typically includes at least a row decoder 210, a word line voltage generator 211, a word line driver 212, a column decoder 220, a bit line driver 222, a bit line voltage generator 221, a reference current / voltage generator 261, a sensitive amplifier / comparator 260, and a logic control module 230 connected to the aforementioned devices for receiving operation commands and controlling the aforementioned devices.

[0058] The row decoder 210 receives the row address signal from the bus 290 and decodes the row address signal to select the address word line.

[0059] The word line driver 212 is connected to multiple word lines WL<0:m>, the word line voltage generator 211, and the row decoder 210. The word line driver 212 receives the row address selection signal and the word line drive voltage, and outputs the word line drive voltage to the multiple word lines WL according to the row address selection signal. <m>At least one word line WL in the memory is connected to at least one row of memory cells.

[0060] Bit line driver 222, bit line voltage generator 221, and column decoder 220 belong to the column drive circuit, and as shown in the figure Figure 2 The connections are shown. The bit line voltage generator 221 and the column decoder 220 are connected to the logic control module 230 to be controlled by the logic control module 230.

[0061] Column decoder 220 receives the column address signal and decodes it to select the address bit line connected to the target memory cell. Bit line voltage generator 221 generates the voltage required for each selected bit line BL and outputs the set voltage to each corresponding selected bit line BL.

[0062] Bit line driver 222 is connected to multiple bit lines BL, bit line voltage generator 221, and column decoder 220. Bit line driver 222 receives bit line voltage and column address selection signal, and outputs the set bit line voltage to multiple bit lines BL according to the column address selection signal. <n>at least one column of the memory cells connected to at least one bit line BL.

[0063] The peripheral circuit 20 further includes a sense amplifier comparator 260, a reference current / voltage generator 261, a data latch 270, etc. The sense amplifier comparator 260 is connected to the reference current / voltage generator 261 and the plurality of bit lines BL<0:n> and is connected to the data latch 270. The sense amplifier comparator 260 is used to compare the data stored in the selected memory cell with the reference value generated by the reference current / voltage generator 261 after receiving the read data when reading the data, and then store the data in the data latch 270, which is output to the data bus 290 together with the data read by other bit lines via the input / output interface 280.

[0064] Based on the structure design of the peripheral circuit 20 of the memory, the operation of the memory can include an erase operation, a read operation, and a program operation, or a set and reset operation. Moreover, when performing the various operations, the controller 100 receives the logical address information according to an L2P (logical address to physical address) mapping table, sends the physical address according to the L2P mapping table, and the peripheral circuit 20 receives the physical address, selects the appropriate word line WL and bit line BL through the row decoder 210 and the column decoder 220, and then performs the addressing of the memory cells in the memory array 10, and then performs the various operations on the selected memory cells through the word line driver 212 and the bit line driver 222. Moreover, when addressing, in some embodiments, the logical address is arranged in the order of the word line WL and the bit line BL address, for example, as shown in the following Figure 3a memory array, the addressing is performed on one WL first, and then different BLs are traversed, and then the next WL is switched to perform the addressing.

[0065] It can be understood that although the memory 200 and the controller 100 are collectively referred to as a storage system, the controller 100 can be combined with the memory 200 in one chip in some embodiments, and therefore, the storage system actually can be a memory, and is not limited to the naming of a so-called system.

[0066] Please continue to refer to Figure 3a , Figure 3a The circuit diagram of the memory array 10 as an example of the memory according to some embodiments of the present application is provided. The memory array 10 includes a plurality of memory cells 11 arranged in a plurality of rows and a plurality of columns, and a word line WL and a bit line BL connected to the plurality of memory cells 11 in the plurality of rows and the plurality of columns, respectively. Each row of memory cells includes a plurality of memory cells 11 arranged along a row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along a column direction (i.e., a second direction Y). Figure 3a The diagram only shows the storage units of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1, where n represents any positive integer greater than 2. In reality, the number of rows and columns of storage units in the memory depends on its storage capacity.

[0067] It should be understood that the memory cells in the memory array can be memory cells of various structures, such as floating gate memory cells, ONO memory cells, resistive RAM (RRAM) memory cells, phase change memory cells (PCM / PCRAM / SOM), etc. This application does not limit them, but this application is particularly applicable to phase change memory cells. Therefore, the following will use the phase change memory cell PCM as an example for illustration, but it should be understood that it is not limited to this.

[0068] Figure 3a The illustrated storage cell is a phase-change storage cell 11, which includes an omonic threshold switch (OTS) 111 and a phase-change storage cell (PCM cell) 112 connected in series between the word line WL and the bit line BL. Both the omonic threshold switch (OTS) 111 and the PCM cell 112 are made of phase-change materials. However, in some technologies, since the PCM cell 112 is used as the threshold setting for data storage, in this embodiment, the two phase-change materials in the storage cell 11 are referred to as the omonic threshold switch (OTS) 111 and the PCM storage cell 112, respectively.

[0069] Figure 3b A schematic diagram of the structure of a storage unit provided for some embodiments of this application. For example... Figure 3b As shown, some embodiments of this application provide a phase-change memory cell structure including: a top electrode 11a and a bottom electrode 11b respectively connecting the word line WL and the bit line BL, and a phase-change memory cell 112, an intermediate electrode 11c, and a bidirectional threshold switch (OTS) 111 located between the top electrode 11a and the bottom electrode 11b. It should be understood that in some embodiments, the intermediate electrode 11c may not be provided, therefore this application is not limited to the structure disclosed herein.

[0070] The phase change memory cell 112 includes one or more phase change materials such as a germanium-antimony-tellurium (Ge-Sb-Te, GST)-based material, one example of which can be Ge2Sb2Te5. Currently more popular phase change materials are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. Phase change materials can have a large resistivity contrast between different phases (e.g., crystalline and amorphous). For example, a phase change material can exhibit a relatively low resistivity in a crystalline phase, but a relatively high resistivity in an amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than in the crystalline phase.

[0071] The phase change material can switch between different phases when heated, enabling writing (including setting and resetting) of information (data). In the present embodiment, the electrodes 11a, 11c can heat the phase change memory cell 112 via the OTS 111 to change the phase of the heated region 112f in the phase change cell 112, thereby reducing the resistance of the phase change memory cell 112 (setting). The top electrode 11a and the bottom electrode 11b are arranged opposite each other and can be interchanged and overlap the bit line BL and the word line WL on the outside, thereby forming a 3D phase change memory.

[0072] In some embodiments, the OTS device is composed of a phase change material such as Ge-Te-As-Si, in which case the threshold voltage Vth of the OTS 111 will change under the control of the polarity of the applied voltage, more specifically, the threshold voltage will change by ΔVth as the polarity of the applied voltage changes. With this ΔVth, even without the phase change cell 112, setting and resetting can be achieved, and the OTS device can be used independently as a binary storage device, so in this example the OTS 111 is referred to as a SOM (selector only memory) or SSM (self-selecting memory).

[0073] Therefore, it can be understood that the phase change memory (PCM) described in the present application includes various variants of PCM, such as Xpoint type PCM, and selector only memory SOM (selector only memory) or SSM (self-selecting memory) composed of the aforementioned OTS, and also includes two-dimensional (2D) and three-dimensional (3D) arrangements of various phase change memories, as well as single-pole or multi-level storage PCM.

[0074] Furthermore, in further research within this application, it was understood that when a read / write operation is performed on a cell, for example... Figure 3a The memory cell 11(S) will apply a higher voltage bias, such as Vhh and Vll, to the corresponding WLn (word line) and BLn (bit line); the unselected WLn+1 / n-1 and BLn+1 / n-1 will be kept at zero bias or low bias, such as Vuw and Vub, to ensure the non-conducting state.

[0075] Furthermore, for example, selecting the... Figure 3a When a write operation is performed on memory cell 11(s), a write voltage Vwrite is applied to the corresponding BLn (bit line), and a zero bias voltage V0 is applied to WLn (bit line). For unselected adjacent memory cells 11(a) and 11(b), a low bias voltage, such as Vwrite / 2, is applied to the corresponding word line and bit line WLn+1 / n-1 and BLn+1 / n-1. For other unselected cells on the same WLn and BLn as the selected memory cell 11(s), although they will not be selected for conduction or writing, there will still be a certain bias voltage across memory cell 11. These memory cells 11 will have a bias voltage drift problem. That is, the threshold voltage drift caused by the operation bias voltage on the same bit line word line to other memory cells.

[0076] Figure 4 The diagram shows the Vth distribution for set and reset states when the threshold voltage (Vth) exhibits a bias drift effect in this study. The curve to the left of Vread represents the Vth distribution for set states, and the curve to the right of Vread represents the Vth distribution for reset states. The solid line B0 indicates the absence of bias drift. As the number of operations on the same word line WL or bit line BL increases, the corresponding Vth distribution for set and reset states will drift as shown by the dashed lines B1 and B2. The bias drift is strongly correlated with the number of operations (i.e., the stress). The more operations, the greater the impact of the bias drift. Due to the presence of bias drift, the read window margin (RWM) that accurately distinguishes set and reset states is greatly reduced, which easily leads to read errors.

[0077] In some three-dimensional phase change memory embodiments, if a 2k WL x 4k BL x 2 stack architecture is used, the bias voltage on the same word line / bit line (WL / BL) will affect the 4k memory cells above and below the memory cell of the same word line WL, and affect 2k memory cells of the same bit line BL, resulting in threshold voltage shift and power on retention problem.

[0078] In some embodiments, read retry or ECC (error correction) is used to solve the bias voltage shift and power on retention problem, but the increase of read retry times will sacrifice the system performance, and there is room for improvement.

[0079] Therefore, according to some embodiments of the present application, as shown in Figure 5 The present application further provides an operating method of a memory system, comprising:

[0080] Step S1: accumulating the individual operation times of a plurality of memory blocks in a memory to generate a plurality of accumulated values respectively corresponding to the plurality of memory blocks;

[0081] Step S2: determining the difference between two of the plurality of accumulated values corresponding to more accumulated operation times and less accumulated operation times; and

[0082] Step S3: when the difference is equal to a preset value, performing a refresh operation on the memory block corresponding to the less accumulated operation times.

[0083] Specifically, as shown in Figure 6 A memory array 10 in a memory includes a plurality of memory blocks 10b, each of which has a corresponding block address. Each memory block 10b can include a plurality of memory cells 11 as described above. The number of memory blocks 10b in the memory array 10 can be n*n, and the serial numbers can be ROW1-1, ROW1-2, …, ROW1-n, …, ROWn-1, …, ROWn-n.

[0084] In some embodiments, the memory blocks 10b are arranged as a matrix of N*M memory cells in the memory, and N and M are positive integers greater than 1, and N can be equal to or different from M. Specifically, as shown in Figure 7 Figure 7 ​In particular, a schematic diagram of a memory block with second-level addressing in a memory according to some embodiments of this application is shown. N and M can both be 64, that is, 4096 memory cells constitute one memory block 10b. These 4096 memory blocks 10b then constitute a memory array 10. Figure 7 In the example shown, storage block 10b can be addressed by using the high-order bits of the address (ROW0 to ROW4096) and storage cell addressing by using the low-order bits of the address (ADD0 to ADD4096), thus achieving two-level addressing. Refresh management is then performed through storage block 10b, i.e., ROW to ROW4096.

[0085] However, it is understood that the division of storage block 10b shown is not limited to the foregoing example. In some embodiments, the storage block 10b may also be divided into units of individual storage stacks, storage planes, block storage arrays, or page storage arrays in the memory.

[0086] Furthermore, in some embodiments, the plurality of storage blocks 10b for cumulative value comparison are configured such that multiple storage blocks 10b on the same bit line or word line are grouped together, and the cumulative values ​​of each storage block within a group are compared. Since each read / write operation affects the storage cells on the same bit line or word line, this configuration allows for individual comparison of storage blocks on the same word line or bit line within a range. This enables more precise remediation of data corruption when storage blocks on the same word line or bit line experience significantly different numbers of write operations.

[0087] Specifically, such as Figure 7 As shown, the cumulative values ​​of storage block numbers ROW0 to ROW63 can be compared within a range, and the cumulative values ​​of storage block numbers ROW64 to ROW127 can also be compared within a range.

[0088] In some embodiments, the method further includes forming a stack table for storing the plurality of cumulative values ​​corresponding to the plurality of storage blocks, respectively.

[0089] Specifically, such as Figure 8 As shown, the stack table 300 stores multiple cumulative values ​​corresponding to the multiple storage blocks 10b. Furthermore, the initial value of each of the multiple storage blocks 10b can be 0 or, for example, 2000. Each time an operation is performed, the cumulative value of the corresponding storage block is incremented by 1 (with an initial value of 0) or decremented by 1 (with an initial value of, for example, 2000). That is, the count can be incremented or decremented. Specifically, when the initial value is set to 0, each time an operation is performed, the cumulative value of the corresponding storage block is incremented by 1. When the initial value is set to a value greater than or equal to a preset value, each time an operation is performed, the cumulative value of the corresponding storage block is decremented by 1. The operation includes either a write operation or a read operation.

[0090] exist Figure 8 In the example shown, the data is not sorted by cumulative value, but by storage block number. However, in some embodiments, the cumulative value can be sorted in the stack table.

[0091] like Figure 5 As described in steps S2 and S3 above, when the difference between the cumulative values ​​corresponding to the more cumulative operation count and the less cumulative operation count among the plurality of cumulative values ​​is equal to a preset value, the storage block corresponding to the less cumulative operation count is set as a longer idle storage block, and a refresh operation is performed on the longer idle storage block.

[0092] Specifically, with Figure 8 In the example shown, if the preset value is set to 2000, then when there are 2000 cumulative values ​​for storage block ROW1-1 and 0 cumulative values ​​for storage block ROWn-n in the stack table, that is, when the difference equals the preset value of 2000, the condition described in step S3 is met, and a refresh operation is performed on the storage block ROWn-n, which corresponds to the fewer cumulative operation counts (0). The refresh operation can use various feasible methods in the prior art, which will not be elaborated here.

[0093] Furthermore, in some embodiments, such as Figure 9 As shown, optionally, the method further includes:

[0094] After performing the refresh operation on the longer idle storage block, return to steps S1 and S2, repeat the accumulation and judgment for each storage block 10b, so as to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and perform the refresh operation on the longer idle storage block.

[0095] Specifically, for example, after refreshing the relatively idle storage block ROWn-n, the cumulative value of storage block ROW1-1 with a large number of cumulative operations reaches 2010. In addition to the aforementioned old relatively idle storage block ROWn-n, the cumulative value of the second storage block with fewer cumulative operations, such as ROWn-1, reaches 10. That is, a second storage block ROWn-1 with fewer cumulative operations that meets the preset value of 2000 appears, and it is used as the new relatively idle storage block. Then, the refresh operation is performed on the new relatively idle storage block ROWn-1.

[0096] It's important to clarify that since steps S1-S3 are repetitive, for ease of description, both old and new relatively long-idle storage blocks are referred to as "relatively long-idle storage blocks." However, it should be understood that the term "relatively long-idle storage block" can refer to something old or new depending on the step. But within a loop of steps S1-S3 that hasn't returned to step S1, the "relatively long-idle storage block" refers to the same block. Furthermore, the statement "besides the aforementioned old relatively long-idle storage blocks" means that in some embodiments, after the old relatively long-idle storage block ROWn-n is refreshed, the determination of its accumulated value can be excluded. There are several possible methods for this exclusion, which will be further explained below.

[0097] In some embodiments, such as Figure 9 As shown, the method may optionally include the following after step S3:

[0098] Step S31a: After performing the refresh operation on the longer idle storage block, update the cumulative value corresponding to the longer idle storage block to the cumulative value corresponding to the more cumulative operation count, as the refreshed cumulative value.

[0099] Specifically, as in the example described above, after the storage block ROWn-n, which has fewer cumulative operation counts (0), is refreshed, the cumulative value of the longer idle storage block ROWn-n is set to 2000, which is the cumulative value of the more cumulative operation counts. In this way, even if the longer idle storage block ROWn-n is not excluded from the comparison of cumulative values, because its cumulative value is set to 2000, the difference between it and the cumulative value of the more cumulative operation counts (2000) will be minimal, becoming 0. Therefore, compared to other storage blocks 10b, it will be the storage block with the smallest difference and will not quickly fall into the refresh process, nor will it be considered an object to be refreshed.

[0100] Furthermore, regarding the handling of the relatively long-idle storage block ROWn-n after the refresh, in addition to the embodiment shown in step S31a above, in some embodiments, the operation method may also alternatively include:

[0101] Step S31 b: After performing the refresh operation on the long-idle storage blocks, the long-idle storage blocks are removed from the accumulation and judgment steps S1 and S2 until the refresh status of the multiple storage blocks meets the predetermined conditions, at which point they are included in the accumulation and judgment steps again.

[0102] Specifically, in some embodiments, instead of modifying the cumulative value corresponding to the longer idle storage block ROWn-n to 2000 as described in step S31a above, the longer idle storage block ROWn-n can be directly excluded from the subsequent cumulative value comparison objects.

[0103] As for when to include the relatively idle storage blocks ROWn-n in the cumulative value comparison again, it can be determined according to predetermined conditions. For example, this predetermined condition could be that half of the storage blocks in the plurality of storage blocks will not be included in the judgment again. Or, for example, this predetermined condition could be that if the plurality of storage blocks includes N storage blocks, then N-1 storage blocks will not be included in the judgment again after they have been refreshed; that is, all storage blocks except for the storage blocks with a higher cumulative number of operations have been refreshed.

[0104] In some embodiments, after the operation in step 31b, when the longer idle storage blocks ROWn-n or all storage blocks are to be included in the determination again, such as Figure 9 As shown, it may further include:

[0105] Step S32: Reset the accumulated value corresponding to the longer idle storage blocks, or to each of the storage blocks individually, to the initial value.

[0106] Specifically, for example, the cumulative value of the longer idle storage block ROWn-n, or the cumulative value of all storage blocks, can be reset to the initial value of 0 or 2000.

[0107] As is understandable, while the preceding examples focused on the handling of longer-idle storage blocks in a single round after a refresh, the same approach can be applied to refreshes in the second, third, fourth, and N-1th rounds. That is, after a refresh, each storage block can choose to update its accumulated value or exclude it from the accumulation and comparison process.

[0108] Furthermore, it's understandable that when the cumulative value is a +1 increment (upward), it's easy to see that the cumulative value is simply the upward value itself. However, when the cumulative value is a -1 decrement (downward), the cumulative number of operations mentioned here is not equal to the downward value itself, but rather refers to the difference between the downward value and the initial value. For example, when the initial value is 2000 or a larger value and a downward count is performed, when the downward value reaches 500, the so-called cumulative number of operations refers to 1500 times (2000 - 500), not the value 500 itself. Therefore, when comparing and judging the multiple cumulative values, the statement "judging the difference between the two cumulative values ​​corresponding to the larger and smaller cumulative number of operations" can be applied to both upward and downward counting scenarios.

[0109] The following is an explanation of an embodiment for updating the cumulative value, using the count as an example. For instance, if the initial value is 2000 and the preset value is 1000, when the count of fewer cumulative operations reaches 1500 and there are 500 cumulative operations, and the count of more cumulative operations has reached 500 and there are 1500 cumulative operations, the difference between the cumulative value corresponding to the more and fewer cumulative operations reaches the preset value of 1000. At this time, a refresh operation is performed on the storage block with a count of 1500 and fewer cumulative operations, and the count of the longer idle storage block with fewer cumulative operations is set to 500, which is the same as the count of 500 corresponding to the more cumulative operations, so it will not be refreshed again quickly.

[0110] Furthermore, in some embodiments, it is understood that the cumulative value after refresh is not limited to the cumulative value corresponding to a large number of cumulative operations, but can be any appropriate value, such as a smaller cumulative value. Also, it is understood that the practice of excluding refreshed storage blocks from comparison can be implemented after a certain number of storage blocks have been refreshed, i.e., not necessarily N-1 as mentioned above, but for example N / 2, where the cumulative value of all storage blocks can be returned to its initial value, and all storage blocks can be included in the next round of comparison.

[0111] The operation method of the storage system provided in this application, as described above, can effectively reduce the impact of bias drift on the system storage blocks, prevent read errors caused by excessive threshold voltage drift of the storage cells due to bias, and improve the power-on data retention time.

[0112] The storage system operation method provided in this application can further reduce the difference in the maximum number of writes of storage blocks on the same word line (WL) or bit line (BL) by configuring storage blocks and cooperating with wear leveling operations.

[0113] Based on the operation methods of the storage system provided in the foregoing embodiments, some embodiments of this application also provide a storage system, including:

[0114] Memory, including a memory array consisting of multiple memory cells; and

[0115] A controller, electrically connected to the memory, is configured to control the memory and perform the following actions:

[0116] The number of individual operations on multiple memory blocks in the cumulative memory is accumulated to generate multiple cumulative values ​​corresponding to the multiple memory blocks respectively;

[0117] Determine the difference between the two cumulative values ​​corresponding to the larger number of cumulative operations and the smaller number of cumulative operations among the plurality of cumulative values; and

[0118] When the difference equals a preset value, a refresh operation is performed on the longer idle storage block corresponding to the fewer cumulative operation counts.

[0119] Specifically, such as Figure 1 The structure shown allows for the configuration of various modules within the controller 100 to perform the aforementioned cumulative actions, judgment actions, and refresh actions.

[0120] In some embodiments, the controller further includes a system memory for storing a stack table for storing the plurality of cumulative values ​​corresponding to the plurality of storage blocks.

[0121] In some embodiments, the controller is further configured to: after performing the refresh operation on the longer idle storage block, repeat the accumulation and the judgment to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and perform the refresh operation on the longer idle storage block.

[0122] In some embodiments, the controller is further configured to: after performing the refresh operation on the longer idle storage block, update the cumulative value corresponding to the longer idle storage block to the cumulative value corresponding to the more cumulative operation count, as the refreshed cumulative value.

[0123] In some embodiments, the controller is further configured to: after performing the refresh operation on the long-idle storage blocks, exclude the long-idle storage blocks from the judgment until the refresh status of the plurality of storage blocks meets a predetermined condition before they are included in the judgment again.

[0124] In some embodiments, the storage controller is further configured to: set initial values ​​for the plurality of cumulative values ​​corresponding to the plurality of storage blocks respectively; and when the plurality of storage blocks includes N storage blocks and N-1 storage blocks are refreshed, reset the cumulative values ​​individually corresponding to all storage blocks to the initial values.

[0125] In some embodiments, the controller is further configured to: set the initial value of the accumulated value to 0, and increment the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed, wherein the operation includes one of a write operation and a read operation.

[0126] In some embodiments, the controller is further configured to: set the initial value of the accumulated value to be greater than or equal to the preset value, and decrement the accumulated value of the corresponding storage block of the operation by 1 each time the operation is performed, wherein the operation includes one of a write operation and a read operation.

[0127] In some embodiments, the storage block is an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage units in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0128] In some embodiments, the plurality of storage blocks are located on the same bit line or word line.

[0129] The operations for these configurations have been explained in the corresponding operation methods described above. They can be implemented with the controller's software and firmware, so they will not be repeated here. Please refer to the previous descriptions for details.

[0130] The storage system disclosed in this application can also achieve the beneficial effects described above for various operating methods and configurations. That is, it can not only reduce the impact of bias drift and help reduce the problem of bias drift, but also support a longer power-on data retention time.

[0131] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.< / n> < / m>

Claims

1. A method for operating a storage system, characterized in that, The operation method includes: The cumulative number of write and read operations in multiple storage blocks in the cumulative memory is used to generate multiple cumulative values ​​corresponding to the multiple storage blocks respectively. Determine the difference between the two cumulative values ​​corresponding to the larger number of cumulative operations and the smaller number of cumulative operations among the plurality of cumulative values; and When the difference equals a preset value, a refresh operation is performed on the longer idle storage block corresponding to the fewer cumulative operation counts.

2. The operating method as described in claim 1, characterized in that, The method further includes: A stack table is formed to store the cumulative values ​​corresponding to the plurality of storage blocks.

3. The operating method as described in claim 1, characterized in that, The method further includes: After performing the refresh operation on the relatively long idle storage block, the accumulation and judgment are repeated to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the relatively long idle storage block, and the refresh operation is performed on the relatively long idle storage block.

4. The operating method as described in claim 1, characterized in that, The method further includes: After performing the refresh operation on the longer idle storage block, the cumulative value corresponding to the longer idle storage block is updated to the cumulative value corresponding to the more cumulative operation count, as the cumulative value after refresh.

5. The operating method as described in claim 1, characterized in that, The method further includes: After the refresh operation is performed on the long-idle storage blocks, the long-idle storage blocks are removed from the judgment until the refresh status of the multiple storage blocks meets the predetermined conditions, at which point they are included in the judgment again.

6. The operating method as described in claim 2, characterized in that, The method further includes: Set initial values ​​for the plurality of cumulative values ​​corresponding to the plurality of storage blocks; and, When the plurality of storage blocks includes N storage blocks, and N-1 storage blocks are refreshed, the cumulative values ​​corresponding to each of the individual storage blocks are reset to the initial values.

7. The operating method as described in claim 2, characterized in that, The method further includes: The initial value of the accumulated value is set to 0. Each time the operation is performed, the accumulated value of the corresponding storage block of the operation is incremented by 1. The operation includes either a write operation or a read operation.

8. The operating method as described in claim 2, characterized in that, The method further includes: The initial value of the accumulated value is set to be greater than or equal to the preset value. Each time the operation is performed, the accumulated value of the corresponding storage block of the operation is decremented by 1. The operation includes either a write operation or a read operation.

9. The operating method as described in claim 1, characterized in that, The method further includes: The storage block is configured as an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage units in the memory, where N and M are positive integers greater than 1, and N is equal to or not equal to M.

10. The operating method as described in claim 1, characterized in that, The operation method further includes: The plurality of storage blocks are configured to be located on the same bit line or word line.

11. A storage system, characterized in that, The storage system includes: Memory, having multiple storage blocks; and A controller, connected to the memory, is configured to control the memory and perform the following actions: The cumulative number of write and read operations in multiple storage blocks in the cumulative memory is used to generate multiple cumulative values ​​corresponding to the multiple storage blocks respectively. Determine the difference between the two cumulative values ​​corresponding to the larger number of cumulative operations and the smaller number of cumulative operations among the plurality of cumulative values; and When the difference equals a preset value, a refresh operation is performed on the longer idle storage block corresponding to the fewer cumulative operation counts.

12. The storage system as claimed in claim 11, characterized in that, The controller also includes a system memory for storing a stack table, which stores the cumulative values ​​corresponding to the plurality of storage blocks.

13. The storage system as claimed in claim 11, characterized in that, The controller is also configured as follows: After performing the refresh operation on the relatively long idle storage block, the accumulation and judgment are repeated to determine the second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the relatively long idle storage block, and the refresh operation is performed on the relatively long idle storage block.

14. The storage system as claimed in claim 11, characterized in that, The controller is also configured as follows: After performing the refresh operation on the longer idle storage block, the cumulative value corresponding to the longer idle storage block is updated to the cumulative value corresponding to the more cumulative operation count, as the cumulative value after refresh.

15. The storage system as claimed in claim 11, characterized in that, The controller is also configured as follows: After the refresh operation is performed on the long-idle storage blocks, the long-idle storage blocks are removed from the judgment until the refresh status of the multiple storage blocks meets the predetermined conditions, at which point they are included in the judgment again.

16. The storage system as claimed in claim 13, characterized in that, The controller is also configured as follows: Set initial values ​​for the plurality of cumulative values ​​corresponding to the plurality of storage blocks respectively; as well as When the plurality of storage blocks includes N storage blocks, and N-1 storage blocks are refreshed, the cumulative values ​​corresponding to each of the individual storage blocks are reset to the initial values.

17. The storage system as claimed in claim 13, characterized in that, The controller is also configured as follows: The initial value of the accumulated value is set to 0. Each time the operation is performed, the accumulated value of the corresponding storage block of the operation is incremented by 1. The operation includes either a write operation or a read operation.

18. The storage system as claimed in claim 11, characterized in that, The controller is also configured as follows: The initial value of the accumulated value is set to be greater than or equal to the preset value. Each time the operation is performed, the accumulated value of the corresponding storage block of the operation is decremented by 1. The operation includes either a write operation or a read operation.

19. The storage system as claimed in claim 11, characterized in that, The storage block is an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage units in the memory, where N and M are positive integers greater than 1, and N is equal to or not equal to M.

20. The storage system as claimed in claim 11, characterized in that, The multiple storage blocks are located on the same bit line or word line.

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