High-speed frequency divider, multimode frequency divider, phase-locked loop circuit, chip and electronic equipment

Abstract

The invention provides a high-speed frequency divider, a multi-mode frequency divider, a phase-locked loop circuit, a chip and electronic equipment, the high-speed frequency divider comprises four latch circuits, each latch circuit comprises a gating unit and a latch unit, the gating unit is switched between a conducting state and a non-conducting state according to an input clock signal, the latch unit comprises two phase inverters, and the phase inverters are connected with the gating unit and the latch unit. The connection state of the two phase inverters is controlled according to different level states of input clock signals, so that inverted output or latching of the signals is realized; a gating unit in the first latch circuit comprises a first NAND gate logic circuit which comprises a gating control end for receiving an input clock signal, so that the first NAND gate logic circuit is switched to a conducting state during a first level state of the input clock signal and is switched to a non-conducting state during a second level state of the input clock signal. According to the multi-mode frequency divider, the path delay of the first-stage 2 / 3 frequency divider is reduced, the speed performance of the first-stage 2 / 3 frequency divider is improved, and the multi-mode frequency divider can work at a higher working frequency.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a high-speed frequency divider, a multi-mode frequency divider, a phase-locked loop circuit, a chip and an electronic device. Background Art

[0002] The divider is one of the core modules of wired and wireless transceivers and is widely used in high-speed communications and circuits. Its main function is to generate an output signal according to a certain frequency division ratio of the input signal. A multi-modulus divider (MMD) is a programmable divider that can obtain multiple frequency division ratios through programming, thereby generating output signals of multiple frequencies. The divider or multi-modulus divider (MMD) is one of the important components of a fractional phase-locked loop. It can convert high-frequency signals into low-frequency signals at a specific ratio. For example, it can be used in the feedback branch of a phase-locked loop to complete the switching between channels.

[0003] Currently, most multi-mode dividers use a cascaded 2 / 3 divider module, where the next-stage input signal is generated by the previous-stage divider, and the operating frequency decreases step by step. Therefore, the divider operating frequency is limited by the performance of the first-stage 2 / 3 divider. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a high-speed divider, a multi-mode divider, a phase-locked loop circuit, a chip and an electronic device, aiming to solve the speed limitation problem of traditional architecture multi-mode dividers in high-speed applications.

[0005] According to a first aspect of the present application, a high-speed frequency divider is provided, comprising:

[0006] a first latch circuit, a second latch circuit, a third latch circuit and a fourth latch circuit;

[0007] The first latch circuit, the second latch circuit, the third latch circuit and the fourth latch circuit each include a gating unit and a latch unit connected to an output end of the gating unit;

[0008] The gating unit is used to switch between a conducting state and a non-conducting state according to an input clock signal;

[0009] The latch unit includes a second inverter and a third inverter, and the latch unit is used to output the input terminal signal through the second inverter according to the input clock signal, or to latch the signal by using the second inverter and the third inverter in an end-to-end state;

[0010] Wherein, the gating unit in the first latch circuit comprises:

[0011] A first NAND gate logic circuit includes a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal receives the output terminal signal of the second latch circuit, the second input terminal receives the output terminal signal of the fourth latch circuit, and the gating control terminal receives the input clock signal. The first NAND gate logic circuit is used to switch to a conducting state during a first level state of the input clock signal, and to switch to a non-conducting state during a second level state of the input clock signal.

[0012] Optionally, the latch unit further includes:

[0013] a transmission gate logic circuit connected in series with the third inverter between the output terminal and the input terminal of the second inverter, the transmission gate logic circuit switching between a conducting state and a non-conducting state according to the input clock signal;

[0014] Wherein, when the transmission gate logic circuit is in the on state, the second inverter and the third inverter are in an end-to-end connection state;

[0015] When the transmission gate logic circuit is in a non-conducting state, the third inverter does not participate in the operation.

[0016] Optionally, the second inverter and the third inverter each include an input terminal and an output terminal, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the input terminal of the second inverter;

[0017] The third inverter also includes an enable control terminal. During the period when the signal at the enable control terminal is in the second level state, the third inverter inverts and outputs the output signal of the second inverter. During the period when the signal at the enable control terminal is in the first level state, the third inverter does not participate in the operation.

[0018] Optionally, the gating unit in the second latch circuit includes:

[0019] a transmission gate logic circuit, the input end of which is connected to the output end of the first latch circuit, and switches between a conducting state and a non-conducting state according to the input clock signal,

[0020] The transmission gate logic circuit is in a conducting state during a second level state of the input clock signal, and is in a non-conducting state during a first level state of the input clock signal.

[0021] Optionally, the gating unit in the third latch circuit includes:

[0022] The second NAND gate logic circuit includes a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal of the second NAND gate logic circuit receives an inverted signal of the output terminal signal of the second latch circuit, the second input terminal of the second NAND gate logic circuit receives a mode input signal, the gating control terminal of the second NAND gate logic circuit receives the input clock signal, and the second NAND gate logic circuit is used to switch to a conducting state during a first level state of the input clock signal, and to switch to a non-conducting state during a second level state of the input clock signal.

[0023] Optionally, the gating unit in the fourth latch circuit includes:

[0024] A third NAND gate logic circuit comprises a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal of the third NAND gate logic circuit receives the output terminal signal of the third latch circuit, the second input terminal of the third NAND gate logic circuit receives the frequency division selection signal, the gating control terminal of the third NAND gate logic circuit receives the inverted signal of the input clock signal, and the third NAND gate logic circuit is used to switch to a conducting state during the second level state of the input clock signal, and to switch to a non-conducting state during the first two level states of the input clock signal.

[0025] According to a second aspect of the present application, a multi-mode frequency divider is provided, comprising:

[0026] n cascaded frequency division modules, wherein the first-stage frequency division module of the n cascaded frequency division modules adopts a high-speed frequency divider as disclosed in any embodiment of the present application, and n is an integer greater than or equal to 4;

[0027] The frequency division control circuit logically combines a plurality of frequency division selection signals and a plurality of mode output signals to obtain mode input signals of frequency division modules at each level.

[0028] Optionally, among the n cascaded frequency division modules, each frequency division module except the first-stage frequency division module includes:

[0029] a fourth NAND gate logic circuit, a fifth NAND gate logic circuit, and a sixth NAND gate logic circuit;

[0030] A first latch, wherein a clock input terminal receives an input clock signal, and a data input terminal is connected to an output terminal of the fourth NAND gate logic circuit;

[0031] A second latch, wherein a clock input terminal receives the input clock signal, a data input terminal is connected to an inverting output terminal of the first latch, an inverting output terminal of the second latch is connected to a first input terminal of the fourth NAND gate logic circuit, and an output frequency-divided clock signal is generated simultaneously, a non-inverting output terminal of the second latch is connected to a first input terminal of the fifth NAND gate logic circuit, and a second input terminal of the fifth NAND gate logic circuit receives a mode input signal;

[0032] A third latch, wherein the clock input terminal receives the input clock signal, the data input terminal is connected to the output terminal of the fifth NAND gate logic circuit, the inverting output terminal of the third latch is connected to the first input terminal of the sixth NAND gate logic circuit, and a mode output signal is generated at the same time, and the second input terminal of the sixth NAND gate logic circuit receives the frequency division selection signal;

[0033] The fourth latch has a clock input terminal receiving the input clock signal, a data input terminal connected to the output terminal of the sixth NAND gate logic circuit, and a non-inverting output terminal of the fourth latch connected to the second input terminal of the fourth NAND gate logic circuit.

[0034] Optionally, the frequency division control circuit includes:

[0035] Multiple logic units are respectively connected to the mode input terminals of the first-level frequency division module to the n-1-th level frequency division module, and each logic unit is used to obtain the mode input signal of the corresponding frequency division module according to the frequency division selection signals of each subsequent level frequency division module of the corresponding frequency division module and the mode output signal of the subsequent level frequency division module of the corresponding frequency division module.

[0036] Optionally, the logic unit corresponding to the first-stage frequency division module is a first logic unit, comprising a seventh NAND gate logic circuit, a first input end of the seventh NAND gate logic circuit is connected to the mode output end of the second-stage frequency division module, a second input end is connected to the second output end of the logic unit corresponding to the second-stage frequency division module, and an output end of the seventh NAND gate logic circuit is connected to the mode input end of the first-stage frequency division module;

[0037] Each of the plurality of logic units except the first logic unit comprises:

[0038] an eighth NAND gate logic circuit, wherein the first input end is connected to the mode output end of the subsequent frequency division module of the corresponding frequency division module, the second input end is connected to the second output end of the logic unit corresponding to the subsequent frequency division module of the corresponding frequency division module, the output end of the eighth NAND gate logic circuit serves as the first output end of the logic unit and is connected to the mode input end of the corresponding frequency division module;

[0039] A fourth inverter, an input end of which is connected to a second output end of a logic unit corresponding to a subsequent frequency division module of the corresponding frequency division module;

[0040] A fifth inverter, an input end of which is connected to a frequency division selection end of a subsequent frequency division module of the corresponding frequency division module;

[0041] A ninth NAND gate logic circuit has a first input terminal connected to the output terminal of the fourth inverter, a second input terminal connected to the output terminal of the fifth inverter, and an output terminal of the ninth NAND gate logic circuit serving as a second output terminal of the logic unit.

[0042] According to a third aspect of the present application, a phase-locked loop circuit is provided, comprising: a multi-mode frequency divider as disclosed in any embodiment of the present application.

[0043] According to a fourth aspect of the present application, a chip is provided, comprising one of the following:

[0044] A high-speed frequency divider as disclosed in any embodiment of the present application;

[0045] A multi-mode frequency divider as disclosed in any embodiment of the present application;

[0046] A phase-locked loop circuit as disclosed in any embodiment of the present application.

[0047] According to a fifth aspect of the present application, an electronic device is provided, including one of the following:

[0048] A high-speed frequency divider as disclosed in any embodiment of the present application;

[0049] A multi-mode frequency divider as disclosed in any embodiment of the present application;

[0050] A phase-locked loop circuit as disclosed in any embodiment of the present application;

[0051] A chip as disclosed in any embodiment of the present application.

[0052] The beneficial effects of this application include at least:

[0053] The high-speed divider, multi-mode divider, phase-locked loop circuit, chip and electronic device disclosed in the embodiments of the present application utilize a NAND gate logic circuit with a selection control terminal in conjunction with two inverters to form a latch structure in the high-speed divider, so that the signal in the high-speed divider only needs to pass through the NAND gate logic circuit and the inverter to be latched and output. Compared with the traditional solution in which the signal needs to pass through the NAND gate logic circuit first and then through the latch, the present application solution reduces the delay of the signal in the critical path of the high-speed divider by improving the structure of the high-speed divider (such as the first-stage 2 / 3 divider in the multi-mode divider), improves the speed performance of the high-speed divider, thereby being able to improve the operating speed of the multi-mode divider, and facilitating the multi-mode divider to operate at a higher operating frequency.

[0054] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A structural block diagram of a phase-locked loop circuit provided according to an embodiment of the present application is shown;

[0056] Figure 2 A schematic diagram showing the structure of a multi-mode frequency divider in the related art is shown;

[0057] Figure 3 A schematic diagram of an embodiment of a multi-mode frequency divider provided according to an embodiment of the present application is shown;

[0058] Figure 4 Show Figure 3 Schematic diagram of an embodiment of each frequency division module except the first-stage frequency division module;

[0059] Figure 5 Show Figure 3 A schematic diagram of an implementation method of the first-stage frequency division module;

[0060] Figure 6 Show Figure 3 Schematic diagram of another implementation of the first-stage frequency division module. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0062] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0063] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" herein is a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0064] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0065] Figure 1 The structure block diagram of the phase-locked loop circuit provided in the embodiment of the present application is shown as follows: Figure 1 As shown, the phase-locked loop circuit includes: a phase frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LPF) 130, a voltage controlled oscillator (VCO) 140 and a multi-mode divider (MMD) 150, wherein the phase frequency detector 110 is used to compare the phase difference between the reference frequency ref_clk and the feedback frequency; the charge pump 120 and the loop filter 130 are used to convert the phase difference generated by the phase frequency detector 110 into a control voltage for the voltage controlled oscillator 140; the voltage controlled oscillator 140 is used to output a required frequency according to the control voltage; the multi-mode divider 150 is used to generate a feedback frequency according to the output frequency of the voltage controlled oscillator 140, so as to compare it with the reference frequency ref_clk.

[0066] Figure 2 FIG. 4 shows a schematic diagram of the structure of a multi-mode frequency divider in the related art. Figure 2 As shown, in the related art, the multi-mode frequency divider is formed by cascading multiple 2 / 3 frequency division modules, from left to right, they are the first-stage 2 / 3 frequency division module (also referred to as the frequency division module in this article) 211 to the n-stage 2 / 3 frequency division module 21n, and n is an integer greater than 1. Among them, each 2 / 3 frequency division module (also referred to as the frequency division module in this article) includes a frequency division input terminal fi, a frequency division output terminal fo, a mode input terminal Mi, a mode output terminal Mo and a frequency division selection terminal P. The frequency division input terminal fi of the first-stage frequency division module 211 receives the initial signal f(in), and the frequency division input terminal fi of each stage of the frequency division module after the first-stage frequency division module 211 is connected to the frequency division output terminal fo of the previous stage of the frequency division module, so that the first down-conversion signal f(out) is generated at the frequency division output terminal fo of the n-stage frequency division module 21n. The frequency division selection terminals P of the first to n-stage frequency division modules receive frequency division selection signals P[0] to P[n-1] respectively. The mode input terminal Mi of the n-th level frequency division module 21n receives the high level signal H to ensure the realization of the 3-frequency division function. The mode input terminal Mi of each level of frequency division module before the n-th level frequency division module 21n is connected to the mode output terminal Mo of the frequency division module of the next level, thereby generating a second down-conversion signal m(out) at the mode output terminal Mo of the first level frequency division module 211.

[0067] Figure 2 In this case, the multi-mode divider can achieve a division ratio of: Based on this structure, the input signals of the frequency division selection terminals P of the following frequency division modules are controlled by different logic combinations, so that different frequency division ratios can be achieved and clock signals with different frequency division ratios can be generated. Among them, the frequency division ratio range that can be generated by the multi-mode frequency divider is: , k represents the number of bits in the multi-mode divider that do not participate in the programming of the division ratio.

[0068] Since most of the current multi-mode frequency dividers use the cascaded 2 / 3 frequency divider module, the next-stage input signal is generated by the previous-stage frequency divider, and the operating frequency decreases step by step, so the frequency divider operating frequency is limited by the performance of the first-stage 2 / 3 frequency divider. In order to better realize the application of multi-mode frequency dividers in high-speed scenarios, it is necessary to optimize the first-stage 2 / 3 frequency divider in the multi-mode frequency divider.

[0069] The present application scheme further optimizes the structure of the frequency divider and the multi-mode frequency divider, thereby providing a high-speed frequency divider, reducing the delay of the signal in the key path of the high-speed frequency divider, and improving the speed performance of the high-speed frequency divider. When the high-speed frequency divider is used as the first-stage 2 / 3 frequency divider in the multi-mode frequency divider, the operating speed of the multi-mode frequency divider is improved, and the multi-mode frequency divider can be operated at a higher operating frequency. Figure 3 , Figure 3 FIG. 1 is a schematic diagram of an embodiment of a multi-mode frequency divider provided in an embodiment of the present application. It should be noted that the multi-mode frequency divider disclosed in the embodiment of the present application can be applied to Figure 1 In addition to the phase-locked loop circuit shown in , the present invention can also be applied to any other phase-locked loop architecture including a multi-mode divider.

[0070] like Figure 3 As shown, the multi-mode frequency divider provided in the embodiment of the present application includes: n cascaded frequency division modules and a frequency division control circuit 320. Among the n cascaded frequency division modules, from left to right are the first-stage frequency division module 311 to the n-th stage frequency division module 31n, and n is an integer greater than or equal to 4. In this article, the first-stage frequency division module 311 is also called a high-speed frequency divider. The frequency division control circuit 320 receives a plurality of mode output signals, and is used to logically combine a plurality of frequency division selection signals P[0]~P[n] and a plurality of mode output signals, obtain the mode input signal of each stage frequency division module, and realize the adjustment of the system frequency division ratio. In some embodiments, the mode input signal of the n-th stage frequency division module 31n is fixed to a high-level signal H.

[0071] In this embodiment, among the n cascaded frequency division modules, each frequency division module includes a frequency division input terminal fi, a frequency division output terminal fo, a mode input terminal Mi, a mode output terminal Mo, and a frequency division selection terminal P. Among them, the frequency division input terminal fi of the first-stage frequency division module 311 receives the initial clock input signal f(in), and the frequency division input terminal fi of each level of frequency division module after the first-stage frequency division module 311 is connected to the frequency division output terminal fo of the previous level of frequency division module, so that the first down-conversion signal f(out) is generated at the frequency division output terminal fo of the n-th level frequency division module 31n. The frequency division selection terminals P of the first to n-th level frequency division modules receive frequency division selection signals P[0] to P[n-1] respectively. The mode input terminal Mi of the n-th level frequency division module 31n receives a high-level signal H to ensure the realization of the 3-division function. The mode input signal received by the mode input terminal Mi of each level of frequency division module before the n-th level frequency division module 31n is provided by the frequency division control circuit 320. For example, the mode input signal received by the mode input terminal Mi of each level of frequency division module before the n-th level frequency division module 31n is obtained by performing a logical AND-NOT processing on the mode output signal of the next level of frequency division module of the level of frequency division module and the inverted signal of the frequency division ratio selection signal of each next level of frequency division module of the level of frequency division module, thereby generating a second down-conversion signal m(out) at the mode output terminal Mo of the first level frequency division module 311 as the system output clock.

[0072] Optionally, the frequency division selection terminal P of each frequency division module in the multi-mode frequency divider provided in the embodiment of the present application can be connected to the frequency division control circuit 320, so that the frequency division control circuit 320 configures the frequency division selection terminal P of each distribution module; or, the frequency division selection terminal P of each frequency division module can also be directly used as an external terminal and manually configured. Specifically, the multi-mode frequency divider can configure the frequency division selection terminal P and the mode input terminal Mi of each frequency division module according to the desired frequency division ratio to determine the number of frequency division modules involved in the frequency division and the frequency division ratio of each frequency division module, thereby realizing the division of the clock input signal f(in) according to the desired frequency division ratio.

[0073] In a specific implementation, the frequency division control circuit 320 further includes a plurality of logic units, which are respectively connected to the mode input terminals Mi of the first-stage frequency division module 311 to the n-1-th stage frequency division module 31 (n-1), and each logic unit is used to obtain the mode input signal of the corresponding frequency division module according to the frequency division selection signals of the subsequent-stage frequency division modules of the corresponding frequency division module and the mode output signal of the subsequent-stage frequency division module of the corresponding frequency division module.

[0074] In some embodiments, reference Figure 3The logic unit 330 corresponding to the first-stage frequency division module 311 is a first logic unit, including a NAND gate logic circuit 331, a first input end of the NAND gate logic circuit 331 is connected to the mode output end Mo of the second-stage frequency division module 312, a second input end of the NAND gate logic circuit 331 is connected to the second output end of the logic unit 340 corresponding to the second-stage frequency division module 312, and an output end of the NAND gate logic circuit 331 is connected to the mode input end Mi of the first-stage frequency division module 311. Each logic unit except the first logic unit 330 among the multiple logic units includes: two NAND gate logic circuits and two inverters, wherein the first input end of the first NAND gate logic circuit is connected to the mode output end Mo of the subsequent frequency division module of the corresponding frequency division module, the second input end of the first NAND gate logic circuit is connected to the second output end of the logic unit corresponding to the subsequent frequency division module of the corresponding frequency division module, and the output end of the first NAND gate logic circuit serves as the first output end of the logic unit and is connected to the mode input end Mi of the corresponding frequency division module; the input end of the first inverter is connected to the second output end of the logic unit corresponding to the subsequent frequency division module of the corresponding frequency division module; the input end of the second inverter is connected to the frequency division selection end P of the subsequent frequency division module of the corresponding frequency division module; the first input end of the second NAND gate logic circuit is connected to the output end of the first inverter, the second input end of the second NAND gate logic circuit is connected to the output end of the second inverter, and the output end of the second NAND gate logic circuit serves as the second output end of the logic unit.

[0075] Taking the logic unit 340 corresponding to the second-stage frequency division module 312 as an example, the logic unit 340 includes two NAND gate logic circuits 341 and 342, and two inverters 343 and 344, wherein the first input end of the NAND gate logic circuit 341 is connected to the mode output end Mo of the frequency division module 313 (not shown) to receive the mode output signal m(2) (not shown), the second input end of the NAND gate logic circuit 341 is connected to the second output end of the logic unit 350 (not shown) corresponding to the frequency division module 313 (not shown), and the output end of the NAND gate logic circuit 341 serves as the first output end of the logic unit 340. The input end of the inverter 343 is connected to the second output end of the logic unit 350 (not shown) corresponding to the frequency division module 313 (not shown); the input end of the inverter 344 is connected to the frequency division selection end P of the frequency division module 313 (not shown) to receive the frequency division selection signal P[2]; the first input end of the NAND gate logic circuit 342 is connected to the output end of the inverter 343, the second input end of the NAND gate logic circuit 342 is connected to the output end of the inverter 344, and the output end of the NAND gate logic circuit 342 serves as the second output end of the logic unit 340. The structures of the remaining logic units can be deduced by analogy unless otherwise specified.

[0076] The logic unit 3(n+1)0 corresponding to the n-1th level frequency division module 31(n-1) includes two NAND gate logic circuits 3(n+1)1 and 3(n+1)2, two inverters 3(n+1)3 and 3(n+1)4, wherein the first input end of the NAND gate logic circuit 3(n+1)1 is connected to the mode output end Mo of the frequency division module 31n to receive the mode output signal m(n-1), the second input end of the NAND gate logic circuit 3(n+1)1 receives the frequency division selection signal P[n], and the output end of the NAND gate logic circuit 3(n+1)1 serves as the first output end of the logic unit 3(n+1)0 and is connected to Connected to the mode input terminal Mi of the frequency division module 31(n-1); the input terminal of the inverter 3(n+1)3 receives the frequency division selection signal P[n]; the input terminal of the inverter 3(n+1)4 is connected to the frequency division selection terminal P of the frequency division module 31n to receive the frequency division selection signal P[n-1]; the first input terminal of the NAND gate logic circuit 3(n+1)2 is connected to the output terminal of the inverter 3(n+1)3, the second input terminal of the NAND gate logic circuit 3(n+1)2 is connected to the output terminal of the inverter 3(n+1)4, and the output terminal of the NAND gate logic circuit 3(n+1)2 serves as the second output terminal of the logic unit 3(n+1)0.

[0077] The multi-mode frequency divider can be configured to generate a plurality of frequency division selection signals P[0]~P[n] and a plurality of mode input signals according to a desired frequency division ratio, and input the plurality of frequency division selection signals P[0]~P[n-1] to the frequency division selection terminals P of each frequency division module, and input the plurality of mode input signals to the mode input terminals Mi of the first-stage frequency division module to the n-1-stage frequency division module. The plurality of mode input signals can be generated by the frequency division control circuit 320 after performing logic processing on the frequency division selection signals P[0]~P[n] and the mode output signals m(1)~m(n-1) of the second-stage frequency division module to the n-stage frequency division module. Therefore, it is possible to determine to a certain extent the number of frequency division modules required to participate in the frequency division, as well as to determine whether each frequency division module participating in the frequency division implements a two-division mode or a three-division mode, and subsequently adjust the frequency division selection terminal P and the mode input terminal Mi of each frequency division module, thereby adjusting the clock path or state of each frequency division module, so that the multi-mode divider divides the clock signal to be divided according to the desired division ratio.

[0078] Exemplarily, when the multi-mode frequency divider is working, each frequency division module can realize a two-frequency division mode or a three-frequency division mode under the control of the signal received by the frequency division selection terminal P and the mode input terminal Mi. For example, when the signal of the frequency division selection terminal P is at a low level, the frequency division module of this level acts as a two-frequency division circuit. When the signal of the frequency division selection terminal P is at a high level, the frequency division ratio of the frequency division module of this level is determined by the signal of the mode input terminal Mi. When the signal of the mode input terminal Mi is at a low level, the frequency division module of this level acts as a two-frequency division circuit. When the signal of the mode input terminal Mi is at a high level, the frequency division module of this level acts as a three-frequency division circuit. Therefore, by setting the frequency division selection signals P[0]~P[n] of the multi-mode frequency divider, the input clock signal f(in) can be down-converted at different frequency division ratios, and the multi-mode frequency divider can realize a continuously variable frequency division ratio under the control of the frequency division selection signals P[0]~P[n].

[0079] refer to Figure 5 and Figure 6 Among the n cascaded frequency division modules, the first-stage frequency division module 311 includes: a latch circuit 510, a latch circuit 502, a latch circuit 503 and a latch circuit 504 in feedback cascade connection. Among them, the latch circuit 510, the latch circuit 502, the latch circuit 503 and the latch circuit 504 are all connected to the frequency division input terminal fi of the first-stage frequency division module 311 to receive the clock input signal. The first input terminal and the second input terminal of the latch circuit 510 are respectively connected to the output terminals of the latch circuit 520 and the latch circuit 540; the output terminal of the latch circuit 520 is connected to the first input terminal of the latch circuit 530 through the inverter 550. At the same time, the output terminal of the latch circuit 520 is also connected to the frequency division output terminal of the first-stage frequency division module 311. The first-stage frequency division module 311 is connected to the mode input terminal Mi of the first-stage frequency division module 311 to generate an output frequency division clock signal; the second input terminal of the latch circuit 530 is connected to the mode input terminal Mi of the first-stage frequency division module 311 to receive the mode input signal, and the output terminal of the latch circuit 530 is connected to the first input terminal of the latch circuit 540. At the same time, the output terminal of the latch circuit 530 is also connected to the mode output terminal Mo of the first-stage frequency division module 311 to output the mode output signal; the second input terminal of the latch circuit 540 is connected to the frequency division selection terminal P of the first-stage frequency division module 311 to receive the frequency division selection signal.

[0080] Latch circuit 510, latch circuit 520, latch circuit 530 and latch circuit 540 all include a gating unit and a latch unit connected to the output end of the gating unit. The gating unit in each latch circuit is used to switch between a conducting state and a non-conducting state according to an input clock signal; the latch unit in each latch circuit includes a second inverter and a third inverter, and receives an input clock signal, and is used to output the input end signal of the corresponding latch unit through the second inverter according to the input clock signal, or to latch the signal using the second inverter and the third inverter in an end-to-end state. In this article, the non-conducting state refers to a high impedance state or an off state.

[0081] exist Figure 5 In the illustrated embodiment, the gating unit in the latch circuit 510 includes a NAND gate logic circuit 511, and the latch unit in the latch circuit 510 includes an inverter 512, an inverter 513, and a transmission gate logic circuit 514. The NAND gate logic circuit 511 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal. The first input terminal of the NAND gate logic circuit 511 serves as the first input terminal of the latch circuit 510 to receive the output terminal signal of the latch circuit 520. The second input terminal of the NAND gate logic circuit 511 serves as the second input terminal of the latch circuit 510 to receive the output terminal signal of the latch circuit 540. The gating control terminal of the NAND gate logic circuit 511 is connected to the frequency division input terminal fi of the first-stage frequency division module 311 to receive the input clock signal. The output end of the NAND gate logic circuit 511 is connected to the input end of the inverter 512, the output end of the inverter 512 serves as the output end of the latch circuit 510, the input end of the inverter 513 is connected to the output end of the inverter 512, the output end of the inverter 513 is connected to the first end of the transmission gate logic circuit 514, the second end of the transmission gate logic circuit 514 is connected to the input end of the inverter 512, and the control end of the transmission gate logic circuit 514 receives an input clock signal to switch between a conductive state and a non-conductive state according to the input clock signal.

[0082] The NAND gate logic circuit 511 is used to switch to a conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and perform a NAND logic output on the signal at its first input terminal and the signal at its second input terminal, and switch to a non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives). At the same time, the transmission gate logic circuit 514 switches to a non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), so that the inverter 513 does not participate in the work, and switches to a conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), so that the inverter 512 and the inverter 513 are in a head-to-tail connection state. Furthermore, during the first level state of the input clock signal, the logic result of the NOT gate logic circuit 511 is transmitted to the latch circuit 520 via the inverter 512; during the second level state of the input clock signal, the latch circuit 510 latches the signal via the inverter 512 and the inverter 513 in the head-to-tail connection state.

[0083] exist Figure 5 In the illustrated embodiment, the gating unit in the latch circuit 520 includes a transmission gate logic circuit 521 , and the latch unit in the latch circuit 510 includes an inverter 522 , an inverter 523 , and a transmission gate logic circuit 524 . Among them, the first end of the transmission gate logic circuit 521 serves as the input end of the latch circuit 520 to receive the output end signal of the latch circuit 510, the control end of the transmission gate logic circuit 521 is connected to the frequency division input end fi of the first-stage frequency division module 311 to receive the input clock signal, the second end of the transmission gate logic circuit 521 is connected to the input end of the inverter 522, the output end of the inverter 522 serves as the output end of the latch circuit 520, the input end of the inverter 523 is connected to the output end of the inverter 522, the output end of the inverter 523 is connected to the first end of the transmission gate logic circuit 524, the second end of the transmission gate logic circuit 524 is connected to the input end of the inverter 522, and the control end of the transmission gate logic circuit 524 receives the inverted signal of the input clock signal to switch between the conductive state and the non-conductive state according to the input clock signal.

[0084] The transmission gate logic circuit 521 is used to switch to a non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and switch to a conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and output the signal at its first end to the inverter 522. At the same time, the transmission gate logic circuit 524 is switched to a conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), so that the inverter 522 and the inverter 523 are in a head-to-tail connection state, and is switched to a non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), so that the inverter 523 does not participate in the work. Furthermore, during the second level state of the input clock signal, the input signal of the latch circuit 520 is output to the inverter 550 after passing through the transmission gate logic circuit 521 and the inverter 522; during the first level state of the input clock signal, the latch circuit 520 latches the signal via the inverter 522 and the inverter 523 which are in a head-to-tail state.

[0085] exist Figure 5 In the illustrated embodiment, the gating unit in the latch circuit 530 includes a NAND gate logic circuit 531, and the latch unit in the latch circuit 530 includes an inverter 532, an inverter 533, and a transmission gate logic circuit 534. The NAND gate logic circuit 531 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal. The first input terminal of the NAND gate logic circuit 531 serves as the first input terminal of the latch circuit 530, and receives the inverted signal of the output terminal signal of the latch circuit 520 (i.e., the output terminal signal of the inverter 550). The second input terminal of the NAND gate logic circuit 531 serves as the second input terminal of the latch circuit 530, and is connected to the mode input terminal Mi of the first-stage frequency division module 311. The gating control terminal of the NAND gate logic circuit 531 is connected to the frequency division input terminal f of the first-stage frequency division module 311. i is connected to receive the input clock signal, the output end of the NAND gate logic circuit 531 is connected to the input end of the inverter 532, the output end of the inverter 532 serves as the output end of the latch circuit 530, the input end of the inverter 533 is connected to the output end of the inverter 532, the output end of the inverter 533 is connected to the first end of the transmission gate logic circuit 534, the second end of the transmission gate logic circuit 534 is connected to the input end of the inverter 532, and the control end of the transmission gate logic circuit 534 receives the input clock signal to switch between the conductive state and the non-conductive state according to the input clock signal.

[0086] The NAND gate logic circuit 531 is used to switch to the conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and perform the NAND logic output on the signal of the first input terminal and the signal of the second input terminal, and switch to the non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives). At the same time, the transmission gate logic circuit 534 switches to the non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), so that the inverter 533 does not participate in the work, and switches to the conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), so that the inverter 532 and the inverter 533 are in a head-to-tail connection state. Furthermore, during the first level state of the input clock signal, the logic result of the NOT gate logic circuit 531 is transmitted to the mode output terminal Mo of the first-stage frequency division module 311 and the latch circuit 540 via the inverter 532; during the second level state of the input clock signal, the latch circuit 530 latches the signal via the inverter 532 and the inverter 533 which are in a head-to-tail state.

[0087] exist Figure 5 In the illustrated embodiment, the gating unit in the latch circuit 540 includes a NAND gate logic circuit 541, and the latch unit in the latch circuit 540 includes an inverter 542, an inverter 543, and a transmission gate logic circuit 544. The NAND gate logic circuit 541 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal. The first input terminal of the NAND gate logic circuit 541 serves as the first input terminal of the latch circuit 540 to receive the output terminal signal of the latch circuit 530. The second input terminal of the NAND gate logic circuit 541 serves as the second input terminal of the latch circuit 540 to be connected to the frequency division selection terminal P of the first-stage frequency division module 311. The gating control terminal of the NAND gate logic circuit 541 receives the inverted signal of the input clock signal. The output end of the logic circuit 541 serves as the output end of the latch circuit 540 and is connected to the input end of the inverter 542. The input end of the inverter 543 is connected to the output end of the inverter 542. The output end of the inverter 543 is connected to the first end of the transmission gate logic circuit 544. The second end of the transmission gate logic circuit 544 is connected to the input end of the inverter 542. The control end of the transmission gate logic circuit 544 receives the inverted signal of the input clock signal to switch between the conductive state and the non-conductive state according to the input clock signal.

[0088] The NAND gate logic circuit 541 is used to switch to a non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and switch to a conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and perform a NAND logic output on the signal at its first input end and the signal at its second input end. At the same time, the transmission gate logic circuit 544 switches to a conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), so that the inverter 542 and the inverter 543 are in a head-to-tail connection state, and switches to a non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), so that the inverter 543 does not participate in the work. Furthermore, during the second level state of the input clock signal, the logic result of the NOT gate logic circuit 541 is directly transmitted to the latch circuit 510; during the first level state of the input clock signal, the latch circuit 540 latches the signal via the inverter 542 and the inverter 543 in the head-to-tail connection state.

[0089] exist Figure 6 In the illustrated embodiment, the gating unit in the latch circuit 510 includes a NAND gate logic circuit 611, and the latch unit in the latch circuit 510 includes an inverter 612 and an inverter 613. The NAND gate logic circuit 611 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal, the inverter 612 includes an input terminal and an output terminal, and the inverter 613 is a three-state inverter, that is, the inverter 613 includes an input terminal, an output terminal, and an enable control terminal. In this embodiment, the first input end of the NAND gate logic circuit 611 serves as the first input end of the latch circuit 510 to receive the output end signal of the latch circuit 520. The second input end of the NAND gate logic circuit 611 serves as the second input end of the latch circuit 510 to receive the output end signal of the latch circuit 540. The enable control end of the NAND gate logic circuit 611 is connected to the frequency division input end fi of the first-stage frequency division module 311 to receive the input clock signal. The output end of the NAND gate logic circuit 611 is connected to the input end of the inverter 612. The output end of the inverter 612 serves as the output end of the latch circuit 510. The input end of the inverter 613 is connected to the output end of the inverter 612. The output end of the inverter 613 is connected to the input end of the inverter 612. The enable control end of the inverter 613 receives the input clock signal to switch between the conductive state and the non-conductive state according to the input clock signal.

[0090] The NAND gate logic circuit 611 is used to switch to the conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and perform the NAND logic output on the signal of the first input terminal and the signal of the second input terminal, and switch to the non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives). At the same time, the inverter 613 switches to the non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and does not participate in the work, and switches to the conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and is in the end-to-end state with the inverter 612, and the output signal of the inverter 612 is inverted and output, thereby realizing signal latching. Furthermore, during the first level state of the input clock signal, the input signal of the latch circuit 510 is output to the latch circuit 520 after passing through the NAND gate logic circuit 611 and the inverter 612; during the second level state of the input clock signal, the latch circuit 510 latches the signal via the inverter 612 and the inverter 613 which are in an end-to-end state.

[0091] exist Figure 6 In the illustrated embodiment, the gating unit in the latch circuit 520 includes a transmission gate logic circuit 621, and the latch unit in the latch circuit 510 includes an inverter 622 and an inverter 623. The transmission gate logic circuit 621 includes a first terminal, a second terminal, and a control terminal, the inverter 622 includes an input terminal and an output terminal, and the inverter 623 is a three-state inverter, that is, the inverter 623 includes an input terminal, an output terminal, and an enable control terminal. In this embodiment, the first end of the transmission gate logic circuit 621 serves as the input end of the latch circuit 520 to receive the output end signal of the latch circuit 510. The control end of the transmission gate logic circuit 621 is connected to the frequency division input end fi of the first-stage frequency division module 311 to receive the input clock signal. The second end of the transmission gate logic circuit 621 is connected to the input end of the inverter 622. The output end of the inverter 622 serves as the output end of the latch circuit 520. The input end of the inverter 623 is connected to the output end of the inverter 622. The output end of the inverter 623 is connected to the input end of the inverter 622. The enable control end of the inverter 623 receives the inverted signal of the input clock signal to switch between the conductive state and the non-conductive state according to the input clock signal.

[0092] The transmission gate logic circuit 621 is used to switch to a non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and switch to a conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and output the signal at its first end to the inverter 622. At the same time, the inverter 623 switches to a conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), is in a state of end-to-end connection with the inverter 622, and inverts the output signal of the inverter 622 to output, thereby realizing signal latching, and switches to a non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and does not participate in the work. Furthermore, during the second level state of the input clock signal, the input signal of the latch circuit 520 is output to the inverter 650 after passing through the transmission gate logic circuit 621 and the inverter 622; during the first level state of the input clock signal, the latch circuit 520 latches the signal via the inverter 622 and the inverter 623 which are in an end-to-end state.

[0093] exist Figure 6 In the illustrated embodiment, the gating unit in the latch circuit 530 includes a NAND gate logic circuit 631, and the latch unit in the latch circuit 530 includes an inverter 632 and an inverter 633. The NAND gate logic circuit 631 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal, the inverter 632 includes an input terminal and an output terminal, and the inverter 633 is a three-state inverter, that is, the inverter 633 includes an input terminal, an output terminal, and an enable control terminal. In this embodiment, the first input end of the NAND gate logic circuit 631 serves as the first input end of the latch circuit 530 to receive the inverted signal of the output end signal of the latch circuit 520 (i.e., the output end signal of the inverter 650); the second input end of the NAND gate logic circuit 631 serves as the second input end of the latch circuit 530 and is connected to the mode input end Mi of the first-stage frequency division module 311; the selection control end of the NAND gate logic circuit 631 is connected to the frequency division input end fi of the first-stage frequency division module 311 to receive the input clock signal; the output end of the NAND gate logic circuit 631 is connected to the input end of the inverter 632; the output end of the inverter 632 serves as the output end of the latch circuit 530; the input end of the inverter 633 is connected to the output end of the inverter 632; the output end of the inverter 633 is connected to the input end of the inverter 632; the enable control end of the inverter 633 receives the input clock signal to switch between the conduction state and the non-conduction state according to the input clock signal.

[0094] The NAND logic circuit 631 is used to switch to the conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), perform NAND logic output on the signals at its first input terminal and the second input terminal, and switch to the non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives). At the same time, the inverter 633 switches to the non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives) and does not participate in the operation, and switches to the conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and is in a head-to-tail connection state with the inverter 632 to invert the output signal of the inverter 632, thereby realizing signal latching. Furthermore, during the first level state of the input clock signal, the logical result of the NAND logic circuit 631 is transmitted to the mode output terminal Mo of the first-stage frequency division module 311 and the latching circuit 540 through the inverter 632; during the second level state of the input clock signal, the latching circuit 330 performs signal latching through the inverters 632 and 633 in a head-to-tail connection state.

[0095] In Figure 6 In the illustrated embodiment, the gating unit in the latching circuit 540 includes a NAND logic circuit 641, and the latching unit in the latching circuit 540 includes an inverter 642 and an inverter 643. Among them, the NAND logic circuit 641 includes a first input terminal, a second input terminal, a gating control terminal, and an output terminal, the inverter 642 includes an input terminal and an output terminal, and the inverter 643 is a tri-state inverter, that is, the inverter 643 includes an input terminal, an output terminal, and an enable control terminal. In this embodiment, the first input terminal of the NAND logic circuit 641 serves as the first input terminal of the latching circuit 540 to receive the output signal of the latching circuit 530, the second input terminal of the NAND logic circuit 641 serves as the second input terminal of the latching circuit 540 and is connected to the frequency division selection terminal P of the first-stage frequency division module 311, the gating control terminal of the NAND logic circuit 641 receives the inverted signal of the input clock signal, the output terminal of the NAND logic circuit 641 serves as the output terminal of the latching circuit 540 and is simultaneously connected to the input terminal of the inverter 642, the input terminal of the inverter 643 is connected to the output terminal of the inverter 642, the output terminal of the inverter 643 is connected to the input terminal of the inverter 642, and the enable control terminal of the inverter 643 receives the inverted signal of the input clock signal to switch between the conducting state and the non-conducting state according to the input clock signal.

[0096] The NAND logic circuit 641 is used to switch to the non-conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and switch to the conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives), and perform NAND logic output on the signals at its first input terminal and the second input terminal. At the same time, the inverter 643 switches to the conducting state during the first level state of the input clock signal (such as when the rising edge of the input clock signal arrives), and is in a head-to-tail connection state with the inverter 642, and performs inverting output on the output signal of the inverter 642, thereby realizing signal latching, and switches to the non-conducting state during the second level state of the input clock signal (such as when the falling edge of the input clock signal arrives) and does not participate in the operation. Furthermore, during the second level state of the input clock signal, the logical result of the NAND logic circuit 641 is directly transmitted to the latch circuit 510; during the first level state of the input clock signal, the latch circuit 540 performs signal latching via the inverters 642 and 643 in a head-to-tail connection state.

[0097] Further, as Figure 4 shown, in the cascaded n frequency division modules, each frequency division module except the first-level frequency division module 311 includes: latches 401, 402, 403, and 404 connected in feedback cascade, and NAND logic circuits 405, 406, and 407. In this embodiment, the latches 401 and 403 are clock rising edge sampling latches, and the latches 402 and 404 are clock falling edge sampling latches, wherein the clock rising edge sampling latches and the clock falling edge sampling latches are cross-cascaded. Combining Figure 3 and Figure 4, in this embodiment, the clock input terminals CLK of the latches 401, 402, 403, and 404 are all connected to the frequency division input terminals fi of the corresponding frequency division modules to receive the input clock signal, that is, the output frequency division clock signal of the previous-stage frequency division module. The data input terminal D of the latch 401 is connected to the output terminal of the NAND logic circuit 405. The data input terminal D of the latch 402 is connected to the inverted output terminal Qb of the latch 401. The inverted output terminal Qb of the latch 402 is connected to the first input terminal of the NAND logic circuit 405. At the same time, the inverted output terminal Qb of the latch 402 is also connected to the frequency division output terminal fo of the corresponding frequency division module to generate the corresponding output frequency division clock signal. The non-inverted output terminal Q of the latch 402 is connected to the first input terminal of the NAND logic circuit 406. The second input terminal of the NAND logic circuit 406 is connected to the mode input terminal Mi of the corresponding frequency division module to receive the corresponding mode input signal. The data input terminal D of the latch 403 is connected to the output terminal of the NAND logic circuit 406. The inverted output terminal Qb of the latch 403 is connected to the first input terminal of the NAND logic circuit 407. At the same time, the first input terminal of the NAND logic circuit 407 is also connected to the mode output terminal Mo of the corresponding frequency division module to generate the corresponding mode output signal. The second input terminal of the NAND logic circuit 407 is connected to the frequency division selection terminal P of the corresponding frequency division module to receive the corresponding frequency division selection signal. The data input terminal D of the latch 404 is connected to the output terminal of the NAND logic circuit 407. The non-inverted output terminal Q of the latch 404 is connected to the second input terminal of the NAND logic circuit 405.

[0098] It can be understood that the traditional frequency division module (i.e., the traditional 2 / 3 frequency divider) mainly samples signals using the double edges (rising edge and falling edge) of the input clock signal. Its speed is mainly limited by the propagation time, setup time of the internal latch (such as the D latch, also known as the D-latch), and the delay of the NAND gate. When the signal is transmitted between the two latches in this frequency division module (clock high and low level switching), the following formula needs to be satisfied: (1),

[0099] where Tcq is the propagation time of the signal in the latch, Tsu is the setup time of the latch, and Tnand is the delay time of the NAND logic circuit.

[0100] In the high-speed frequency divider (i.e., the first-stage frequency division module) 311 in the embodiments of the present application, when the signal is transmitted between the two latch circuits in it (clock high and low level switching), the following formula needs to be satisfied: (2),

[0101] Among them, Tnand is the delay time of the NAND logic circuit with a strobe control terminal, and Tinv1 and Tinv2 are the delay times of the two inverters in the latch unit, respectively.

[0102] Comparing formula (1) and formula (2), it can be seen that Tinv1 + Tinv2 is less than Tcq + Tsu. That is, the optimization and improvement of the structure of the high-speed frequency divider (such as the first-stage 2 / 3 frequency division module in the multi-mode frequency divider) in the solution of the present application reduces the delay time when the signal is transmitted in the high-speed frequency divider, improves the speed performance of the high-speed frequency divider, and thus can improve the working speed of the multi-mode frequency divider, which is conducive to realizing the multi-mode frequency divider working at a higher working frequency.

[0103] Furthermore, an embodiment of the present application further provides a chip, which integrates one of the frequency dividers, multi-mode frequency dividers, and phase-locked loop circuits disclosed in any of the foregoing embodiments. Exemplarily, the chip includes, but is not limited to, a digital signal processor (DSP) chip, a communication chip, a microcontroller (MCU) chip, a field programmable gate array (FPGA) chip, a complex programmable logic device (CPLD) chip, etc.

[0104] Furthermore, an embodiment of the present application further provides an electronic device, which includes one of the frequency dividers, multi-mode frequency dividers, phase-locked loop circuits, and chips disclosed in any of the foregoing embodiments. Exemplarily, the electronic device includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, a desktop computer, a digital camera, a game console (such as PlayStation, Xbox, Nintendo Switch), a television, a wireless router, a Bluetooth headset, a smart watch, a drone, a smart home device (such as a smart speaker, a smart bulb, a smart socket), an e-book reader, a Bluetooth keyboard and mouse, a health device such as an electronic sphygmomanometer, a weighing scale, etc.

[0105] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present application, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A high-speed frequency divider, comprising: a first latch circuit, a second latch circuit, a third latch circuit and a fourth latch circuit; The first latch circuit, the second latch circuit, the third latch circuit and the fourth latch circuit each include a gating unit and a latch unit connected to an output end of the gating unit; The gating unit is used to switch between a conducting state and a non-conducting state according to an input clock signal; The latch unit includes a second inverter and a third inverter, and the latch unit is used to output the input terminal signal through the second inverter according to the input clock signal, or to latch the signal by using the second inverter and the third inverter in an end-to-end state; Wherein, the gating unit in the first latch circuit comprises: A first NAND gate logic circuit includes a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal receives the output terminal signal of the second latch circuit, the second input terminal receives the output terminal signal of the fourth latch circuit, and the gating control terminal receives the input clock signal. The first NAND gate logic circuit is used to switch to a conducting state during a first level state of the input clock signal, and to switch to a non-conducting state during a second level state of the input clock signal.

2. The high-speed frequency divider according to claim 1, wherein: The latch unit further includes: a transmission gate logic circuit connected in series with the third inverter between the output terminal and the input terminal of the second inverter, the transmission gate logic circuit switching between a conducting state and a non-conducting state according to the input clock signal; Wherein, when the transmission gate logic circuit is in the on state, the second inverter and the third inverter are in an end-to-end connection state; When the transmission gate logic circuit is in a non-conducting state, the third inverter does not participate in the operation.

3. The high-speed frequency divider according to claim 1, wherein: The second inverter and the third inverter each include an input terminal and an output terminal, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the input terminal of the second inverter; The third inverter also includes an enable control terminal. During the period when the signal at the enable control terminal is in the second level state, the third inverter inverts and outputs the output signal of the second inverter. During the period when the signal at the enable control terminal is in the first level state, the third inverter does not participate in the operation.

4. The high-speed frequency divider according to claim 1, wherein: The gating unit in the second latch circuit includes: a transmission gate logic circuit, the input end of which is connected to the output end of the first latch circuit, and switches between a conducting state and a non-conducting state according to the input clock signal, The transmission gate logic circuit is in a conducting state during a second level state of the input clock signal, and is in a non-conducting state during a first level state of the input clock signal.

5. The high-speed frequency divider according to claim 1, wherein: The gating unit in the third latch circuit comprises: The second NAND gate logic circuit includes a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal of the second NAND gate logic circuit receives an inverted signal of the output terminal signal of the second latch circuit, the second input terminal of the second NAND gate logic circuit receives a mode input signal, the gating control terminal of the second NAND gate logic circuit receives the input clock signal, and the second NAND gate logic circuit is used to switch to a conducting state during a first level state of the input clock signal, and to switch to a non-conducting state during a second level state of the input clock signal.

6. The high-speed frequency divider according to claim 1, wherein: The gating unit in the fourth latch circuit comprises: A third NAND gate logic circuit comprises a first input terminal, a second input terminal, a gating control terminal and an output terminal, wherein the first input terminal of the third NAND gate logic circuit receives the output terminal signal of the third latch circuit, the second input terminal of the third NAND gate logic circuit receives the frequency division selection signal, the gating control terminal of the third NAND gate logic circuit receives the inverted signal of the input clock signal, and the third NAND gate logic circuit is used to switch to a conducting state during the second level state of the input clock signal, and to switch to a non-conducting state during the first two level states of the input clock signal.

7. A multi-mode frequency divider, comprising: n cascaded frequency division modules, wherein the first-stage frequency division module of the n cascaded frequency division modules adopts the high-speed frequency divider according to any one of claims 1 to 6, and n is an integer greater than or equal to 4; The frequency division control circuit logically combines a plurality of frequency division selection signals and a plurality of mode output signals to obtain mode input signals of frequency division modules at each level.

8. The multi-mode frequency divider according to claim 7, wherein: Among the n cascaded frequency division modules, each frequency division module except the first-stage frequency division module comprises: a fourth NAND gate logic circuit, a fifth NAND gate logic circuit, and a sixth NAND gate logic circuit; A first latch, wherein a clock input terminal receives an input clock signal, and a data input terminal is connected to an output terminal of the fourth NAND gate logic circuit; A second latch, wherein a clock input terminal receives the input clock signal, a data input terminal is connected to an inverting output terminal of the first latch, an inverting output terminal of the second latch is connected to a first input terminal of the fourth NAND gate logic circuit, and an output frequency-divided clock signal is generated simultaneously, a non-inverting output terminal of the second latch is connected to a first input terminal of the fifth NAND gate logic circuit, and a second input terminal of the fifth NAND gate logic circuit receives a mode input signal; A third latch, wherein the clock input terminal receives the input clock signal, the data input terminal is connected to the output terminal of the fifth NAND gate logic circuit, the inverting output terminal of the third latch is connected to the first input terminal of the sixth NAND gate logic circuit, and a mode output signal is generated at the same time, and the second input terminal of the sixth NAND gate logic circuit receives the frequency division selection signal; The fourth latch has a clock input terminal receiving the input clock signal, a data input terminal connected to the output terminal of the sixth NAND gate logic circuit, and a non-inverting output terminal of the fourth latch connected to the second input terminal of the fourth NAND gate logic circuit.

9. The multi-mode frequency divider according to claim 7, wherein: The frequency division control circuit comprises: Multiple logic units are respectively connected to the mode input terminals of the first-level frequency division module to the n-1-th level frequency division module, and each logic unit is used to obtain the mode input signal of the corresponding frequency division module according to the frequency division selection signals of each subsequent level frequency division module of the corresponding frequency division module and the mode output signal of the subsequent level frequency division module of the corresponding frequency division module.

10. The multi-mode frequency divider according to claim 9, wherein: The logic unit corresponding to the first-stage frequency division module is a first logic unit, comprising a seventh NAND gate logic circuit, wherein a first input end of the seventh NAND gate logic circuit is connected to a mode output end of the second-stage frequency division module, a second input end is connected to a second output end of the logic unit corresponding to the second-stage frequency division module, and an output end of the seventh NAND gate logic circuit is connected to a mode input end of the first-stage frequency division module; Each of the plurality of logic units except the first logic unit comprises: an eighth NAND gate logic circuit, wherein the first input end is connected to the mode output end of the subsequent frequency division module of the corresponding frequency division module, the second input end is connected to the second output end of the logic unit corresponding to the subsequent frequency division module of the corresponding frequency division module, the output end of the eighth NAND gate logic circuit serves as the first output end of the logic unit and is connected to the mode input end of the corresponding frequency division module; A fourth inverter, an input end of which is connected to a second output end of a logic unit corresponding to a subsequent frequency division module of the corresponding frequency division module; A fifth inverter, an input end of which is connected to a frequency division selection end of a subsequent frequency division module of the corresponding frequency division module; A ninth NAND gate logic circuit has a first input terminal connected to the output terminal of the fourth inverter, a second input terminal connected to the output terminal of the fifth inverter, and an output terminal of the ninth NAND gate logic circuit serving as a second output terminal of the logic unit.

11. A phase-locked loop circuit, comprising: A multimode frequency divider as claimed in any one of claims 7 to 10.

12. A chip comprising one of the following: The high-speed frequency divider as claimed in any one of claims 1 to 6; The multimode frequency divider as claimed in any one of claims 7 to 10; The phase locked loop circuit as claimed in claim 11.

13. An electronic device comprising one of the following: The high-speed frequency divider as claimed in any one of claims 1 to 6; The multimode frequency divider as claimed in any one of claims 7 to 10; The phase-locked loop circuit as claimed in claim 11; The chip as claimed in claim 12.

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