Dynamic device matching device and method suitable for high-precision digital-to-analog converter

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a dynamic device matching device and method suitable for a high-precision digital-to-analog converter. An input signal is received by setting a pointer updating unit; determining the end position of the pointer according to the input signal and the initial position of the pointer; the n DAC control units are respectively connected with the pointer updating unit; each DAC control unit comprises a comparison unit, a sorting storage unit and a sorting updating unit; the sorting storage unit is used for storing the current sorting sequence number of the DAC control unit; the comparison unit is used for comparing the current sorting sequence number with the target sorting sequence numbers indicated by the starting position and the ending position respectively; determining an output signal of the DAC control unit based on the comparison result; the sorting updating unit is used for updating the current sorting sequence number based on the comparison result so as to be subjected to delayed selection when the input signal is received next time under the condition that the DAC control unit is selected this time; the shaping capability can be improved, and the hardware implementation complexity is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and particularly to a dynamic device matching device and method applicable to a high-precision digital-to-analog converter. Background Art

[0002] The selection logic circuit of a digital-to-analog converter (DAC) is a digital logic circuit. Its core function is to generate multiple control signals of 0 or 1 according to the input multi-bit digital signal, so as to ensure that the sum of these signals is equal to the value of the input signal, thereby controlling the output of the multi-path feedback DAC. Specifically, the output of each DAC selection logic circuit has two states of 0 or 1. When a digital value is input to the selection logic circuit, the selection logic circuit will select a corresponding number of selection logic circuit outputs to be 1, and the rest to be 0, so as to achieve high-precision digital-to-analog conversion. For example, if the input is 3, then three selection logic circuit outputs are 1, and the rest are 0, and the sum of these 1s is equal to the input 3.

[0003] The selection logic circuit of the DAC is often used in the multi-path feedback DAC of a high-precision oversampling analog-to-digital converter (ADC) to implement the conversion function of the ADC. Due to the deviation (device mismatch error) between the actual output value and the designed value of each path of the DAC in the actual circuit design, the output signal of the multi-path DAC deviates from the designed value, which will cause a significant decrease in the signal-to-noise and distortion ratio (SNDR) and the spurious free dynamic range (SFDR) of the ADC conversion. To avoid this problem, currently, the device mismatch error is generally reduced by calibrating or optimizing the selection logic circuit.

[0004] Dynamic element matching (DEM) is an idea of using the selection logic circuit to solve the device mismatch error in the oversampling ADC and affect the in-band SNDR and SFDR problems. Specifically, the dynamic device matching technology can achieve the shaping and suppression of the in-band mismatch error of the signal by controlling the selection order of the DACs with the same output weight.

[0005] Traditional dynamic device matching technologies include the following:

[0006] The first one: Data Weighted Averaging (DWA), which is a common dynamic device matching technology. It controls the selection order of the DACs, sequentially selects each DAC, thereby ensuring that the selection times of each DAC are equal, and can achieve first-order error shaping of the device mismatch error in the DAC, reducing the influence of the in-band mismatch error of the signal.

[0007] However, the DWA technology has the problem of weak shaping ability and will introduce high-order harmonic distortion under small signals. Therefore, in high-precision ADC applications, the mismatch error of the DAC control unit using DWA is still the main factor restricting the ADC SNDR and SFDR.

[0008] The second one: High-order dynamic device matching technology. It can achieve high-order device mismatch error shaping through a complex vector quantization logic circuit. Its DAC selection order has the characteristic of First-In-Last-Out. While ensuring the balance of the selection times of each DAC, it makes the previously preferred DAC have a lower selection priority, and the DACs with a later selection order are preferentially selected. In this way, the randomness is stronger, no high-order harmonic distortion will be generated, and the shaping and suppression ability of the mismatch error is also stronger.

[0009] However, the logic implementation of the high-order dynamic device matching technology is extremely complex. Under the same number of DACs, the hardware overhead of the high-order dynamic device matching technology is dozens to hundreds of times that of DWA. Therefore, its application in high-precision oversampling ADCs is not extensive. Summary of the Invention

[0010] In view of this, the present disclosure proposes a dynamic device matching device and method applicable to high-precision digital-to-analog converters, which can solve the problems that the traditional DWA circuit has poor shaping ability and signal harmonic distortion under low-signal input, and the logic implementation design complexity of the traditional high-order dynamic device matching technology is too high, resulting in large power consumption and area in practical applications and being unable to be applied to industrial products.

[0011] According to one aspect of the present disclosure, there is provided a dynamic device matching device applicable to a high-precision digital-to-analog converter, and the device includes:

[0012] A pointer update unit, configured to: receive an input signal; determine an end position of the pointer according to the input signal and a start position of the pointer stored in advance; the start position and the end position are used to indicate the target sorting serial numbers of the DAC control units selected this time;

[0013] n DAC control units, each connected to the pointer update unit; each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit; n is an integer greater than 1;

[0014] The sorting storage unit is configured to: store the current sorting sequence number of the DAC control unit, where the current sorting sequence number is used to indicate the sorting order of the DAC control unit among the n DAC control units;

[0015] The comparison unit is configured to: compare the current sorting sequence number with the target sorting sequence number indicated by the start position and the target sorting sequence number indicated by the end position respectively to obtain a comparison result; determine the output signal of the DAC control unit based on the comparison result;

[0016] The sorting update unit is configured to update the current sorting sequence number based on the comparison result, so that in the case where the DAC control unit is selected this time, it will be selected later when receiving an input signal next time.

[0017] In a possible implementation, the pointer update unit is further configured to: determine whether the sum result of the input signal and the start position overflows; in the case of overflow, subtract n from the sum result to obtain the end position;

[0018] Correspondingly,

[0019] The comparison unit is configured to: determine the output signal of the DAC control unit based on the comparison result and the determination result of whether there is an overflow;

[0020] The sorting update unit is configured to: update the current sorting sequence number based on the comparison result and the determination result of whether there is an overflow.

[0021] In a possible implementation, the sorting update unit is configured to:

[0022] In the case where the sum result does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the start position, and the current sorting sequence number is less than the target sorting sequence number indicated by the end position, subtract the target sorting sequence number indicated by the start position from the current sorting sequence number of the DAC control unit to obtain the updated sorting sequence number;

[0023] In the case where the sum result does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the start position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the end position, keep the current sorting sequence number of the DAC control unit unchanged;

[0024] When the sum result does not overflow, the current sorting sequence number of the DAC control unit is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, add the value indicated by the input signal to the current sorting sequence number of the DAC control unit to obtain an updated sorting sequence number;

[0025] When the sum result overflows, the current sorting sequence number of the DAC control unit is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, add n minus the target sorting sequence number indicated by the starting position to the current sorting sequence number of the DAC control unit to obtain an updated sorting sequence number;

[0026] When the sum result overflows, the current sorting sequence number of the DAC control unit is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, keep the current sorting sequence number of the DAC control unit unchanged;

[0027] When the sum result overflows, the current sorting sequence number of the DAC control unit is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, add the difference obtained by subtracting n from the value indicated by the input signal to the current sorting sequence number of the DAC control unit to obtain an updated sorting sequence number.

[0028] In a possible implementation manner, the sorting update unit includes: a first adder, a first data selector and a first register respectively connected to the input end of the first adder, and a second data selector and a third data selector respectively connected to the first data selector; the output end of the first adder is connected to the input end of the first register;

[0029] The first register is used to store the current sorting sequence number;

[0030] The first data selector is used to connect to the second data selector through the first input end when the sum result overflows; and connect to the third data selector through the second input end when the sum result does not overflow;

[0031] The second data selector includes a first data input end, a second data input end and a third data input end; the first data input end is used to input the difference obtained by subtracting n from the value indicated by the input signal to the second data selector; the second data input end is used to input the difference of n minus the target sorting sequence number indicated by the starting position to the second data selector; the third data input end is used to input 0 to the second data selector;

[0032] The third data selector includes a fourth data input terminal, a fifth data input terminal, and a sixth data input terminal; the fourth data input terminal is used to input 0 to the second data selector; the fifth data input terminal is used to input the negative value of the target sorting sequence number indicated by the starting position to the second data selector; the sixth data input terminal is used to input the value indicated by the input signal to the second data selector.

[0033] In a possible implementation, the comparison unit is configured to:

[0034] When the sum result overflows, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, determine that the output signal is 1;

[0035] Or,

[0036] When the sum result overflows, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, determine that the output signal is 1;

[0037] Or,

[0038] When the sum result does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, determine that the output signal is 1.

[0039] In a possible implementation, when the sum result overflows, the first output terminal of the pointer update unit outputs 1, and when the sum result does not overflow, the first output terminal of the pointer update unit outputs 0; correspondingly,

[0040] The comparison unit includes a first comparator, a second comparator, and an exclusive OR gate;

[0041] The first comparator is configured to output 1 when the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and output 0 when the current sorting sequence number is less than the target sorting sequence number indicated by the starting position;

[0042] The second comparator is configured to output 1 when the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, and output 0 when the current sorting sequence number is less than the target sorting sequence number indicated by the ending position;

[0043] The exclusive OR gate is respectively connected to the first comparator, the second comparator, and the first output terminal; the exclusive OR gate is configured to output 0 or 1 based on the first comparison result, the second comparison result, and the determination result output from the first output terminal.

[0044] In a possible implementation, the pointer update unit includes a second adder and a second register;

[0045] The second register is configured to store the starting position of the pointer;

[0046] The second adder includes a signal input terminal and a pointer input terminal. The signal input terminal is configured to input the input signal to the second adder; the pointer input terminal is connected to the output terminal of the second register to input the starting position stored in the second register to the second adder; the second adder further includes a first output terminal and a second output terminal. The first output terminal is configured to output a determination result of whether there is an overflow; the second output terminal is configured to output the ending position.

[0047] In a possible implementation, the second output terminal is connected to the input terminal of the second register to store the ending position, so that in the case of receiving the input signal next time, the ending position is used as the starting position of the pointer corresponding to the next input signal, and the ending position of the pointer corresponding to the next input signal is determined.

[0048] In a possible implementation, each DAC control unit further includes a reset unit, configured to: update the current sorting sequence number stored in the sorting storage unit to a preset value when receiving a reset signal, and the preset values corresponding to different DAC control units are different.

[0049] According to another aspect of the present disclosure, a dynamic device matching method applicable to a high-precision digital-to-analog converter is provided. The method includes:

[0050] Receiving an input signal;

[0051] Determining the ending position of the pointer according to the input signal and the starting position of the pre-stored pointer; the starting position and the ending position are used to indicate the target sorting sequence number of the DAC control unit selected this time;

[0052] For each DAC control unit, comparing the current sorting sequence number corresponding to the DAC control unit with the target sorting sequence number indicated by the starting position and the target sorting sequence number indicated by the ending position respectively to obtain a comparison result; wherein, the current sorting sequence number is used to indicate the sorting order of the DAC control unit among n DAC control units;

[0053] Determine the output signal of the DAC control unit based on the comparison result, and update the current sorting sequence number, so that in the case where the DAC control unit is selected this time, it will be selected later when the input signal is received next time.

[0054] By setting a pointer update unit for: receiving an input signal; determining the end position of the pointer according to the input signal and the starting position of the pre-stored pointer; and n DAC control units, respectively connected to the pointer update unit; each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit; the sorting storage unit is used for: storing the current sorting sequence number of the DAC control unit, and the current sorting sequence number is used to indicate the sorting order of the DAC control unit among the n DAC control units; the comparison unit is used for: comparing the current sorting sequence number with the target sorting sequence number indicated by the starting position and the target sorting sequence number indicated by the ending position respectively to obtain a comparison result; determining the output signal of the DAC control unit based on the comparison result; the sorting update unit is used for updating the current sorting sequence number based on the comparison result, so that in the case where the DAC control unit is selected this time, it will be selected later when the input signal is received next time; on the one hand, compared with the traditional digital weighted average circuit, this dynamic device matching device adopts the design idea of last-in-first-out, making the selection result of the DAC control unit similar to the selection result of the high-order DEM. Therefore, the shaping ability is similar to that of the high-order DEM, the shaping ability is strong, and the harmonic suppression ability is extremely strong, which can solve the problem of poor shaping ability of the traditional data weighted average circuit; on the other hand, compared with the high-order DEM, the sorting update unit of this dynamic device matching device can directly operate the current sorting sequence number of each DAC control unit, without the complex digital filtering circuit and comparison sorting circuit in the traditional high-order DEM. Therefore, the hardware implementation complexity is low, which can solve the problem that the logic circuit of the high-order DEM is complex to implement and cannot be widely applied.

[0055] In addition, the dynamic device matching device provided by the present application can be used in high-precision oversampling ADC and DAC control unit products. This solution has extremely low power consumption and area overhead, and the digital logic of this solution has good process compatibility. Its power consumption and area advantages will be further improved in advanced processes. Therefore, it can be conveniently integrated into the ADC and DAC control unit modules to assist the ADC and DAC control units to achieve the index requirements of low power consumption and high linearity in advanced processes, and further improve the versatility of the dynamic device matching device.

[0056] According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. Description of the Drawings

[0057] The accompanying drawings that are included in and form a part of the specification illustrate exemplary embodiments, features, and aspects of the present disclosure, and are used to explain the principles of the present disclosure together with the specification.

[0058] Figure 1 A block diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter according to an embodiment of the present disclosure;

[0059] Figure 2 A schematic diagram showing a logic circuit implementation of a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter according to an embodiment of the present disclosure;

[0060] Figure 3 A schematic diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter selecting a DAC control unit according to an embodiment of the present disclosure;

[0061] Figure 4 A schematic diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter updating the current sorting sequence number of a DAC control unit according to an embodiment of the present disclosure;

[0062] Figure 5 A schematic diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter updating the current sorting sequence number of a DAC control unit according to another embodiment of the present disclosure;

[0063] Figure 6 A schematic diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter selecting a DAC control unit and updating the current sorting sequence number of the DAC control unit according to an embodiment of the present disclosure;

[0064] Figure 7 A schematic diagram showing the selection results of the present application, a digital weighted average circuit, and a second-order DEM according to an embodiment of the present disclosure;

[0065] Figure 8 A schematic diagram showing the comparison output spectrum of the shaping mismatch error of the present application, a digital weighted average circuit, and a second-order DEM according to an embodiment of the present disclosure;

[0066] Figure 9 A flowchart showing a dynamic device matching method applicable to a high-precision digital-to-analog converter according to an embodiment of the present disclosure. Detailed Embodiments

[0067] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0068] As used herein, the terms "comprising," "including," "having," or variations thereof are open-ended and include one or more stated features, wholes, elements, steps, components, or functions, but do not preclude the presence or addition of one or more other features, wholes, elements, steps, components, functions, or groups thereof.

[0069] When an element is referred to as being "connected," "coupled," "responsive," or variations thereof to another element, it can be directly connected, coupled, or responsive to the other element, or intervening elements may be present.

[0070] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0071] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment illustrated herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0072] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0073] Figure 1 A block diagram showing a dynamic device matching apparatus applicable to a high-precision digital-to-analog converter according to an embodiment of the present disclosure. The selection idea of the selection DAC of the dynamic device matching apparatus includes:

[0074] 1. The number of DACs selected from all DACs is the same as the magnitude of the input signal. The selected DACs output 1, and the unselected DACs output 0;

[0075] 2. For different DACs, if the selection times of the DACs are different, the DACs with fewer selection times are preferentially selected; if the selection times of the DACs are the same, the DACs that were selected later in the previous selection process are preferentially selected, that is, it has the selection characteristic of last-in-first-out. In this way, the idea of variable DAC selection priority can reduce the output nonlinearity caused by DAC device mismatch errors.

[0076] Based on the above selection idea, as Figure 1As shown, the device includes: a pointer update unit 110 and n DAC control units 120. Here, n is an integer greater than 1. Exemplarily, n is a multiple of 2.

[0077] The pointer update unit 110 is used to update the position of the pointer. The pointer is used to indicate the sorting serial number of the currently selected DAC control unit 120. In this embodiment, each of the n DAC control units 120 corresponds to a sorting serial number, and the sorting serial numbers corresponding to different DAC control units 120 are different. The pointer moves sequentially according to this sorting serial number. For example: if the number of DAC control units 120 is 8, and the sorting serial numbers corresponding to the 8 DAC control units 120 are 0 to 7 respectively, then the pointer can move sequentially from 0 to 7, and after reaching 7, it can return to 0 and move sequentially again.

[0078] In one example, the pointer update unit 110 is used to: receive an input signal; determine the end position of the pointer according to the input signal and the starting position of the pointer stored in advance. Here, the starting position and the end position are used to indicate the target sorting serial number of the currently selected DAC control unit.

[0079] The input signal is used to indicate the number of DAC control units that output 1 this time, that is, the value of the input signal is less than or equal to n.

[0080] Exemplarily, the pointer update unit 110 sums the input signal and the starting position of the pointer to obtain the end position of the pointer. Correspondingly, the pointer update unit 110 is further used to: determine whether the summation result of the input signal and the starting position overflows; in the case of overflow, subtract n from the summation result to obtain the end position.

[0081] The summation result overflow means that: the summation result is greater than the maximum sorting serial number. At this time, the pointer needs to return to the position of the first sorting serial number (for example, return to 0) and move sequentially again.

[0082] Still taking the number of DAC control units 120 being 8 and the corresponding sorting serial numbers being 0 to 7 as an example, if the summation result of the starting position of the pointer and the input signal is greater than 7, for example, the summation result is 10, then 8 needs to be subtracted from the summation result, and the obtained end position is 10 - 8 = 2.

[0083] Exemplarily, referring to Figure 2 the schematic diagram of the logic circuit implementation of the shown dynamic device matching device, this logic circuit is similar to the digital weighted average algorithm, and uses a pointer that continuously updates the integral input signal to save the number of DAC control units 120 that have been selected and output 1 in each round of selection. As Figure 2 shown, the pointer update unit 110 includes a second adder 210 and a second register 220.

[0084] The second register 220 is used to store the starting position of the pointer.

[0085] The second adder 210 includes: a signal input terminal and a pointer input terminal. The signal input terminal is used to input the above input signal D to the second adder 210 in ; The pointer input terminal is connected to the output terminal (i.e., the data output pin Q) of the second register 220 to input the starting position PT stored in the second register 220 to the second adder 210.

[0086] The second adder 210 further includes: a first output terminal and a second output terminal. The first output terminal is used to output the determination result C0 of whether there is an overflow; the second output terminal is used to output the end position PTN.

[0087] Optionally, the second output terminal is connected to the input terminal (i.e., the data input pin D) of the second register 220 to store the end position, so that in the case of receiving an input signal next time, the end position is used as the starting position of the pointer corresponding to the next input signal to determine the end position of the pointer corresponding to the next input signal. That is, when receiving an input signal next time, the data received by the pin D is latched to the pin Q to determine the end position of the pointer corresponding to the next input signal.

[0088] In other embodiments, the pointer update unit 110 may further include a third register for storing the end position and storing the end position to the second register 220 when receiving an input signal next time.

[0089] Optionally, the number of bits of the second register 220 and the second adder 210 is determined based on the value of n. Exemplarily, the number of bits of the second register 220 and the second adder 210 is m, 2 m = n.

[0090] Optionally, the second register 220 further includes a clock synchronization pin CLK to ensure the operation synchronization between the various units in the dynamic device matching device.

[0091] n DAC control units 120 are respectively connected to the pointer update unit 110 to receive the input signal D received by the pointer update unit 110 in , the starting position PT stored in the second register 220 in the pointer update unit 110, the end position PTN output by the second adder 210, and the determination result C0 of whether there is an overflow.

[0092] Inside each DAC control unit 120 is a finite state machine. That is, the DAC control unit 120 can update the sorting order of the DAC control unit 120 according to the output result each time, so as to implement the selection logic of the DAC control unit 120 in a last-in-first-out manner. Among them, the selection logic of the last-in-first-out DAC control unit 120 means: preferentially selecting the DAC control unit 120 that was selected later in the previous selection process.

[0093] Exemplarily, the finite state machine in each DAC control unit 120 includes: a comparison unit 121, a sorting storage unit 122, and a sorting update unit 123.

[0094] The sorting storage unit 122 is used to: store the current sorting serial number of the DAC control unit 120, and the current sorting serial number is used to indicate the sorting order of the DAC control unit 120 among n DAC control units 120.

[0095] The comparison unit 121 is used to: compare the current sorting serial number with the target sorting serial number indicated by the starting position and the target sorting serial number indicated by the ending position respectively to obtain a comparison result; determine the output signal of the DAC control unit 120 based on the comparison result.

[0096] Optionally, the output end of each DAC control unit 120 is used to connect to a DAC. At this time, the output signal (i.e., the digital signal) output by the DAC control unit 120 is used to control the output of the corresponding DAC. Thus, by selecting the DAC control unit 120, the selection of the DAC is realized. For example, when the DAC control unit 120 outputs 1 to the DAC connected to it, it means that the DAC is selected; when the DAC control unit 120 outputs 0 to the DAC connected to it, it means that the DAC is not selected.

[0097] When the sum result of the starting position and the input signal does not overflow, if the current sorting serial number is between the target sorting serial number indicated by the starting position and the target sorting serial number indicated by the ending position (for example, between the target sorting serial number indicated by the starting position and the target sorting serial number indicated by the position before the ending position), it means that the current sorting serial number is the DAC control unit 120 that needs to output 1 selected by the pointer this time. Correspondingly, the output signal is 1; if the current sorting serial number exceeds the range between the target sorting serial number indicated by the starting position and the target sorting serial number indicated by the ending position, it means that the current sorting serial number is not the DAC control unit 120 that needs to output 1 selected by the pointer this time. Correspondingly, the output signal is 0.

[0098] For example: Refer to Figure 3 , assuming n = 8, the current sorting serial numbers Rank 1 ~Rank8 They are 4, 5, 0, 1, 2, 3, 6, and 7 respectively. If the pointer moves sequentially in the direction of increasing sorting sequence numbers, then according to the differences in the currently saved sorting sequence numbers in the 8 DAC control units 120, the Ranks of the 8 DAC control units 120 1 ~Rank 8 can be arranged into a selection sequence from left to right. If the starting position PT stored in the second register 220 is 0, when the input signal is 4, it means that 4 DAC control units 120 need to be selected, and the pointer needs to move 4 times starting from the starting position. That is, the pointer moves from 0 to 4, and the DAC control units 120 with the current sorting sequence numbers of 0, 1, 2, and 3 respectively (i.e., E3, E4, E5, and E6) are the selected DAC control units 120 that need to output 1. In this example, taking the sorting sequence number starting from 0 and the pointer moving in ascending order of the sorting sequence number as an example for illustration, in actual implementation, the sorting sequence number of the DAC control unit 120 can also start from 1, and the pointer moves in descending order of the sorting sequence number. The specific implementation principle is the same, and it can be adaptively adjusted according to the principle of first in last out when the sorting sequence number is updated.

[0099] In the case where the sum of the starting position and the input signal overflows, the end position is before the starting position. At this time, the sorting sequence numbers between the end position and the starting position are no longer the target sorting sequence numbers. At this time, the comparison unit 121 also needs to determine the output signal in combination with the determination result of whether there is an overflow. That is, the comparison unit 121 is used to: determine the output signal of the DAC control unit 120 based on the comparison result and the determination result of whether there is an overflow.

[0100] Exemplarily, the comparison unit 121 is used to: determine that the output signal is 1 when the sum overflows, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the end position; or, determine that the output signal is 1 when the sum overflows, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the end position; or, determine that the output signal is 1 when the sum does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the end position.

[0101] Accordingly, when the sum result overflows, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, the output signal is determined to be 0; or, when the sum result does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, the output signal is determined to be 0; or, when the sum result does not overflow, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, the output signal is determined to be 0.

[0102] To implement the comparison logic of the above-mentioned comparison unit 121, refer to Figure 2 the schematic diagram of the logic circuit implementation of the dynamic device matching device shown in the figure. Assume that when the sum result overflows, the first output terminal of the pointer update unit 110 outputs 1, and when the sum result does not overflow, the first output terminal of the pointer update unit 110 outputs 0; as Figure 2 shown in the figure, the comparison unit 121 includes a first comparator 1211, a second comparator 1212, and an exclusive OR gate 1213.

[0103] The first comparator 1211 includes two input terminals and one output terminal. Among them, the two input terminals of the first comparator 1211 respectively input the current sorting sequence number Rank i of the DAC control unit 120 and the starting position PT to compare whether the current sorting sequence number Rank i is greater than the target sorting sequence number indicated by the starting position PT. The output terminal of the first comparator 1211 is used to output the comparison result C1. The first comparator 1211 is used to: when the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, output 1, that is, C1 is 0; when the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, output 0, that is, C1 is 0.

[0104] The second comparator 1212 includes two input terminals and one output terminal. Among them, the two input terminals of the second comparator 1212 respectively input the current sorting sequence number Rank i of the DAC control unit 120 and the ending position PTN to compare whether the current sorting sequence number Rank i is greater than the target sorting sequence number indicated by the ending position PTN. The output terminal of the second comparator 1212 is used to output the comparison result C2. The second comparator 1212 is used to: when the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, output 1, that is, C2 is 1; when the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, output 0, that is, C2 is 0.

[0105] The exclusive-OR unit 1213 is respectively connected to the first comparator 1211, the second comparator 1212, and the first output terminal. The exclusive-OR unit 1213 is configured to output 0 or 1 based on the first comparison result C1, the second comparison result C2, and the determination result C0 output from the first output terminal.

[0106] According to the exclusive-OR calculation logic, when C0 = 1, C1 = 1, and C2 = 1, that is, when the summation result overflows, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position. At this time, the exclusive-OR value SV i is 1, which conforms to the comparison logic of the above-mentioned comparison unit 121.

[0107] When C0 = 1, C1 = 0, and C2 = 0, that is, when the summation result overflows, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position. At this time, the exclusive-OR value SV i is 1, which conforms to the comparison logic of the above-mentioned comparison unit 121.

[0108] When C0 = 0, C1 = 1, and C2 = 0, that is, when the summation result does not overflow, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position. At this time, the exclusive-OR value SV i is 1, which conforms to the comparison logic of the above-mentioned comparison unit 121.

[0109] It should be noted that since when the summation result does not overflow, there is no situation where the current sorting sequence number is less than the target sorting sequence number indicated by the starting position and greater than the target sorting sequence number indicated by the ending position, and when the summation result overflows, there is no situation where the current sorting sequence number is less than the target sorting sequence number indicated by the starting position and greater than or equal to the target sorting sequence number indicated by the ending position. Therefore, when determining the output signal, these two situations do not need to be considered.

[0110] To ensure that each DAC control unit 120 satisfies the last-in-first-out selection logic after this selection, it is also necessary to update the current sorting sequence number currently stored in the DAC control unit 120 for use when receiving an input signal next time.

[0111] In this embodiment, the sorting update unit 123 is configured to update the current sorting sequence number based on the comparison result, so that when the DAC control unit 120 is selected this time, it will be selected later when receiving an input signal next time. That is, the sorting update unit 123 makes the current sorting sequence number of the DAC control unit 120 conform to the last-in-first-out selection logic.

[0112] According to the last-in-first-out selection logic, when the sum result of the starting position and the input signal does not overflow, in order to delay the selection of the current DAC control unit 120 in the next time, the current sorting sequence number of the DAC control unit 120 can be updated to the front of the sorting, that is, subtract the target sorting sequence number indicated by the starting position from the current sorting sequence number of the DAC control unit 120. In this way, when the pointer moves sequentially backward, the selection of the current DAC control unit 120 will be delayed.

[0113] For example: Refer to Figure 4 , assuming n = 8, the current sorting sequence numbers Rank 1 ~Rank 8 stored in each DAC control unit 120, namely E1 to E8, are 0, 1, 2, 3, 4, 5, 6, and 7 respectively. If the pointer moves sequentially in the direction of increasing sorting sequence number, and the starting position PT is 2, when the input signal is 3, it means that the pointer needs to move 3 times starting from the starting position PT, that is, the pointer moves from 2 to 5. The DAC control units 120 with the current sorting sequences of 2, 3, and 4 respectively (i.e., E3, E4, E5) are the selected DAC control units 120 that need to output 1. At this time, subtracting PT from the current sorting sequence numbers of E3, E4, and E5 can move them to the front of the sorting.

[0114] In the case where the sum result of the starting position and the input signal overflows, the end position PTN of the pointer is before the starting position PT. At this time, the sorting sequence numbers of some of the currently selected DAC control units 120 may already be at the front of the sorting. Therefore, it is not necessary to move the sorting sequence numbers of these DAC control units 120. That is, the sorting update unit 123 also needs to determine the output signal in combination with the determination result of whether there is an overflow. That is, the sorting update unit 123 is used to: update the current sorting sequence number based on the comparison result and the determination result of whether there is an overflow.

[0115] For example: Refer to Figure 5 , assuming n = 8, the current sorting sequence numbers Rank 1 ~Rank 8They are 3, 4, 0, 1, 2, 5, 6, and 7 respectively. If the pointer moves sequentially in the direction of increasing sorting sequence numbers, and the starting position PT is 5, when the input signal is 4, it means that the pointer needs to move 4 times starting from the starting position PT. At this time, the pointer overflows and needs to move from 5 to 7 and then back to 0, and continue to move sequentially to 1. The currently sorted DAC control units 120 with sorting sequence numbers of 5, 6, 7, and 0 respectively (i.e., E6, E7, E8, and E3) are the selected DAC control units 120 that need to output 1. At this time, only the currently sorted sequence numbers of E6, E7, and E8 need to be subtracted by PT, and E3 remains unchanged, which can ensure that the selected DAC control units 120 are selected later.

[0116] To implement the above update logic, the sorting update unit 123 is used for:

[0117] When the sum result does not overflow, the currently sorted sequence number is greater than or equal to the target sorted sequence number indicated by the starting position, and the currently sorted sequence number is less than the target sorted sequence number indicated by the ending position, subtract the target sorted sequence number indicated by the starting position from the currently sorted sequence number of the DAC control unit 120 to obtain the updated sorted sequence number.

[0118] Refer to Figure 4 , the sum result does not overflow, and for E3, E4, and E5, the currently sorted sequence number is greater than or equal to the target sorted sequence number indicated by the starting position and less than the target sorted sequence number indicated by the ending position, that is, E3, E4, and E5 are the selected DAC control units 120. At this time, subtracting PT from the currently sorted sequence number of this DAC control unit 120 can make this DAC control unit 120 be selected later next time.

[0119] When the sum result does not overflow, the currently sorted sequence number is greater than or equal to the target sorted sequence number indicated by the starting position, and the currently sorted sequence number is greater than or equal to the target sorted sequence number indicated by the ending position, keep the currently sorted sequence number of the DAC control unit 120 unchanged.

[0120] Refer to Figure 4 , the sum result does not overflow, and for E6, E7, and E8, the currently sorted sequence number is greater than or equal to the target sorted sequence number indicated by the starting position and greater than or equal to the target sorted sequence number indicated by the ending position, that is, E6, E7, and E8 are not the selected DAC control units 120. At this time, in the next selection, this DAC control unit 120 needs to be preferentially selected, and the currently sorted sequence number can remain unchanged.

[0121] When the summation result does not overflow, the current sorting sequence number of the DAC control unit 120 is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, the value indicated by the input signal is added to the current sorting sequence number of the DAC control unit 120 to obtain an updated sorting sequence number.

[0122] Reference Figure 4 , the summation result does not overflow, and for E1 and E2, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position and less than the target sorting sequence number indicated by the ending position, that is, E1 and E2 are not the selected DAC control unit 120. At this time, in the next selection, this DAC control unit 120 needs to be preferentially selected. And E1 and E2 are before the starting position, while E6, E7, and E8 are after the starting position, indicating that E1 and E2 enter the sorting earlier than E6, E7, and E8. To ensure the first-in-last-out logic, E1 and E2 need to be selected after E6, E7, and E8, that is, E1 and E2 need to be before E6, E7, and E8. At this time, the value indicated by the input signal can be added to the current sorting sequence numbers of E1 and E2.

[0123] When the summation result overflows, the current sorting sequence number of the DAC control unit 120 is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, the current sorting sequence number of the DAC control unit 120 is added with n minus the target sorting sequence number indicated by the starting position to obtain an updated sorting sequence number.

[0124] Reference Figure 5 , the summation result overflows, and for E4, E5, E1, and E2, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position and greater than or equal to the target sorting sequence number indicated by the ending position, that is, E4, E5, E1, and E2 are not the selected DAC control unit 120. At this time, in the next selection, E4, E5, E1, and E2 need to be preferentially selected, that is, E4, E5, E1, and E2 need to be after E3, E6, E7, and E8. At this time, after adding 8 minus the target sorting sequence number 5 indicated by the starting position PT to the current sorting sequence numbers of E4, E5, E1, and E2, the updated sorting sequence numbers of E4, E5, E1, and E2 are obtained, that is, the current sorting sequence number + 3.

[0125] When the summation result overflows, the current sorting sequence number of the DAC control unit 120 is less than the target sorting sequence number indicated by the starting position, and the current sorting sequence number is less than the target sorting sequence number indicated by the ending position, the current sorting sequence number of the DAC control unit 120 remains unchanged.

[0126] Reference Figure 5, the summation result overflows, and for E3, the current sorting sequence number is less than the target sorting sequence number indicated by the starting position and less than the target sorting sequence number indicated by the ending position, that is, E3 is the selected DAC control unit 120. At this time, in the next selection, E3 needs to be postponed for selection. However, E3 is already at the forefront of the sorting, so the current sorting sequence number of E3 does not need to be changed to ensure that E3 is postponed for selection next time.

[0127] In the case where the summation result overflows, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position, and the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the ending position, the difference obtained by adding the value indicated by the input signal minus n to the current sorting sequence number of the DAC control unit 120 is used to obtain the updated sorting sequence number.

[0128] Reference Figure 5 , the summation result overflows, and for E6, E7, and E8, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the starting position and greater than or equal to the target sorting sequence number indicated by the ending position, that is, E6, E7, and E8 are the selected DAC control unit 120. At this time, in the next selection, E6, E7, and E8 need to be postponed for selection. Therefore, the difference obtained by adding the value 4 indicated by the input signal minus 8 to the current sorting sequence numbers of E6, E7, and E8 is used to obtain the updated sorting sequence numbers, that is, subtract 4 from the current sorting sequence numbers of E6, E7, and E8.

[0129] To implement the above update logic, refer to Figure 2 the schematic diagram of the logical circuit implementation of the dynamic device matching device shown. Those skilled in the art should understand that Figure 2 the logical circuit structure shown is only an example. Those skilled in the art can design a sorting update unit as needed as long as the above update logic can be implemented. As Figure 2 shown, the sorting update unit 123 of each DAC control unit 120 includes: a first adder 1231, a first data selector 1232 and a first register 1233 respectively connected to the input end of the first adder 1231, and a second data selector 1234 and a third data selector 1235 respectively connected to the first data selector 1232; the output end of the first adder 1231 is connected to the input end D of the first register 1233.

[0130] The first register 1233 is used to store the current sorting sequence number of the DAC control unit 120.

[0131] The first data selector 1232 is used to connect to the second data selector 1234 through the first input end in the case where the summation result overflows; and connect to the third data selector 1235 through the second input end in the case where the summation result does not overflow.

[0132] The first data selector 1232 is also connected to the first output terminal of the second adder to receive the determination result C0 of whether there is an overflow. When C0 received by the first data selector 1232 is 0, it is connected to the third data selector 1235 through the second input terminal; when C0 received by the first data selector 1232 is 1, it is connected to the second data selector 1234 through the first input terminal.

[0133] The second data selector 1234 includes: a first data input terminal, a second data input terminal, and a third data input terminal.

[0134] The second data selector 1234 is also connected to the first comparator and the second comparator to receive the comparison result C1 output from the output terminal of the first comparator and the comparison result C2 output from the output terminal of the second comparator.

[0135] When C1 = 1 and C2 = 1, the second data selector 1234 connects the first data input terminal and disconnects the second data input terminal and the third data input terminal; when C1 = 0 and C2 = 1, it connects the second data input terminal and disconnects the first data input terminal and the third data input terminal; when C1 = 0 and C2 = 0, it connects the third data input terminal and disconnects the first data input terminal and the second data input terminal.

[0136] Among them, the first data input terminal is used to: input the value D indicated by the input signal to the second data selector 1234 in subtracted by n ( Figure 2 where n is 8) to obtain the difference value. At this time, the first data input terminal and the first input terminal implement the above update logic corresponding to C0 = 1, C1 = 1, and C2 = 1.

[0137] The second data input terminal is used to: input the difference value obtained by subtracting the target sorting serial number PT indicated by the starting position from n ( Figure 2 where n is 8) to the second data selector 1234. At this time, the first data input terminal and the second data input terminal implement the above update logic corresponding to C0 = 1, C1 = 0, and C2 = 1.

[0138] The third data input terminal is used to: input 0 to the second data selector 1234. At this time, the first data input terminal and the third data input terminal implement the above update logic corresponding to C0 = 1, C1 = 0, and C2 = 0.

[0139] The third data selector 1235 includes: a fourth data input terminal, a fifth data input terminal, and a sixth data input terminal. The third data selector 1235 is also connected to the first comparator and the second comparator to receive the comparison result C1 output from the output terminal of the first comparator and the comparison result C2 output from the output terminal of the second comparator.

[0140] When C1 = 1 and C2 = 1, the third data selector 1235 connects to the fourth data input terminal and disconnects the fifth and sixth data input terminals; when C1 = 1 and C2 = 0, it connects to the fifth data input terminal and disconnects the fourth and sixth data input terminals; when C1 = 0 and C2 = 0, it connects to the sixth data input terminal and disconnects the fourth and fifth data input terminals.

[0141] The fourth data input terminal is used to input 0 to the second data selector 1234. At this time, the second data input terminal and the fourth data input terminal implement the above update logic corresponding to C0 = 0, C1 = 1, and C2 = 1.

[0142] The fifth data input terminal is used to input the negative value of the target sorting sequence number indicated by the starting position, that is, -PT, to the second data selector 1234. At this time, the second data input terminal and the fifth data input terminal implement the above update logic corresponding to C0 = 0, C1 = 1, and C2 = 0.

[0143] The sixth data input terminal is used to input the value D indicated by the input signal to the second data selector 1234 in . At this time, the second data input terminal and the sixth data input terminal implement the above update logic corresponding to C0 = 0, C1 = 0, and C2 = 0.

[0144] At this time, after receiving the current sorting sequence number output from the output terminal Q of the first register 1233 and the data selected by each data selector, the first adder 1231 sums them to obtain the updated sorting sequence number, and outputs the updated sorting sequence number to the input terminal D of the first register 1233 through the output terminal. The first register 1233 is used to latch the data received at the input terminal D to the pin Q as the current sorting sequence number for update when receiving the input signal next time.

[0145] Optionally, the bit widths of the first register 1233 and the first adder 1231 are determined based on the value of n. Exemplarily, the bit widths of the first register 1233 and the first adder 1231 are m, 2 m = n.

[0146] Optionally, the first register 1233 further includes a signal synchronization pin CLK to ensure the operation synchronization between the various units in the dynamic device matching device.

[0147] In a possible implementation, each DAC control unit 120 further includes a reset unit configured to: when receiving a reset signal RST, update the current sorting sequence number stored in the sorting storage unit 122 to a preset value, where the preset values corresponding to different DAC control units 120 are different. For example, the preset value is the number of the DAC control unit 120 minus 1, that is, the preset value is i.

[0148] Exemplarily, referring to Figure 2 , the reset unit is a data selector 124. One input terminal of the data selector 124 is connected to the output terminal of the first adder, and the other input terminal is connected to the preset value; the output terminal is connected to the input terminal D of the first register. The data selector is also connected to the input terminal of the reset signal. If the reset signal RST is received, the other input terminal of the data selector 124 is turned on. At this time, the reset unit inputs the preset value to the first register, realizing the reset of the current sorting sequence number of the DAC control unit 120. If the reset signal RST is not received, one input terminal of the data selector is turned on. At this time, the reset unit inputs the output result of the first adder to the first register, realizing the update of the current sorting sequence number of the DAC control unit 120.

[0149] It should be noted that although the logic circuit shown in Figure 2 is used as an example to introduce the dynamic device matching device applicable to high-precision digital-to-analog converters as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly design the logic circuit according to the dynamic device matching principle of the dynamic device matching device.

[0150] In summary, the dynamic device matching device applicable to a high-precision digital-to-analog converter provided in this embodiment sets a pointer update unit for: receiving an input signal; determining an end position of the pointer according to the input signal and a starting position of the pre-stored pointer; and n DAC control units respectively connected to the pointer update unit; each DAC control unit includes a comparison unit, a sorting and storage unit, and a sorting and update unit; the sorting and storage unit is used for: storing a current sorting serial number of the DAC control unit, and the current sorting serial number is used to indicate a sorting order of the DAC control unit among the n DAC control units; the comparison unit is used for: comparing the current sorting serial number with a target sorting serial number indicated by the starting position and a target sorting serial number indicated by the end position respectively to obtain a comparison result; determining an output signal of the DAC control unit based on the comparison result; the sorting and update unit is used for updating the current sorting serial number based on the comparison result so that when the DAC control unit is selected this time, it will be selected later when receiving the input signal next time; on the one hand, compared with the traditional digital weighted average circuit, this dynamic device matching device adopts the design idea of last-in-first-out, making the selection result of the DAC control unit similar to that of the high-order DEM. Therefore, the shaping ability is similar to that of the high-order DEM, with strong shaping ability and extremely strong harmonic suppression ability, which can solve the problem of poor shaping ability of the traditional data weighted average circuit; on the other hand, compared with the high-order DEM, the sorting and update unit of this dynamic device matching device can directly operate the current sorting serial number of each DAC control unit without the complex digital filtering circuit and comparison and sorting circuit in the traditional high-order DEM. Therefore, the hardware implementation complexity is low, which can solve the problem that the logic circuit implementation of the high-order DEM is complex and cannot be widely applied.

[0151] In addition, the dynamic device matching device provided in this application can be used in high-precision oversampling ADC and DAC control unit products. This solution has extremely low power consumption and area overhead, and the digital logic of this solution has good process compatibility. Its power consumption and area advantages will be further improved under advanced processes. Therefore, it can be conveniently integrated into the ADC and DAC control unit modules to assist the ADC and DAC control units to achieve the index requirements of low power consumption and high linearity under advanced processes, further improving the versatility of the dynamic device matching device.

[0152] To more clearly understand the selection principle of the DAC control unit of the dynamic device matching device applicable to a high-precision digital-to-analog converter provided in this application, an example of the process of the device selecting the DAC control unit is given below for illustration. Refer to Figure 6 , assuming that the total number of DAC control units is 8, that is, n = 8, and each DAC control unit is initialized: the current sorting orders of E1 to E8 are 0, 1, 2, 3, 4, 5, 6, 7 respectively, and the starting position PT of the pointer is 0.

[0153] The first selection: The value of the input signal is 3. At this time, PT = 0, PT + 3 = 3, the summation result does not overflow, PTN = 3. The selected DAC control units in the sorting queue are E1 to E3. According to the above selection logic, E1 to E3 output 1, and the current sorting sequence numbers of each DAC control unit remain unchanged.

[0154] The second selection: The value of the input signal is 3. At this time, PT = PTN = 3, PT + 3 = 6, the summation result does not overflow, PTN = 6. The selected DAC control units in the sorting queue are E4 to E6. According to the above selection logic, E4 to E6 output 1, and the current sorting sequence numbers of E4 to E6 are updated to the front of the sorting, from 3 to 5 are updated to 0 to 2 respectively. Correspondingly, E1 to E3 move backward by 3 bits, and the current sorting sequence numbers of E1 to E3 are updated from 0 to 2 to 3 to 5 respectively.

[0155] The third selection: The value of the input signal is 4. At this time, PT = PTN = 6, PT + 4 = 10, the summation result overflows, PTN = 10 - 8 = 2. The selected DAC control units in the sorting queue are E7 to E8 and E4 to E5. According to the above selection logic, E7 to E8 and E4 to E5 output 1. The current sorting sequence numbers of E4 to E5 remain unchanged, and the current sorting sequence numbers of E7 to E8 are after E4 to E5, that is, from 6 to 7 are updated to 2 to 3 respectively. Correspondingly, E6, E1 to E3 move backward by 2 bits, and the current sorting sequence numbers from 2 to 5 are updated to 4 to 7 respectively.

[0156] The fourth selection: The value of the input signal is 4. At this time, PT = PTN = 2, PT + 4 = 6, the summation result does not overflow, PTN = 6. The selected DAC control units in the sorting queue are E7, E8, E6, E1. According to the above selection logic, E7, E8, E6, E1 output 1, and the current sorting sequence numbers move to the front of the sorting, that is, from 2 to 5 are updated to 0 to 3 respectively. Correspondingly, E4 and E5 move backward by 4 bits, and the current sorting sequence numbers from 0 to 1 are updated to 4 to 5 respectively. The current sorting sequence numbers of E2 and E3 remain unchanged.

[0157] The fifth selection: The value of the input signal is 3. At this time, PT = PTN = 6, PT + 3 = 9, the summation result overflows, PTN = 9 - 8 = 1. The selected DAC control units in the sorting queue are E2, E3, and E7. According to the above selection logic, E2, E3, and E7 output 1. The current sorting sequence number of E7 remains unchanged, and the current sorting sequence numbers of E2 and E3 are after E7, that is, from 6 to 7 are updated to 1 to 2 respectively. Correspondingly, E8, E6, E1, E4, and E5 move backward by 2 bits, and the current sorting sequence numbers from 1 to 5 are updated to 3 to 7 respectively.

[0158] 6th selection: The value of the input signal is 4. At this time, PT = PTN = 1, PT + 4 = 5, the summation result does not overflow, PTN = 5. The selected DAC control units in the sorting queue are E2, E3, E8, E6. According to the above selection logic, E2, E3, E8, E6 output 1, and the current sorting sequence number moves to the front of the sorting, that is, it is updated from 1 to 4 to 0 to 3 in sequence. Correspondingly, E7 moves backward by 4 bits, and the current sorting sequence number is updated from 0 to 4. The current sorting sequence numbers of E1, E4, and E5 remain unchanged.

[0159] 7th selection: The value of the input signal is 3. At this time, PT = PTN = 5, PT + 3 = 8, the summation result overflows, PTN = 8 - 8 = 0. The selected DAC control units in the sorting queue are E1, E4, E5. According to the above selection logic, E1, E4, E5 output 1, and E1, E4, E5 move to the front of the sorting, that is, it is updated from 5 to 7 to 0 to 2 in sequence. Correspondingly, E2, E3, E8, E6, E7 move backward by 3 bits, that is, the current sorting sequence number is updated from 0 to 4 to 3 to 7.

[0160] 8th selection: The value of the input signal is 4. At this time, PT = PTN = 0, PT + 4 = 4, the summation result does not overflow, PTN = 4. The selected DAC control units in the sorting queue are E1, E4, E5 and E2. According to the above selection logic, E1, E4, E5 and E2 output 1. The current sorting sequence numbers of E1, E4, E5 and E2 are already at the front of the sorting. Therefore, the current sorting sequence numbers of E1, E4, E5 and E2 remain unchanged. Correspondingly, the current sorting sequence numbers of E3, E8, E6, E7 also remain unchanged.

[0161] 9th selection: The value of the input signal is 3. At this time, PT = PTN = 4, PT + 3 = 7, the summation result does not overflow, PTN = 7. The selected DAC control units in the sorting queue are E3, E8, E6. According to the above selection logic, E3, E8, E6 output 1, and the current sorting sequence numbers of E3, E8, E6 move to the front of the sorting. Therefore, the current sorting sequence numbers of E3, E8, E6 are updated from 4 to 6 to 0 to 2 in sequence. Correspondingly, E1, E4, E5 and E2 move backward by 3 bits, that is, the current sorting sequence numbers of E1, E4, E5 and E2 are updated from 0 to 3 to 3 to 6 in sequence, and E7 remains unchanged.

[0162] 10th selection: The value of the input signal is 4. At this time, PT = PTN = 7, PT + 4 = 11, and the summation result overflows. PTN = 11 - 8 = 3. The selected DAC control units in the sorting queue are E7, E3, E8, and E6. According to the above selection logic, E7, E3, E8, and E6 output 1, and E7 moves behind E3, E8, and E6. That is, the current sorting sequence number is updated from 7 to 3. Correspondingly, E1, E4, E5, and E2 move backward by 1 bit, that is, the current sorting sequence numbers from 3 to 6 are updated to 4 to 7.

[0163] Repeat the above selection process until a reset signal is received and updated to the preset value, or a stop update signal is received, and then stop the above selection process.

[0164] By comparing the selection results of the dynamic device matching device applicable to high-precision digital-to-analog converters provided in this application with the selection results of traditional digital weighted average circuits and the selection results of 2nd-order DEM respectively, the obtained results are as shown in Figure 7 . According to Figure 7 it can be known that the selection results of the dynamic device matching device provided in this application are compared with Figure 7 the leftmost digital weighted average selection result in Figure 7 and the dynamic device matching result of the rightmost 2nd-order DEM. The selection results of this application are similar to the 2nd-order dynamic device matching results, both having the selection characteristic of advanced in and last out, that is, the shaping effect of 2nd-order DEM can be achieved.

[0165] The comparison output spectrum of the shaping mismatch error of the selection results of the dynamic device matching device applicable to high-precision digital-to-analog converters provided in this application, the selection results of the digital weighted average circuit, and the selection results of the second-order DEM in the same delta sigma ADC (a kind of high-precision ADC device) is as shown in Figure 8 . According to Figure 8 it can be known that this application has a similar shaping ability to the second-order DEM. Compared with the digital weighted average circuit, this application has a better ability to suppress harmonic distortion.

[0166] Figure 9 The flowchart of the dynamic device matching method applicable to high-precision digital-to-analog converters according to an embodiment of the present disclosure is shown. This application is described by taking this method as an example for the dynamic device matching device applicable to high-precision digital-to-analog converters provided in the above embodiment. The method includes the following steps:

[0167] Step 901, receive an input signal;

[0168] Step 902: Determine the end position of the pointer according to the input signal and the start position of the pre-stored pointer; the start position and the end position are used to indicate the target sorting serial number of the DAC control unit selected this time.

[0169] Step 903: For each DAC control unit, compare the current sorting serial number corresponding to the DAC control unit with the target sorting serial numbers indicated by the start position and the end position respectively to obtain a comparison result; wherein, the current sorting serial number is used to indicate the sorting order of the DAC control unit among the n DAC control units.

[0170] Step 904: Determine the output signal of the DAC control unit based on the comparison result and update the current sorting serial number so that, in the case where the DAC control unit is selected this time, it will be selected later when the input signal is received next time.

[0171] For relevant details, refer to the above embodiments.

[0172] In some embodiments, the functions or unit modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above embodiments, and their specific implementations can be referred to each other. For the sake of brevity, they will not be elaborated here.

[0173] The above has described the embodiments of the present disclosure. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A dynamic device matching device suitable for a high-precision digital-to-analog converter, characterized in that: The device comprises: The pointer updating unit is used to: receive an input signal; determine the end position of the pointer according to the input signal and the start position of the pointer stored in advance; the start position and the end position are used to indicate the target sorting sequence number of the DAC control unit selected this time; n DAC control units are respectively connected to the pointer update unit; each DAC control unit includes a comparison unit, a sort storage unit, and a sort update unit; n is an integer greater than 1; The sorting storage unit is used to store the current sorting sequence number of the DAC control unit, where the current sorting sequence number is used to indicate the sorting order of the DAC control unit among n DAC control units; The comparison unit is used to: compare the current sorting sequence number with the target sorting sequence number indicated by the start position and the target sorting sequence number indicated by the end position, respectively, to obtain a comparison result; and determine the output signal of the DAC control unit based on the comparison result; The sorting update unit is used to update the current sorting sequence number based on the comparison result, so that when the DAC control unit is selected this time, it will be delayed in selection the next time it receives an input signal.

2. The device according to claim 1, characterized in that The pointer updating unit is further used to: determine whether the sum of the input signal and the starting position overflows; if overflow occurs, subtract n from the sum to obtain the end position; Accordingly, The comparison unit is used to determine the output signal of the DAC control unit based on the comparison result and the determination result of whether there is an overflow; The sorting update unit is used to update the current sorting sequence number based on the comparison result and the determination result of whether there is an overflow.

3. The device according to claim 2, characterized in that The sorting update unit is used to: In the case where the sum result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, subtracting the target sorting number indicated by the starting position from the current sorting number of the DAC control unit to obtain an updated sorting number; In the case where the sum result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is kept unchanged; In the case where the sum result does not overflow, the current sorting number is less than the target sorting number indicated by the start position, and the current sorting number is less than the target sorting number indicated by the end position, adding the current sorting number of the DAC control unit to the value indicated by the input signal to obtain an updated sorting number; In the case where the sum result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added with n minus the target sorting number indicated by the starting position to obtain an updated sorting number; In the case where the sum result overflows, the current sorting number is less than the target sorting number indicated by the start position, and the current sorting number is less than the target sorting number indicated by the end position, the current sorting number of the DAC control unit is kept unchanged; When the sum result overflows, the current sort number is greater than or equal to the target sort number indicated by the starting position, and the current sort number is greater than or equal to the target sort number indicated by the ending position, the current sort number of the DAC control unit is added to the value indicated by the input signal minus the difference obtained by subtracting n to obtain an updated sort number.

4. The device according to claim 3, characterized in that The sorting update unit comprises: a first adder, a first data selector and a first register respectively connected to an input end of the first adder, and a second data selector and a third data selector respectively connected to the first data selector; an output end of the first adder is connected to an input end of the first register; The first register is used to store the current sorting sequence number; The first data selector is used to connect with the second data selector through the first input terminal when the sum result overflows; and to connect with the third data selector through the second input terminal when the sum result does not overflow; The second data selector comprises a first data input terminal, a second data input terminal and a third data input terminal; the first data input terminal is used to input a difference value obtained by subtracting the value indicated by the input signal from the value n to the second data selector; the second data input terminal is used to input a difference value obtained by subtracting the target sorting sequence number indicated by the starting position from the value n to the second data selector; the third data input terminal is used to input 0 to the second data selector; The third data selector includes a fourth data input terminal, a fifth data input terminal and a sixth data input terminal; the fourth data input terminal is used to input 0 to the second data selector; the fifth data input terminal is used to input the negative value of the target sorting number indicated by the starting position to the second data selector; the sixth data input terminal is used to input the value indicated by the input signal to the second data selector.

5. The device according to claim 2, characterized in that The comparison unit is used for: In the case where the sum result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the start position, and the current sorting number is greater than or equal to the target sorting number indicated by the end position, determining that the output signal is 1; or, In the case where the sum result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, determining that the output signal is 1; or, When the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 1.

6. The device according to claim 5, characterized in that When the sum result overflows, the first output terminal of the pointer updating unit outputs 1, and when the sum result does not overflow, the first output terminal of the pointer updating unit outputs 0; accordingly, The comparison unit includes a first comparator, a second comparator, and an XOR device; The first comparator is used to output 1 if the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and output 0 if the current sorting number is less than the target sorting number indicated by the starting position; The second comparator is used to output 1 when the current sorting number is greater than or equal to the target sorting number indicated by the end position, and output 0 when the current sorting number is less than the target sorting number indicated by the end position; The XOR device is connected to the first comparator, the second comparator and the first output terminal respectively; the XOR device is used to output 0 or 1 based on the first comparison result, the second comparison result and the determination result output by the first output terminal.

7. The device according to claim 2, characterized in that The pointer updating unit comprises a second adder and a second register; The second register is used to store the starting position of the pointer; The second adder comprises a signal input terminal and a pointer input terminal, the signal input terminal is used to input the input signal to the second adder; the pointer input terminal is connected to the output terminal of the second register to input the starting position stored in the second register to the second adder; The second adder further includes a first output terminal and a second output terminal, wherein the first output terminal is used to output a result of determining whether there is an overflow; and the second output terminal is used to output the end position.

8. The device according to claim 7, characterized in that The second output end is connected to the input end of the second register to store the end position, so that when the input signal is received next time, the end position is used as the starting position of the pointer corresponding to the next input signal to determine the end position of the pointer corresponding to the next input signal.

9. The device according to any one of claims 1 to 8, characterized in that: Each DAC control unit further includes a reset unit, which is used to update the current sorting sequence number stored in the sorting storage unit to a preset value when a reset signal is received. Different DAC control units correspond to different preset values.

10. A dynamic device matching method suitable for a high-precision digital-to-analog converter, characterized in that: The method comprises: receiving an input signal; Determine the end position of the pointer according to the input signal and the start position of the pointer stored in advance; the start position and the end position are used to indicate the target sorting sequence number of the DAC control unit selected this time; For each DAC control unit, the current sorting sequence number corresponding to the DAC control unit is compared with the target sorting sequence number indicated by the starting position and the target sorting sequence number indicated by the ending position to obtain a comparison result; wherein the current sorting sequence number is used to indicate the sorting order of the DAC control unit among the n DAC control units; The output signal of the DAC control unit is determined based on the comparison result, and the current sorting sequence number is updated so that if the DAC control unit is selected this time, it will be delayed in selection the next time an input signal is received.

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