Method for forming sidewalls of SONOS memory

Abstract

The application provides a sidewall forming method of a SONOS memory. A substrate is provided, which has a logic area and a storage area. A first oxide layer is formed on the logic area of the substrate. An ONO layer is formed on the storage area. The ONO layer is composed of a second oxide layer, a nitride layer and a third oxide layer stacked from bottom to top. A polysilicon layer is deposited. Then, the polysilicon layer is patterned by using photolithography and etching to form a gate polysilicon layer on the logic area and the storage area. The exposed third oxide layer is removed to expose the nitride layer below. A fourth oxide layer is formed on the surface of the gate polysilicon layer. A first sidewall is formed on the fourth oxide layer of the sidewall of the gate polysilicon layer. The material of the first sidewall is nitride. The first sidewall and the exposed nitride layer are oxidized into a fifth oxide layer. Subsequent sidewall structures are formed by using deposition and back etching. The ONO layer of the SONOS area and the first oxide layer of the logic area are etched completely without damaging the substrate, and an effective protection sidewall is formed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming sidewalls of a SONOS memory. Background Technology

[0002] In the development of embedded SONOS memory, sidewall formation faces challenges as it requires simultaneously accommodating both the logic region's MOS transistors and the memory region's SONOS transistors. After gate etching and before sidewall formation, the residual dielectric layer for the SONOS transistors is an ONO layer, while the residual dielectric layer for the MOS transistors is SiO2. Current sidewall processes struggle to simultaneously accommodate both the SONOS and MOS transistor regions during etching.

[0003] 1. If it is ensured that there is no over-etching in the logic area, the SONOS area will encounter the problem of SIN residue in the ONO layer, which will prevent the formation of metal silicide in the source and drain areas, resulting in poor contact and problems such as the inability to etch through the contact holes.

[0004] 2. If the ONO layer in the SONOS region is thoroughly etched, the logic region will suffer from excessive silicon substrate loss, resulting in a deterioration of the source-drain junction of the logic device and a decrease in leakage current.

[0005] To address the aforementioned issues, a novel method for forming the sidewalls of the SONOS memory needs to be proposed. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a sidewall formation method for SONOS memory, which solves the problem that the sidewall process in the prior art is difficult to simultaneously cover the SONOS transistor region and the MOS transistor region during etching.

[0007] To achieve the above and other related objectives, the present invention provides a method for forming sidewalls of a SONOS memory, comprising:

[0008] Step 1: Provide a substrate having a logic region and a memory region. A first oxide layer is formed on the logic region on the substrate, and an ONO layer is formed on the memory region. The ONO layer consists of a second oxide layer, a nitride layer, and a third oxide layer stacked sequentially from bottom to top. A polysilicon layer is deposited, and then the polysilicon layer is patterned using photolithography and etching to form the gate polysilicon layers on the logic region and the memory region.

[0009] Step 2: Remove the exposed third oxide layer to expose the nitride layer underneath, form a fourth oxide layer on the surface of the gate polysilicon layer, and form a first sidewall on the fourth oxide layer located on the sidewall of the gate polysilicon layer. The material of the first sidewall is nitride.

[0010] Step 3: Oxidize the first sidewall and the exposed nitride layer to form a fifth oxide layer, wherein the nitride layer is completely oxidized;

[0011] Step 4: Use deposition and etching back methods to form the subsequent sidewall structure.

[0012] Preferably, the method for patterning the polysilicon layer in step one includes: forming a photoresist layer on the polysilicon layer; photolithographically opening the photoresist layer to define the formation location of the gate polysilicon layer; patterning the polysilicon layer by etching to form the gate polysilicon layer; and removing the remaining photoresist layer.

[0013] Preferably, the etching method in step one is dry etching.

[0014] Preferably, in step two, the exposed third oxide layer is removed using a wet etching method.

[0015] Preferably, the fourth oxide layer is formed in step two using a thermal oxidation method.

[0016] Preferably, the thickness of the fourth oxide layer in step two is 20 to 50 angstroms.

[0017] Preferably, the method for forming the first sidewall in step two includes: depositing a first sidewall material layer and etching back the first sidewall material layer to form the first sidewall.

[0018] Preferably, the thickness of the first sidewall in step two is 60 to 100 angstroms.

[0019] Preferably, in step three, the first sidewall and the exposed nitrided layer are oxidized into a fifth oxide layer using an in-situ water vapor oxidation method.

[0020] Preferably, the method for forming the subsequent sidewall structure in step four includes: sequentially depositing a second and a third sidewall material layer, wherein the second sidewall material layer is a nitride and the third sidewall material layer is an oxide layer; etching the second and third material layers, stopping the etching on the fifth oxide layer, so that it remains at the sidewall of the gate polysilicon layer to form a sidewall structure, exposing the fifth oxide layer on the upper surface of the gate polysilicon layer, and exposing the fifth oxide layer extending from the bottom end of the second sidewall; and continuing to etch away the fifth oxide layer, the fourth oxide layer on the upper surface of the gate polysilicon layer, and the first, second, and fifth oxide layers exposed on the substrate.

[0021] Preferably, in step four, the second and third sidewall material layers are etched using a dry etching method.

[0022] Preferably, in step four, wet etching is used to remove the fifth oxide layer, the fourth oxide layer, and the exposed first, second, and fifth oxide layers on the upper surface of the gate polysilicon layer.

[0023] Preferably, the thickness of the second sidewall material layer in step four is 150 to 300 angstroms.

[0024] Preferably, the thickness of the third sidewall material layer in step four is 200 to 700 angstroms.

[0025] Preferably, the method is used for processes at technology nodes of 55nm and below.

[0026] As described above, the sidewall formation method of the SONOS memory of the present invention has the following beneficial effects:

[0027] This invention can simultaneously etch the ONO layer of the SONOS region and the first oxide layer of the logic region without damaging the substrate, thus forming an effective protective sidewall for the SONOS and MOS transistors. Attached Figure Description

[0028] Figure 1 The diagram shows a pre-existing deposited ONO sidewall.

[0029] Figure 2 The diagram shows the structure after etching the ONO sidewalls in the prior art.

[0030] Figure 3 The diagram shown is a schematic representation of the process flow of the present invention.

[0031] Figure 4 The diagram shown illustrates the formation of the gate polysilicon layer according to the present invention.

[0032] Figure 5 The diagram shown illustrates the removal of the exposed third oxide layer according to the present invention.

[0033] Figure 6 The diagram shown illustrates the formation of the fourth oxide layer according to the present invention.

[0034] Figure 7 The diagram shows a schematic of the deposited first sidewall material layer of the present invention.

[0035] Figure 8 The diagram shown is a schematic diagram of the etching of the first sidewall material layer according to the present invention.

[0036] Figure 9 The diagram shows the oxidation of the first sidewall and the exposed nitride layer into a fifth oxide layer according to the present invention.

[0037] Figure 10 The diagram shows the deposited second and third sidewall material layers of the present invention.

[0038] Figure 11 This is a schematic diagram of the first etching process for forming the sidewall structure according to the present invention.

[0039] Figure 12 This is a schematic diagram of the second etching process for forming the sidewall structure according to the present invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figure 3 The present invention provides a method for forming sidewalls of a SONOS memory, comprising:

[0042] Step 1: Provide a substrate 1, which has logic regions and memory regions. A first oxide layer 2 is formed on the logic regions of the substrate 1, and an ONO layer 3 is formed on the memory regions. The ONO layer 3 consists of a second oxide layer, a nitride layer, and a third oxide layer stacked sequentially from bottom to top. A polysilicon layer is deposited, and then the polysilicon layer is patterned using photolithography and etching to form the gate polysilicon layers 4 on the logic regions and memory regions, forming... Figure 4 The structure shown; in various embodiments of the present invention, the material of the oxide layer may be silicon dioxide, and the material of the nitride layer may be silicon nitride;

[0043] In some embodiments, the method of patterning the polysilicon layer in step one includes: forming a photoresist layer on the polysilicon layer; photolithographically opening the photoresist layer to define the formation location of the gate polysilicon layer 4; using etching to pattern the polysilicon layer to form the gate polysilicon layer 4; and removing the remaining photoresist layer, which can be done using methods such as ashing or wet cleaning.

[0044] In some embodiments, the etching method in step one is dry etching.

[0045] Step 2: Remove the exposed third oxide layer to expose the underlying nitride layer, forming a layer like... Figure 5 The structure shown has a fourth oxide layer 5 formed on the surface of the gate polysilicon layer 4, forming a structure as shown. Figure 6 The structure shown forms a first sidewall 6 on the fourth oxide layer 5 on the sidewall of the gate polysilicon layer 4. The material of the first sidewall 6 is nitride, forming a structure as shown in the diagram. Figure 8 The structure shown;

[0046] In some embodiments, the exposed third oxide layer is removed in step two using a wet etching method.

[0047] In some embodiments, a fourth oxide layer 5 is formed in step two using a thermal oxidation method, which is used to repair the etching loss of the gate polysilicon layer 4.

[0048] In some embodiments, the thickness of the fourth oxide layer 5 in step two is 20 to 50 angstroms.

[0049] In some embodiments, the method for forming the first sidewall 6 in step two includes: depositing a material layer of the first sidewall 6 to form a layer as shown in the figure. Figure 7 The structure shown is formed by etching back the material layer of the first sidewall 6 to form the first sidewall 6.

[0050] In some embodiments, the thickness of the first sidewall 6 in step two is 60 to 100 angstroms, and it can subsequently be oxidized to form an oxide layer with a thickness of about 100 angstroms.

[0051] Step 3: Oxidize the first sidewall 6 and the exposed nitride layer to form the fifth oxide layer 7. The nitride layer needs to be completely oxidized, while the first sidewall 6 does not necessarily need to be completely oxidized, forming a structure like... Figure 9 In the structure shown, the residual ONO layer 3 in the SONOS region is converted into the same oxide as the logic region, and the oxide generated by oxidation can also serve as the first layer of silicon oxide in the sidewall structure.

[0052] In some embodiments, in step three, the first sidewall 6 and the exposed nitride layer are oxidized to the fifth oxide layer 7 using in-situ water vapor oxidation. In-situ water vapor oxidation can also oxidize Si and polycrystalline silicon to oxides.

[0053] Step 4: Use deposition and etching back methods to form the subsequent sidewall structure.

[0054] In some embodiments, the method for forming the subsequent sidewall structure in step four includes: sequentially depositing second and third sidewall material layers, wherein the second sidewall 8 material layer is a nitride and the third sidewall 9 material layer is an oxide layer, forming a structure as shown in the figure. Figure 10 The structure shown is as follows: The second and third sidewall material layers are etched, with the etching stopping at the fifth oxide layer 7, leaving it at the sidewall of the gate polysilicon layer 4 to form a sidewall structure. The fifth oxide layer 7 on the upper surface of the gate polysilicon layer 4 is exposed, and the fifth oxide layer 7 extending from the bottom end of the second sidewall 8 is also exposed, forming a structure as shown. Figure 11 The structure shown is further etched to remove the fifth oxide layer 7, the fourth oxide layer 5, and the exposed first, second, and fifth oxide layers on the substrate 1 from the upper surface of the gate polysilicon layer 4. The remaining fifth oxide layer 7 serves as the first sidewall in the sidewall structure, forming a structure as shown. Figure 12 The structure shown.

[0055] In some embodiments, the second and third sidewall material layers are etched using a dry etching method in step four.

[0056] In some embodiments, in step four, the fifth oxide layer 7, the fourth oxide layer 5, and the exposed first, second, and fifth oxide layers on the upper surface of the gate polysilicon layer 4 are removed by wet etching.

[0057] In some embodiments, the thickness of the material layer of the second sidewall 8 in step four is 150 to 300 angstroms.

[0058] In some embodiments, the thickness of the third sidewall 9 material layer in step four is 200 to 700 angstroms.

[0059] In some embodiments, the above method is used for processes at technology nodes of 55nm and below.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] In summary, this invention can simultaneously and completely etch the ONO layer of the SONOS region and the first oxide layer of the logic region without damaging the substrate, forming effective protective sidewalls for the SONOS and MOS transistors. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a sidewall of a SONOS memory, comprising: At least comprising: Step one, providing a substrate, the substrate has a logic area and a memory area, the logic area on the substrate is formed with a first oxide layer, the memory area is formed with an ONO layer, the ONO layer is composed of a second oxide layer, a nitride layer and a third oxide layer stacked from bottom to top, depositing a polysilicon layer, then using photolithography and etching method to pattern the polysilicon layer to form a gate polysilicon layer on the logic area and the memory area; Step two, removing the exposed third oxide layer to expose the nitride layer below, forming a fourth oxide layer on the surface of the gate polysilicon layer, forming a first sidewall on the fourth oxide layer on the sidewall of the gate polysilicon layer, the material of the first sidewall is nitride; Step three, oxidizing the first sidewall and the exposed nitride layer to form a fifth oxide layer, the nitride layer is completely oxidized, the fifth oxide layer wraps the top and sidewall of the gate polysilicon layer and extends to the surrounding substrate surface; Step four, using deposition and etching back method to form subsequent sidewall structure; the method for forming the subsequent sidewall structure comprises: sequentially depositing second and third sidewall material layers, the second sidewall material layer is nitride, and the third sidewall material layer is an oxide layer; etching the second and third sidewall material layers, and stopping etching on the fifth oxide layer, so that the second and third sidewall material layers remain to form a sidewall structure at the sidewall of the gate polysilicon layer, the fifth oxide layer on the upper surface of the gate polysilicon layer is exposed, and the fifth oxide layer extending out of the bottom end of the remaining second sidewall material layer is exposed; and continuing to etch to remove the fifth oxide layer on the upper surface of the gate polysilicon layer, the fourth oxide layer and the first, second and fifth oxide layers exposed on the substrate.

2. The method of claim 1, wherein: The method for patterning the polysilicon layer in step one comprises the following steps: forming a photoresist layer on the polysilicon layer; opening the photoresist layer by photolithography to define the forming position of the gate polysilicon layer; patterning the polysilicon layer by etching to form the gate polysilicon layer; and removing the remaining photoresist layer.

3. The method of claim 1, wherein: The etching method in step one is dry etching.

4. The method of claim 1, wherein: The exposed third oxide layer is removed by wet etching in step two.

5. The method of claim 1, wherein: The fourth oxide layer is formed by thermal oxidation in step two.

6. The method of claim 1, wherein: The thickness of the fourth oxide layer in step two is 20-50 angstroms.

7. The method of claim 1, wherein: The method for forming the first sidewall in step two comprises the following steps: depositing a first sidewall material layer, and etching back the first sidewall material layer to form a first sidewall.

8. The method of claim 1, wherein: The thickness of the first sidewall in step two is 60-100 angstroms.

9. The method of claim 1, wherein: The first sidewall and the exposed nitride layer are oxidized into a fifth oxide layer by in-situ water vapor oxidation in step three.

10. The method of claim 1, wherein: The second and third sidewall material layers are etched by dry etching in step four.

11. The method of claim 1, wherein: The fifth oxide layer on the upper surface of the gate polysilicon layer, the fourth oxide layer and the exposed first, second and fifth oxide layers are etched and removed by wet etching in step four.

12. The method of claim 1, wherein: The thickness of the second sidewall material layer in step four is 150-300 angstroms.

13. The method of claim 1, wherein: The thickness of the third sidewall material layer in step four is 200-700 angstroms.

14. The method of claim 1, wherein: The method is used for 55 nm and below technology node processes. The method is used for 55 nm and below technology node processes.

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