Sense amplifier circuit and semiconductor memory device including same

Abstract

The invention provides a sense amplifier circuit and a semiconductor memory device including the same. The sense amplifier circuit includes bit line sense amplifiers each including an amplification circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. An amplification circuit is connected to the bit line and the complementary bit line to adjust voltages of the read bit line and the complementary read bit line. An isolation circuit connects the bit line and the complementary bit line to the complementary readout bit line and the readout bit line. The offset cancellation circuit connects the bit line and the complementary bit line to the readout bit line and the complementary readout bit line. The equalizer circuit equalizes the bit line and the complementary bit line to a pre-charge voltage, and includes an equalization transistor. The active region is formed such that sources of equalization transistors of the first bit line sense amplifier and the second bit line sense amplifier are connected, and sources of equalization transistors of the first bit line sense amplifier and the third bit line sense amplifier are separated.

Description

Technical Field

[0001] Example embodiments generally relate to semiconductor integrated circuits, and more particularly, to sense amplifier circuits of semiconductor memory devices and semiconductor memory devices including the sense amplifier circuits. Background Art

[0002] Semiconductor memory devices can be classified into two categories depending on whether they retain stored data when disconnected from a power supply. These semiconductor memory devices fall into two categories: non-volatile memory devices, which retain their stored data even after being disconnected from the power supply; and volatile memory devices, which lose the data they record. Volatile memory devices can read and write data quickly, but the data they contain may disappear when they are turned off. Non-volatile memory devices can be used to store data that needs to be retained because the content remains even after the device is powered off.

[0003] A semiconductor memory device may include a plurality of memory cells. It may be necessary to precharge a bit line and a complementary bit line to a precharge voltage, perform a charge sharing operation, and observe changes in the voltage levels of the bit line and the complementary bit line in order to identify the data contained in the memory cell. A sense amplifier can then receive and amplify the voltage difference between the bit line and the complementary bit line to detect the data stored in the memory cell. Summary of the Invention

[0004] At least one example embodiment of the present disclosure provides a sense amplifier circuit capable of efficiently preventing defects and reducing size.

[0005] At least one example embodiment of the present disclosure provides a semiconductor memory device including the sense amplifier circuit.

[0006] According to an exemplary embodiment, a sense amplifier circuit includes a plurality of bit line sense amplifiers. Each of the plurality of bit line sense amplifiers includes an amplifying circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. The amplifying circuit is electrically connected to a bit line and a complementary bit line, reads a voltage difference between the bit line and the complementary bit line, and adjusts voltages of a read bit line and a complementary read bit line based on the voltage difference. The isolation circuit electrically connects the bit line and the complementary bit line to the complementary read bit line and the read bit line, respectively. The offset cancellation circuit electrically connects the bit line and the complementary bit line to the read bit line and the complementary read bit line, respectively. The equalizer circuit equalizes the bit line and the complementary bit line to a precharge voltage. The equalizer circuit includes an equalization transistor having a source, a drain, and a gate configured to receive an equalization signal. An active region is formed such that sources of the equalization transistors of a first bit line sense amplifier and a second bit line sense amplifier are connected to each other, and sources of the equalization transistors of the first bit line sense amplifier and a third bit line sense amplifier are separated from each other.

[0007] According to an exemplary embodiment, a semiconductor memory device includes a memory cell array and a sense amplifier circuit. The memory cell array includes a plurality of memory cells. The sense amplifier circuit includes a plurality of bit line sense amplifiers connected to the plurality of memory cells. Each of the plurality of bit line sense amplifiers includes an amplifying circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. The amplifying circuit is electrically connected to a bit line and a complementary bit line, reads a voltage difference between the bit line and the complementary bit line, and adjusts voltages of a read bit line and a complementary read bit line based on the voltage difference. The isolation circuit electrically connects the bit line and the complementary bit line to the complementary read bit line and the read bit line, respectively. The offset cancellation circuit electrically connects the bit line and the complementary bit line to the read bit line and the complementary read bit line, respectively. The equalizer circuit equalizes the bit line and the complementary bit line to a precharge voltage. The equalizer circuit includes an equalization transistor having a source, a drain, and a gate configured to receive an equalization signal. An active region is formed such that sources of the equalization transistors of a first bit line sense amplifier and a second bit line sense amplifier are connected to each other, and sources of the equalization transistors of the first bit line sense amplifier and a third bit line sense amplifier are separated from each other.

[0008] According to an exemplary embodiment, a sense amplifier circuit includes a plurality of bit line sense amplifiers. Each of the plurality of bit line sense amplifiers includes an amplification circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. The amplification circuit is electrically connected to a bit line and a complementary bit line, reads a voltage difference between the bit line and the complementary bit line based on a first control signal and a second control signal, and adjusts voltages of a read bit line and a complementary read bit line based on the voltage difference. The isolation circuit electrically connects the bit line and the complementary bit line to the complementary read bit line and the read bit line, respectively, based on an isolation signal. The offset cancellation circuit electrically connects the bit line and the complementary bit line to the read bit line and the complementary read bit line, respectively, based on an offset cancellation signal. The equalizer circuit is electrically connected to the complementary read bit line and equalizes the bit line and the complementary bit line to a precharge voltage. The equalizer circuit includes an equalization transistor having a source configured to receive the precharge voltage, a gate configured to receive an equalization signal, and a drain electrically connected to the complementary read bit line. Sources of a first equalization transistor and a second equalization transistor included in a first bit line sense amplifier and a second bit line sense amplifier adjacent to each other are connected to each other, and a first active region corresponding to the sources of the first equalization transistor and the second equalization transistor is integrally formed. Sources of a third equalization transistor and a fourth equalization transistor included in a third bit line sense amplifier and a fourth bit line sense amplifier adjacent to each other and spaced apart from the first bit line sense amplifier and the second bit line sense amplifier are connected to each other, and a second active region corresponding to the sources of the third equalization transistor and the fourth equalization transistor is integrally formed. The sources of the first equalization transistor and the second equalization transistor and the sources of the third equalization transistor and the fourth equalization transistor are separated from each other, and an active cut region is formed between the first active region and the second active region to separate the first active region from the second active region.

[0009] In a sense amplifier circuit and a semiconductor memory device according to an exemplary embodiment, some sources of equalization transistors included in a bit line sense amplifier and corresponding active regions may be separated. For example, sources of equalization transistors included in the same bit line sense amplifier group may be electrically connected to each other, while sources of equalization transistors included in different bit line sense amplifier groups may be electrically separated from each other. Accordingly, compared to a conventional sense amplifier circuit, defects or failures in the sense amplifier circuit can be prevented, and the size of the sense amplifier circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary non-limiting example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a sense amplifier circuit according to an exemplary embodiment.

[0012] Figure 2 illustrates Figure 1 an example of a sense amplifier circuit.

[0013] Figure 3 is a circuit diagram illustrating an example of a bit-line sense amplifier included in the sense amplifier circuit according to an exemplary embodiment.

[0014] Figure 4A , Figure 4B and Figure 4C illustrates Figure 2 an example of the layout of the sense amplifier circuit.

[0015] Figure 5A is a cross-sectional view taken along line A-A' in Figure 4C .

[0016] Figure 5B is a cross-sectional view taken along line B-B' in Figure 4C .

[0017] Figure 6A illustrates Figure 2 an example of the layout of the sense amplifier circuit.

[0018] Figure 6B is a cross-sectional view taken along line C-C' in Figure 6A .

[0019] Figure 7 is a circuit diagram illustrating an example of a bit-line sense amplifier included in the sense amplifier circuit according to an exemplary embodiment.

[0020] Figure 8 illustrates Figure 1 an example of the sense amplifier circuit.

[0021] Figure 9 illustrates Figure 8 an example of the layout of the sense amplifier circuit.

[0022] Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A and Figure 13B are diagrams for describing the operation of a bit-line sense amplifier included in the sense amplifier circuit according to an exemplary embodiment.

[0023] Figure 14 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0024] Figure 15 is an illustration of Figure 14 an example of a memory cell array included in a semiconductor memory device.

[0025] Figure 16 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0026] Figure 17 is a block diagram illustrating an example of a memory module that can be used in a memory system according to an exemplary embodiment.

[0027] Figure 18 is a block diagram illustrating an electronic system including a memory module according to an exemplary embodiment. Detailed Description

[0028] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals refer to like elements.

[0029] Expressions such as "first", "second", etc. used herein may refer to various different elements regardless of their order and / or priority, and are merely used to distinguish one element from another, without limiting the elements.

[0030] Figure 1 is a block diagram illustrating a sense amplifier circuit according to an exemplary embodiment.

[0031] Referring to Figure 1 , the sense amplifier circuit 100 includes a plurality of bit line sense amplifiers BLSA.

[0032] In some exemplary embodiments, as will be described with reference to Figure 14 , the sense amplifier circuit 100 may be included in a semiconductor memory device and may perform an operation of reading data stored in the semiconductor memory device.

[0033] Each of the plurality of bit line sense amplifiers BLSA may be connected to a bit line and a complementary bit line, and may include an amplification circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. The detailed circuit configuration of each bit line sense amplifier will be described with reference to Figure 3 and Figure 7 .

[0034] Multiple bit - line sense amplifiers BLSA can be divided or classified into multiple groups of bit - line sense amplifiers 101, 102, and 103. For example, the first group of bit - line sense amplifiers 101 can include two or more bit - line sense amplifiers BLSA, the second group of bit - line sense amplifiers 102 can include two or more bit - line sense amplifiers BLSA, and the Kth group of bit - line sense amplifiers 103 can include two or more bit - line sense amplifiers BLSA, where K is a positive integer greater than or equal to 2.

[0035] Multiple bit - line sense amplifiers BLSA can receive a pre - charge voltage VBL. For example, the pre - charge voltage VBL can be provided to an equalizer circuit. For example, as will be referenced Figure 3 and Figure 7 described, the equalizer circuit can include equalization transistors, and the pre - charge voltage VBL can be applied to the source (or source electrode or first electrode) of the equalization transistors.

[0036] In some example embodiments, the sources of the equalization transistors of the bit - line sense amplifiers BLSA can be completely separated from each other or partially connected. For example, the sources of the equalization transistors included in the bit - line sense amplifiers within the same group of bit - line sense amplifiers can be connected to each other, while the sources of the equalization transistors included in the bit - line sense amplifiers in different groups of bit - line sense amplifiers can be separated or isolated from each other.

[0037] For example, as Figure 1 shown, the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the first group of bit - line sense amplifiers 101 are electrically connected to each other, the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the second group of bit - line sense amplifiers 102 are electrically connected to each other, and the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the Kth group of bit - line sense amplifiers 103 are electrically connected to each other. Additionally, as shown by the 'X' marks in Figure 1 , the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the first group of bit - line sense amplifiers 101 and the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the second group of bit - line sense amplifiers 102 are electrically separated from each other, and the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the second group of bit - line sense amplifiers 102 and the sources of the equalization transistors included in the bit - line sense amplifiers BLSA included in the Kth group of bit - line sense amplifiers 103 are electrically separated from each other.

[0038] In other words, when multiple bit line sense amplifiers BLSA include a first bit line sense amplifier, a second bit line sense amplifier adjacent to the first bit line sense amplifier, and a third bit line sense amplifier adjacent to the second bit line sense amplifier, and when the first bit line sense amplifier and the second bit line sense amplifier are included in the same bit line sense amplifier group and the first bit line sense amplifier and the third bit line sense amplifier are included in different bit line sense amplifier groups, the active region may be formed such that the sources of the equalization transistors of the first bit line sense amplifier and the second bit line sense amplifier are electrically connected to each other, and since the first bit line sense amplifier and the third bit line sense amplifier are located in different bit line sense amplifier groups, the sources of the equalization transistors of the first bit line sense amplifier and the third bit line sense amplifier are electrically separated or isolated from each other.

[0039] In some example embodiments, as will be described with reference to Figure 4A , Figure 4B and Figure 4C , each bit line sense amplifier BLSA among the multiple bit line sense amplifiers BLSA may include an active region corresponding to the source of the equalization transistor. For example, the feature that the sources of the equalization transistors included in the bit line sense amplifiers included in the same bit line sense amplifier group are connected to each other may represent or indicate that the active regions corresponding to the sources of the equalization transistors included in the bit line sense amplifiers included in the same bit line sense amplifier group are connected to each other and are integrally formed. For example, the feature that the sources of the equalization transistors included in the bit line sense amplifiers included in different bit line sense amplifier groups are separated from each other may represent or indicate that the active regions corresponding to the sources of the equalization transistors included in the bit line sense amplifiers included in different bit line sense amplifier groups are separated from each other and an active cut region is formed between the active regions.

[0040] Figure 2 is a block diagram illustrating an example of a sense amplifier circuit of Figure 1 .

[0041] Referring to Figure 2 , the sense amplifier circuit 100a includes a first bit line sense amplifier BLSA11, a second bit line sense amplifier BLSA12, a third bit line sense amplifier BLSA21, and a fourth bit line sense amplifier BLSA22.

[0042] In the Figure 2 example, the first bit line sense amplifier BLSA11 and the second bit line sense amplifier BLSA12 form one bit line sense amplifier group, and the third bit line sense amplifier BLSA21 and the fourth bit line sense amplifier BLSA22 form another bit line sense amplifier group.

[0043] For example, the first bit line sense amplifier BLSA11 and the second bit line sense amplifier BLSA12, which are paired bit line sense amplifiers, can be set or arranged adjacent to each other and can form the first group of bit line sense amplifiers or can be included in the first group of bit line sense amplifiers. For example, the third bit line sense amplifier BLSA21 and the fourth bit line sense amplifier BLSA22, which are another pair of bit line sense amplifiers, can be set or arranged adjacent to each other, can be spaced apart from the first bit line sense amplifier BLSA11 and the second bit line sense amplifier BLSA12, and can form the second group of bit line sense amplifiers or can be included in the second group of bit line sense amplifiers.

[0044] As described in the reference Figure 1 The sources of the first equalization transistors included in the first group of bit line sense amplifiers (e.g., the sources of the first equalization transistors included in the first bit line sense amplifier BLSA11 and the second bit line sense amplifier BLSA12) can be electrically connected to each other, and the active regions corresponding to the sources of the first equalization transistors can be integrally formed. Similarly, the sources of the second equalization transistors included in the second group of bit line sense amplifiers (e.g., the sources of the second equalization transistors included in the third bit line sense amplifier BLSA21 and the fourth bit line sense amplifier BLSA22) can be electrically connected to each other, and the active regions corresponding to the sources of the second equalization transistors can be integrally formed. The source of the first equalization transistor and the source of the second equalization transistor can be electrically separated from each other, and the active region corresponding to the source of the first equalization transistor and the active region corresponding to the source of the second equalization transistor can be separated from each other.

[0045] Although Figure 2 two groups of bit line sense amplifiers are illustrated, the exemplary embodiments are not limited thereto, and the number of groups of bit line sense amplifiers can be determined in various ways according to the exemplary embodiments. In another example, the number of groups of bit line sense amplifiers can be one or three or more.

[0046] In a conventional sense amplifier circuit, the sources of all the equalization transistors included in all the bit line sense amplifiers are connected to each other.

[0047] However, in the sense amplifier circuit according to the exemplary embodiments, some of the sources of the equalization transistors included in the bit line sense amplifiers and the corresponding active regions can be separated. For example, a plurality of bit line sense amplifiers can be divided into several groups of bit line sense amplifiers. The sources of the equalization transistors included in the same group of bit line sense amplifiers can be electrically connected to each other, and the sources of the equalization transistors included in different groups of bit line sense amplifiers can be electrically separated from each other. Therefore, compared with the conventional sense amplifier circuit in which the sources of all the equalization transistors are connected to each other, defects or failures in the sense amplifier circuit can be prevented, and the size of the sense amplifier circuit can be reduced.

[0048] Figure 3 is a circuit diagram illustrating an example of a bit - line sense amplifier included in a sense - amplifier circuit according to an exemplary embodiment.

[0049] Reference Figure 3 , the bit - line sense amplifier 110a includes amplifier circuits 121 and 122, offset - cancellation circuits 131 and 132, an isolation circuit 135, and an equalizer circuit 141. For example, the bit - line sense amplifier 110a can be one of multiple bit - line sense amplifiers BLSA in Figure 1 and / or one of the bit - line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 in Figure 2 .

[0050] In Figure 3 , for ease of description, the bit - line sense amplifier 110a, the first memory cell MC1, and the second memory cell MC2 are illustrated.

[0051] The bit - line sense amplifier 110a can be connected to a bit line BL and a complementary bit line BLB disposed opposite to the bit line BL, and can be connected to a control line 111 and a complementary control line 112 disposed opposite to the control line 111. The bit - line sense amplifier 110a can be connected to the first memory cell MC1 through the bit line BL and to the second memory cell MC2 through the complementary bit line BLB, respectively. For example, the bit - line sense amplifier 110a, the first memory cell MC1, and the second memory cell MC2 can constitute a semiconductor memory device.

[0052] The first memory cell MC1 can include a cell transistor CT1 connected to a word line WLi and the bit line BL, respectively, and a cell capacitor CC1 connected to a ground voltage VSS. The second memory cell MC2 can include a cell transistor CT2 connected to a word line WLj and the complementary bit line BLB, respectively, and a cell capacitor CC2 connected to the ground voltage VSS.

[0053] Each of the amplifier circuits 121 and 122 can be electrically connected to the bit line BL and the complementary bit line BLB, can read a voltage difference between the bit line BL and the complementary bit line BLB based on a first control signal LA and a second control signal LAB, and can adjust voltages of a read bit line SBL and a complementary read bit line SBLB based on the read voltage difference.

[0054] In some example embodiments, the amplification circuits 121 and 122 may include a p-type amplifier 121 and an n-type amplifier 122. The p-type amplifier 121 may include a first p-type metal oxide semiconductor (PMOS) transistor MP1 and a second PMOS transistor MP2, while the n-type amplifier 122 may include a first n-type metal oxide semiconductor (NMOS) transistor MN1 and a second NMOS transistor MN2. However, in another example, the amplification circuit 121 may be an n-type amplifier, and the amplification circuit 122 may be a p-type amplifier.

[0055] The first PMOS transistor MP1 may be connected between a control line 111 supplied with a first control signal LA and a readout bit line SBL (e.g., between a first node N1 and the readout bit line SBL). In this case, the first PMOS transistor MP1 may include a gate (or gate electrode or control electrode) connected to a complementary readout bit line SBLB (or a fourth node N4). The second PMOS transistor MP2 may be connected between the control line 111 and the complementary readout bit line SBLB. In this case, the second PMOS transistor MP2 may include a gate connected to the readout bit line SBL (or a third node N3).

[0056] The first NMOS transistor MN1 may be connected between a complementary control line 112 supplied with a second control signal LAB and the readout bit line SBL (e.g., between a second node N2 and the readout bit line SBL). In this case, the first NMOS transistor MN1 may include a gate connected to a bit line BL (or a fifth node N5). The second NMOS transistor MN2 may be connected between the complementary control line 112 and the complementary readout bit line SBLB. In this case, the second NMOS transistor MN2 may include a gate connected to a complementary bit line BLB (or a sixth node N6).

[0057] The offset cancellation circuit 131 may be electrically connected between the bit line BL and the readout bit line SBL based on an offset cancellation signal P1. Similarly, the offset cancellation circuit 132 may be electrically connected between the complementary bit line BLB and the complementary readout bit line SBLB based on the offset cancellation signal P1.

[0058] The offset cancellation circuit 131 may include a first offset cancellation transistor OC1, and the offset cancellation circuit 132 may include a second offset cancellation transistor OC2. In this case, the first offset cancellation transistor OC1 may be connected between the bit line BL and the readout bit line SBL, and may include a gate for receiving the offset cancellation signal P1. Similarly, the second offset cancellation transistor OC2 may be connected between the complementary bit line BLB and the complementary readout bit line SBLB, and may include a gate for receiving the offset cancellation signal P1.

[0059] The isolation circuit 135 may be electrically connected between the bit line BL and the complementary bit line BLB based on the isolation signal P2 to the complementary sense bit line SBLB and the sense bit line SBL, respectively.

[0060] In this case, the isolation circuit 135 may include a first isolation transistor ISO1 and a second isolation transistor ISO2. The first isolation transistor ISO1 may be connected between the bit line BL and the complementary read bit line SBLB, and the first isolation transistor ISO1 may include a gate for receiving an isolation signal P2. The second isolation transistor ISO2 may be connected between the complementary bit line BLB and the read bit line SBL, and the second isolation transistor ISO2 may include a gate for receiving the isolation signal P2.

[0061] The equalizer circuit 141 may be electrically connected between the precharge voltage VBL and the complementary sense bit line SBLB, and may equalize the bit line BL and the complementary bit line BLB to the precharge voltage VBL based on the equalization signal PEQ. In this case, the equalizer circuit 141 may include an equalization transistor EQ. The equalization transistor EQ may include a source (or a first electrode), a drain (or a drain electrode or a second electrode), and a gate for receiving the equalization signal PEQ. As described above, the sources of the equalization transistors EQ included in the same bit line sense amplifier group may be electrically connected to each other, while the sources of the equalization transistors EQ included in different bit line sense amplifier groups may be electrically separated from each other.

[0062] Figure 4A , Figure 4B , Figure 4C , Figure 5A and Figure 5B It's a picture. Figure 2 FIG. 1 is a diagram of an example of a layout of a sense amplifier circuit.

[0063] refer to Figure 4A , Figure 4B and Figure 4C , which shows a top view of a portion of the layout of the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 included in the sense amplifier circuit 100a. For example, when each of the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 has Figure 3 When the circuit configuration shown in the figure is Figure 4A , Figure 4B and Figure 4C Can include illustrations Figure 3 Layout of the right half of the components in the bit line sense amplifier 110a.

[0064] like Figure 4A , Figure 4B and Figure 4CAs depicted, two directions that are each parallel or substantially parallel to the first surface (e.g., the top surface) of the semiconductor substrate 10 and cross each other are referred to as the first direction D1 (e.g., the X-axis direction) and the second direction D2 (e.g., the Y-axis direction). Additionally, the direction perpendicular or substantially perpendicular to the first surface of the semiconductor substrate 10 is referred to as the third direction D3 (e.g., the Z-axis direction). For example, the first direction D1 and the second direction D2 may be perpendicular or substantially perpendicular to each other. Additionally, the third direction D3 may be perpendicular or substantially perpendicular to both the first direction D1 and the second direction D2. Furthermore, the directions indicated by the arrows in the figure and their opposite directions are considered to be the same direction. The definitions of the first direction D1, the second direction D2, and the third direction D3 are the same in the subsequent figures.

[0065] The region where the equalization transistor EQ, the second offset cancellation transistor OC2, the second isolation transistor ISO2, and the second NMOS transistor MN2 among the components included in the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 are formed may include or may be divided into a first region 20, a second region 30 adjacent to the first region 20, and a third region 40 adjacent to the second region 30. In this case, the first region 20 may be disposed on the second region 30 along the second direction D2, and the second region 20 may be disposed on the third region 40 along the second direction D2.

[0066] The bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 may include active regions AR11, AR12, AR13, AR14, AR21, AR22, AR23, and AR24 formed in the semiconductor substrate 10, and may include gate patterns 21, 31, 32, 41, 42, 43, and 44 formed on the semiconductor substrate 10 and the active regions AR11, AR12, AR13, AR14, AR21, AR22, AR23, and AR24.

[0067] The active region AR11 may be disposed in the first region 20 and may have a rectangular shape in a top view with a long side parallel to the first direction D1 and a short side parallel to the second direction D2. The active regions AR12 and AR13 may be disposed in the first region 20 and the second region 30, and in a top view, each of the active regions AR12 and AR13 may have a rectangular shape with a long side parallel to the second direction D2 and a short side parallel to the first direction D1. The active regions AR12 and AR13 may be disposed below the active region AR11 along the second direction D2 and may be spaced apart from each other along the first direction D1. In this case, a part of the active region AR12 may be disposed in the first region 20, and another part of the active region AR12 may be disposed in the second region 30. Similarly, a part of the active region AR13 may be disposed in the first region 20, and another part of the active region AR13 may be disposed in the second region 30. The active region AR14 may be disposed in the third region 40 and may be spaced apart from the active regions AR12 and AR13 along the second direction D2. For ease of explanation, the active regions AR11, AR12, and AR13 are described as separate regions. However, the exemplary embodiments are not limited thereto. For example, the active regions AR11, AR12, and AR13 may be integrally formed to form one active region.

[0068] The arrangement and shape of the active regions AR21, AR22, AR23, and AR24 may be substantially the same as the arrangement and shape of the active regions AR11, AR12, AR13, and AR14. For example, the active region AR21 may be disposed in the first region 20, the active regions AR22 and AR23 may be disposed in the first region 20 and the second region 30, and the active region AR24 may be disposed in the third region 40. Additionally, the active regions AR22 and AR23 may be disposed below the active region AR21 along the second direction D2, and the active region AR24 may be spaced apart from the active regions AR22 and AR23 along the second direction D2.

[0069] The gate pattern 21 may extend along a first direction D1 over the active regions AR12 and AR13 and the active regions AR22 and AR23 in the first region 20, and may receive an equalization signal PEQ. The gate patterns 31 and 32 may extend along the first direction D1 over the active regions AR12 and AR13 and the active regions AR22 and AR23 in the second region 30, may be spaced apart from each other along a second direction D2, and may receive an offset cancellation signal P1 and an isolation signal P2, respectively. The gate patterns 41 and 42 may extend along the second direction D2 over the active region AR14 in the third region 40, and may be spaced apart from each other along the first direction D1. The gate patterns 43 and 44 may extend along the second direction D2 over the active region AR24 in the third region 40, and may be spaced apart from each other along the first direction D1.

[0070] The active regions AR11, AR12, AR13, and AR14 and the gate patterns 21, 31, 32, 41, and 42 may correspond to an equalization transistor EQ, a second offset cancellation transistor OC2, a second isolation transistor ISO2, and a second NMOS transistor MN2 included in the bit line sense amplifiers BLSA11 and BLSA12.

[0071] For example, the active regions AR11, AR12, and AR13 in the first region 20 and the gate pattern 21 in the first region 20 may correspond to the equalization transistors EQ of the bit line sense amplifiers BLSA11 and BLSA12. In this case, the active regions AR11, AR12, and AR13 in the first region 20 and the gate pattern 21 in the first region 20 may form the equalization transistors EQ of the bit line sense amplifiers BLSA11 and BLSA12. The active region AR12 in the second region 30 and the gate pattern 31 in the second region 30 may correspond to or form the second offset cancellation transistor OC2 of the bit line sense amplifier BLSA11. In this case, the active region AR12 in the second region 30 and the gate pattern 31 in the second region 30 may form the second offset cancellation transistor OC2 of the bit line sense amplifier BLSA11. The active region AR13 in the second region 30 and the gate pattern 31 in the second region 30 may correspond to the second offset cancellation transistor OC2 of the bit line sense amplifier BLSA12. In this case, the active region AR13 in the second region 30 and the gate pattern 31 in the second region 30 may form the second offset cancellation transistor OC2 of the bit line sense amplifier BLSA12. The active region AR12 in the second region 30 and the gate pattern 32 in the second region 30 may correspond to the second isolation transistor ISO2 of the bit line sense amplifier BLSA11, and the active region AR13 in the second region 30 and the gate pattern 32 in the second region 30 may correspond to the second isolation transistor ISO2 of the bit line sense amplifier BLSA12. In this case, the active region AR12 in the second region 30 and the gate pattern 32 in the second region 30 may form or constitute the second isolation transistor ISO2 of the bit line sense amplifier BLSA11, and the active region AR13 in the second region 30 and the gate pattern 32 in the second region 30 may form or constitute the second isolation transistor ISO2 of the bit line sense amplifier BLSA12. The active region AR14 in the third region 40 and the gate pattern 41 in the third region 40 may correspond to the second NMOS transistor MN2 of the bit line sense amplifier BLSA11, and the active region AR14 in the third region 40 and the gate pattern 42 in the third region 40 may correspond to the second NMOS transistor MN2 of the bit line sense amplifier BLSA12. In this case, the active region AR14 in the third region 40 and the gate pattern 41 in the third region 40 may form the second NMOS transistor MN2 of the bit line sense amplifier BLSA11, and the active region AR14 in the third region 40 and the gate pattern 42 in the third region 40 may form the second NMOS transistor MN2 of the bit line sense amplifier BLSA12.

[0072] Similarly, the active regions AR21, AR22, AR23, and AR24 and the gate patterns 21, 31, 32, 43, and 44 may correspond to an equalization transistor EQ, a second offset cancellation transistor OC2, a second isolation transistor ISO2, and a second NMOS transistor MN2 included in the bit line sense amplifiers BLSA21 and BLSA22.

[0073] Some of the active regions AR11 and AR14 for the bit line sense amplifiers BLSA11 and BLSA12 may be connected to each other and may be integrally formed, so that the bit line sense amplifiers BLSA11 and BLSA12 may be arranged adjacent to each other and may form a pair. Similarly, some of the active regions AR21 and AR24 for the bit line sense amplifiers BLSA21 and BLSA22 may be connected to each other and may be integrally formed, so that the bit line sense amplifiers BLSA21 and BLSA22 may be arranged adjacent to each other and may form a pair. In another example, all of the active regions AR11, AR12, AR13, and AR14 for the bit line sense amplifiers BLSA11 and BLSA12 and all of the active regions AR21, AR22, AR23, and AR24 for the bit line sense amplifiers BLSA21 and BLSA22 may be separated from each other, and thus the bit line sense amplifiers BLSA11 and BLSA12 may be arranged to be spaced apart from the bit line sense amplifiers BLSA21 and BLSA22.

[0074] In some example embodiments, in order to separate the sources of the equalization transistors EQ of the bit line sense amplifiers BLSA11 and BLSA12 from the sources of the equalization transistors EQ of the bit line sense amplifiers BLSA21 and BLSA22, for example, in order to separate the active region AR11 and the active region AR21 from each other, an active cut region ACR1 may be formed between the active region AR11 and the active region AR21. For example, in a manufacturing process, the active regions AR11 and AR21 may be integrally formed and then the active cut region ACR1 may be formed between the active region AR11 and the active region AR21 to separate the active region AR11 and the active region AR21 from each other.

[0075] Conventionally, the active regions AR11 and AR21 are connected to each other and are integrally formed. However, in the sense amplifier circuit according to the example embodiments, the active regions AR11 and AR21 may be separated from each other by forming the active cut region ACR1, and thus defects in the sense amplifier circuit may be prevented and the size of the sense amplifier circuit may be reduced. In addition, the equalization transistor EQ and the second offset cancellation transistor OC2 may be formed in adjacent active regions (or the same active region), and thus the size of the sense amplifier circuit may be further reduced.

[0076] Reference Figure 5A , which shows a cross-sectional view taken along line A-A' in Figure 4C .

[0077] In the semiconductor substrate 10, the active regions AR11 and AR12 (or the first region 20) may be defined by the device isolation region STI, and the doped regions 23a and 23b serving as the source and drain of the equalization transistors EQ of the bit line sense amplifiers BLSA11 and BLSA12 may be formed. For example, the doped regions 23a and 23b may be N+ doped regions, the doped region 23a may be included in the active region AR11, and the doped region 23b may be included in the active region AR12. Thereafter, a gate insulating layer 21a and a gate pattern 21 provided on the gate insulating layer 21 and serving as the gate of the equalization transistor EQ may be sequentially stacked on the semiconductor substrate 10 along the third direction D3 (e.g., the thickness direction).

[0078] The first direct contact DC1 may be provided on the doped region 23a included in the active region AR11 and may be electrically connected to the doped region 23a. In this case, the first direct contact DC1 may be in direct contact with the doped region 23a. The first bit line metal pattern BLMP1 may be provided on the first direct contact DC1 and may be electrically connected to the first direct contact DC1. The second direct contact DC2 may be provided on the first bit line metal pattern BLMP1 and may be electrically connected to the first bit line metal pattern BLMP1. The second bit line metal pattern BLMP2 may be provided on the second direct contact DC2 and may be electrically connected to the second direct contact DC2. In this case, the second bit line metal pattern BLMP2 may be electrically connected to the doped region 23a.

[0079] Accordingly, the precharge voltage VBL may be supplied to the doped region 23a (e.g., to the active region AR11) through the second bit line metal pattern BLMP2, the second direct contact DC2, the first bit line metal pattern BLMP1, and the first direct contact DC1.

[0080] Reference Figure 5B , which shows a cross-sectional view taken along line B-B' in Figure 4C .

[0081] In the semiconductor substrate 10, a doped region 24a serving as the source of the equalization transistors EQ of the bit line sense amplifiers BLSA21 and BLSA22 can be formed. For example, the doped region 24a can be an N+ doped region and can be included in the active region AR21. An active cut region ACR1 can be formed between the active region AR11 and the active region AR21. In this case, the active cut region ACR1 can be formed between the doped region 23a and the doped region 24a.

[0082] A third direct contact DC3 can be disposed on the doped region 24a included in the active region AR21 along a third direction D3 and can be electrically connected to the doped region 24a. A third bit line metal pattern BLMP3 can be disposed on the third direct contact DC3 and can be electrically connected to the third direct contact DC3. A fourth direct contact DC4 can be disposed on the third bit line metal pattern BLMP3 and can be electrically connected to the third bit line metal pattern BLMP3. A second bit line metal pattern BLMP2 can be extended to be disposed on the fourth direct contact DC4 and can be electrically connected to the fourth direct contact DC4. In this case, the second bit line metal pattern BLMP2 can be electrically connected to the doped regions 23a and 24a.

[0083] Accordingly, a precharge voltage VBL can be provided to the doped region 24a (e.g., to the active region AR21) through the second bit line metal pattern BLMP2, the fourth direct contact DC4, the third bit line metal pattern BLMP3, and the third direct contact DC3.

[0084] As described above, according to an exemplary embodiment, a double stack BP structure in which direct contacts and bit line metal patterns are stacked in two layers can be applied to or adapted for a sense amplifier circuit. Accordingly, when the active cut region ACR1 is formed to separate the active regions AR11 and AR21, the precharge voltage VBL can be efficiently provided to the active regions AR11 and AR21.

[0085] Figure 6A is a diagram illustrating Figure 2 an example of the layout of a sense amplifier circuit. Figure 6B is a cross-sectional view taken along line Figure 6A C-C' of

[0086] Referring to Figure 6A , a top view illustrating a part of the layout of the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 included in the sense amplifier circuit 100a is shown.

[0087] Except that a conductive pattern 27 is further formed, Figure 6A the example of Figure 4A ,Figure 4B and Figure 4C are substantially the same. For the sake of brevity, descriptions that are repetitive or overlapping with Figure 4A , Figure 4B and Figure 4C will be omitted.

[0088] The conductive pattern 27 may be spaced apart from the gate pattern 21 along the second direction D2 and may partially overlap with the first region 20. The conductive pattern 27 may extend in the first direction D1. In this case, the conductive pattern 27 may be partially disposed on the active cut region ACR1 along the third direction D3. The conductive pattern 27 may transmit the pre-charge voltage VBL and may apply the pre-charge voltage VBL to the source of the equalization transistor EQ.

[0089] Refer to Figure 6B , which illustrates a cross-sectional view taken along line C-C' in Figure 6A . For the sake of brevity, descriptions that are repetitive or overlapping with Figure 5A will be omitted.

[0090] The insulating layer 27a and the conductive pattern 27 may be sequentially stacked on the device isolation region STI and the doped region 23a along the third direction (e.g., the thickness direction) and may be spaced apart from the gate insulating layer 21a and the gate pattern 21 disposed on the gate insulating layer 21a. The first direct contact DC1 may be electrically connected to the doped region 23a serving as the source of the equalization transistor EQ by penetrating at least a part of the wiring structure including the conductive pattern 27 and the insulating layer 27a in the third direction D3. Since the pre-charge voltage VBL is applied to the conductive pattern 27, the pre-charge voltage VBL may be provided to the source of the equalization transistor EQ through the first direct contact DC1.

[0091] As described above, the doped region 23a serving as the source of the equalization transistor EQ may be electrically connected to the conductive pattern 27 through the first direct contact DC1 that penetrates at least a part of the wiring structure including the conductive pattern 27 and the insulating layer 27a, and the conductive pattern 27 may receive the pre-charge voltage VBL and may provide the pre-charge voltage VBL to the doped region 23a through the first direct contact DC1. Since the pre-charge voltage VBL does not need to be connected to the doped region 23a through an additional metal contact, the width of the bit line metal pattern may be reduced, and the pitch corresponding to the gap between the bit line metal patterns may be increased. Therefore, the size of the bit line sense amplifier may be reduced, and the wiring freedom may be increased.

[0092] Figure 7 is a circuit diagram illustrating an example of a bit line sense amplifier included in a sense amplifier circuit according to an exemplary embodiment.

[0093] Refer toFigure 7 , the bit line sense amplifier 110b may include amplifier circuits 121 and 122, offset cancellation circuits 131 and 132, isolation circuit 135, and equalizer circuit 142.

[0094] Except that the configuration of the equalizer circuit 142 is partially changed, Figure 7 the example of Figure 3 may be substantially the same as Figure 3 the example of. For simplicity, the description that is repeated or overlapped with

[0095] The equalizer circuit 142 may be connected between the precharge voltage VBL and the read bit line SBL, and may equalize the bit line BL and the complementary bit line BLB to the precharge voltage VBL based on the equalization signal PEQ. The equalizer circuit 142 may include an equalization transistor EQ. The equalization transistor EQ may include a source, a drain, and a gate for receiving the equalization signal PEQ. As described above, the sources of the equalization transistors EQ included in the same bit line sense amplifier group may be electrically connected to each other, while the sources of the equalization transistors EQ included in different bit line sense amplifier groups may be electrically separated from each other.

[0096] In some example embodiments, when each of the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 included in the sense amplifier circuit 100a has Figure 7 the illustrated circuit configuration, Figure 4A , Figure 4B and Figure 4C the illustrated layout may correspond to Figure 7 the left half of the components in the bit line sense amplifier 110b of

[0097] Figure 8 is a block diagram illustrating an example of the Figure 1 sense amplifier circuit of. For simplicity, the description that is repeated or overlapped with Figure 2 will be omitted.

[0098] Refer to Figure 8, the sense amplifier circuit 100b may include a first bit line sense amplifier BLSA31, a second bit line sense amplifier BLSA32, a third bit line sense amplifier BLSA33, a fourth bit line sense amplifier BLSA34, a fifth bit line sense amplifier BLSA41, a sixth bit line sense amplifier BLSA42, a seventh bit line sense amplifier BLSA43, and an eighth bit line sense amplifier BLSA44.

[0099] In Figure 8 the example of, the first to fourth bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may form a group of bit line sense amplifiers, and the fifth to eighth bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may form another group of bit line sense amplifiers. In this case, each of the first to fourth bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may be connected to a precharge voltage VBL. Additionally, each of the fifth to eighth bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may be connected to the precharge voltage VBL.

[0100] For example, the first to fourth bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may be included in a first group of bit line sense amplifiers. Among the first group of bit line sense amplifiers, the first bit line sense amplifier BLSA31 and the second bit line sense amplifier BLSA32 may be arranged adjacent to each other, the third bit line sense amplifier BLSA33 and the fourth bit line sense amplifier BLSA34 may be arranged adjacent to each other, and the first bit line sense amplifier BLSA31 and the second bit line sense amplifier BLSA32 may be spaced apart from the third bit line sense amplifier BLSA33 and the fourth bit line sense amplifier BLSA34. In this case, the sources of the first equalization transistors included in the first group of bit line sense amplifiers may be electrically connected to each other, and the active regions corresponding to the sources of the first equalization transistors may be integrally formed.

[0101] Similarly, fifth to eighth bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may be included in the second group of bit line sense amplifiers. Among the second group of bit line sense amplifiers, the fifth bit line sense amplifier BLSA41 and the sixth bit line sense amplifier BLSA42 may be arranged adjacent to each other, the seventh bit line sense amplifier BLSA43 and the eighth bit line sense amplifier BLSA44 may be arranged adjacent to each other, and the fifth bit line sense amplifier BLSA41 and the sixth bit line sense amplifier BLSA42 may be spaced apart from the seventh bit line sense amplifier BLSA43 and the eighth bit line sense amplifier BLSA44. In this case, the sources of the second equalization transistors included in the second group of bit line sense amplifiers may be electrically connected to each other, and the active regions corresponding to the sources of the second equalization transistors may be integrally formed.

[0102] The source of the first equalization transistor and the source of the second equalization transistor may be electrically isolated from each other, and the active region corresponding to the source of the first equalization transistor and the active region corresponding to the source of the second equalization transistor may be separated from each other.

[0103] Figure 9 is a diagram illustrating Figure 8 an example of the layout of the sense amplifier circuit. Descriptions that are repetitive or overlapping with Figure 4A , Figure 4B , Figure 4C , Figure 5A and Figure 5B will be omitted.

[0104] Refer to Figure 9 , a top view illustrating a part of the layout of the bit line sense amplifiers BLSA31, BLSA32, BLSA33, BLSA34, BLSA41, BLSA42, BLSA43, and BLSA44 included in the sense amplifier circuit 100b. For example, when each bit line sense amplifier has the circuit configuration illustrated in Figure 3 , Figure 9 may include a layout of the right half of the components in the bit line sense amplifier 110a illustrating Figure 3 . For example, when each bit line sense amplifier has the circuit configuration illustrated in Figure 7 , Figure 9 may include a layout of the left half of the components in the bit line sense amplifier 110b illustrating Figure 7 .

[0105] The configurations of the bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may be the same as Figure 4A , Figure 4B and Figure 4CThe configurations of the bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 are substantially the same. However, different from the Figure 4A , Figure 4B and Figure 4C bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22, the bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may include the sources of the equalization transistors EQ included in the bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 and the corresponding active regions are connected to each other and integrally formed. Similarly, the configurations of the bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may be substantially the same as those of the Figure 4A , Figure 4B and Figure 4C bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22. However, different from the Figure 4A , Figure 4B and Figure 4C bit line sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22, the bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may include the sources of the equalization transistors EQ included in the bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 and the corresponding active regions are connected to each other and integrally formed.

[0106] In some example embodiments, in order to separate the sources of the equalization transistors EQ of the bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 and the corresponding active regions from those of the bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44, an active cut region ACR2 may be formed. In this case, the active cut region ACR2 may be formed between the bit line sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 and the bit line sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44.

[0107] Although the example embodiments are described based on examples where the number of bit line sense amplifiers included in one group of bit line sense amplifiers is two and four, the example embodiments are not limited thereto, and the number of bit line sense amplifiers included in one group of bit line sense amplifiers may be determined in various ways according to the example embodiments.

[0108] Figure 10 , Figure 11 ,Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A and Figure 13B are diagrams for describing the operation of the bit line sense amplifier included in the sense amplifier circuit according to the exemplary embodiment.

[0109] Referring to Figure 10 , an equivalent circuit of the bit line sense amplifier 110a of Figure 3 is illustrated. For simplicity of the drawings, the equalization transistor EQ, the first offset cancellation transistor OC1 and the second offset cancellation transistor OC2, and the first isolation transistor ISO1 and the second isolation transistor ISO2 are illustrated by dashed lines. Reference will be made to Figure 11 , Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E to describe in detail Figure 10 the operation of the equivalent circuit of the illustrated bit line sense amplifier 110a.

[0110] Referring to Figure 11 , the bit line sense amplifier 110a may sequentially include the following steps: performing a precharge operation (S110) in response to an equalization signal PEQ, an offset cancellation signal P1, an isolation signal P2, and a first control signal LA and a second control signal LAB, performing an offset cancellation operation (S120), performing a charge sharing operation (S130), performing a pre-read operation (S140), and performing a restore operation (S150). For ease of description, reference will be made to Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E to describe Figure 11 the operations in

[0111] Referring to Figure 12A , in Figure 11 the operation S110, the bit line sense amplifier 110a may perform a precharge operation (S110). The bit line sense amplifier 110a may precharge the bit line BL, the complementary bit line BLB, the sense bit line SBL, and the complementary sense bit line SBLB to a precharge voltage VBL. For example, the equalization signal PEQ, the offset cancellation signal P1, and the isolation signal P2 may have a logic high level (e.g., HIGH as shown in Figure 13B ).

[0112] First, in response to an equalization signal PEQ having a logic high level (e.g., HIGH), a precharge voltage VBL may be provided to a sense bit line SBL. Then, a first offset cancellation transistor OC1 and a second offset cancellation transistor OC2 may be turned on in response to an offset cancellation signal P1 having a logic high level, and a first isolation transistor ISO1 and a second isolation transistor ISO2 may be turned on in response to an isolation signal P2 having a logic high level (e.g., HIGH). Accordingly, a bit line BL, a complementary bit line BLB, a sense bit line SBL, and a complementary sense bit line SBLB may be connected to a node and may be charged to the precharge voltage VBL. In this case, a first control signal LA and a second control signal LAB may be charged to the precharge voltage VBL. Accordingly, in this case, the bit line BL, the complementary bit line BLB, the sense bit line SBL, the complementary sense bit line SBLB, and the first control signal LA and the second control signal LAB may be equally charged to the precharge voltage VBL.

[0113] Reference Figure 12B , in Figure 11 operation S120 of, a bit line sense amplifier 110a may perform an offset cancellation operation. For example, the isolation signal P2 may have a logic low level (e.g., LOW as shown in Figure 13B ), and the offset cancellation signal P1 may have a logic high level (e.g., HIGH as shown in Figure 13B ).

[0114] The first isolation transistor ISO1 and the second isolation transistor ISO2 may be turned off in response to the isolation signal P2 having a logic low level, and the first offset cancellation transistor OC1 and the second offset cancellation transistor OC2 may be turned on in response to the offset cancellation signal P1 having a logic high level. In this case, the first control signal LA may transition from the precharge voltage VBL to an internal power supply voltage VINTA, and the second control signal LAB may transition from the precharge voltage VBL to a ground voltage VSS. The internal power supply voltage VINTA may be a voltage supplied to a memory cell array (e.g., the memory cell array 300 in Figure 14 ). Thereafter, the first control signal LA may transition from the internal power supply voltage VINTA to the precharge voltage VBL, and the second control signal LAB may transition from the ground voltage VSS to the precharge voltage VBL.

[0115] In the bit line sense amplifier 110a, for example, due to variations in manufacturing processes, temperature, etc., the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 may have different threshold voltages (e.g., Vth) from each other. In this case, the bit line sense amplifier 110a may cause offset noise due to the difference in the threshold voltages of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2.

[0116] In some example embodiments, the offset of the bit line sense amplifier 110b may be compensated based on an offset cancellation operation, and the first to fourth examples (e.g., cases I to IV) in the reference Figure 13A are described herein.

[0117] In Figure 13A the first example (e.g., case I), it is assumed that the threshold voltage of the first NMOS transistor MN1 is greater than the threshold voltage of the second NMOS transistor MN2. In this case, the first NMOS transistor MN1 and the second NMOS transistor MN2 may operate as diodes. The amount of current flowing through the first NMOS transistor MN1 may be less than the amount of current flowing through the second NMOS transistor MN2. Additionally, the amount of current flowing through the first PMOS transistor MP1 may be less than the amount of current flowing through the second PMOS transistor MP2. Therefore, as Figure 13A illustrated, the voltage of the complementary bit line BLB may increase to a predetermined level greater than the voltage of the bit line BL.

[0118] In Figure 13A the second example (e.g., case II), it is assumed that the threshold voltage of the second NMOS transistor MN2 is greater than the threshold voltage of the first NMOS transistor MN1. In this case, the first NMOS transistor MN1 and the second NMOS transistor MN2 may operate as diodes. The amount of current flowing through the second NMOS transistor MN2 may be less than the amount of current flowing through the first NMOS transistor MN1. Additionally, the amount of current flowing through the second PMOS transistor MP2 may be less than the amount of current flowing through the first PMOS transistor MP1. Therefore, as Figure 13A illustrated, the voltage of the complementary bit line BLB may decrease to a predetermined level less than the voltage of the bit line BL.

[0119] In Figure 13AIn a third example (e.g., Case III), it is assumed that the threshold voltage of the first PMOS transistor MP1 is greater than the threshold voltage of the second PMOS transistor MP2. The amount of current flowing through the first PMOS transistor MP1 can be less than the amount of current flowing through the second PMOS transistor MP2. The first NMOS transistor MN1 and the second NMOS transistor MN2 can flow a predetermined amount of current as diodes. Thus, as Figure 13A illustrated, the voltage of the complementary bit line BLB can increase to a predetermined level greater than the voltage of the bit line BL.

[0120] In Figure 13A a fourth example (e.g., Case IV), it is assumed that the threshold voltage of the second PMOS transistor MP2 is greater than the threshold voltage of the first PMOS transistor MP1. The amount of current flowing through the second PMOS transistor MP2 can be less than the amount of current flowing through the first PMOS transistor MP1. The first NMOS transistor MN1 and the second NMOS transistor MN2 can flow a predetermined amount of current as diodes. Thus, as Figure 13A illustrated, the voltage of the complementary bit line BLB can decrease to a predetermined level less than the voltage of the bit line BL.

[0121] In the above first to fourth examples (e.g., Case I to IV), compared with the voltage of the bit line BL, the voltage of the complementary bit line BLB can increase or decrease to a predetermined level, and thus the bit line BL and the complementary bit line BLB can have a predetermined voltage difference. This voltage difference can be interpreted as an offset voltage due to offset noise. This means that the offset noise of the bit line sense amplifier 110a can be eliminated by making the bit line BL and the complementary bit line BLB have a voltage difference by virtue of the offset voltage. In other words, the bit line sense amplifier 110a can compensate for the offset through an offset cancellation operation.

[0122] Referring to Figure 12C , in Figure 11 operation S130, the bit line sense amplifier 110a can perform a charge sharing operation. For example, the offset cancellation signal P1 and the isolation signal P2 can have a logic low level (e.g., LOW as Figure 13B illustrated).

[0123] The first offset cancellation transistor OC1 and the second offset cancellation transistor OC2 and the first isolation transistor ISO1 and the second isolation transistor ISO2 can be turned off in response to the offset cancellation signal P1 and the isolation signal P2 having a logic low level (e.g., LOW as Figure 13B illustrated). In this case, the word line WLi connected to the storage cell (e.g., the storage cell MC1 in Figure 3 ) can be activated, and the unit capacitor stored in the storage cell (e.g., Figure 3A charge sharing operation is performed between the charge in the unit capacitor CC1) and the charge stored in the bit line BL. In this case, the first control signal LA and the second control signal LAB may have a precharge voltage VBL.

[0124] For example, when data with a value of '1' is stored in the memory cell, the voltage of the bit line BL may increase by a predetermined level during the charge sharing operation. On the other hand, when data with a value of '0' is stored in the memory cell, the voltage of the bit line BL may decrease by a predetermined level during the charge sharing operation.

[0125] Reference Figure 12D , in Figure 11 operation S140, the bit line sense amplifier 110a may perform a pre-sensing operation. For example, the offset cancellation signal P1 and the isolation signal P2 may have a logic low level (e.g., LOW as shown in Figure 13B ).

[0126] When Figure 12C the charge sharing operation described in is performed, the voltage of the bit line BL may increase or decrease by a predetermined level (e.g., ΔV) according to the data stored in the memory cell. In this case, the first control signal LA may transition from the precharge voltage VBL to the internal power supply voltage VINTA, and the second control signal LAB may transition from the precharge voltage VBL to the ground voltage VSS. Therefore, the bit line sense amplifier 110a may charge the voltages of the sense bit line SBL and the complementary sense bit line SBLB to the internal power supply voltage VINTA, and may discharge the voltages of the sense bit line SBL and the complementary sense bit line SBLB to the ground voltage VSS based on the voltage difference between the bit line BL and the complementary bit line BLB.

[0127] For example, when data with a value of '1' is stored in the memory cell, during the pre-sensing operation, the voltage of the sense bit line SBL may increase to the internal power supply voltage VINTA, and the voltage of the complementary sense bit line SBLB may decrease to the ground voltage VSS. On the other hand, when data with a value of '0' is stored in the memory cell, the voltage of the sense bit line SBL may decrease to the ground voltage VSS, and the voltage of the complementary sense bit line SBLB may increase to the internal power supply voltage VINTA.

[0128] For example, during the pre-sensing operation, the bit line BL and the complementary bit line BLB, and the sense bit line SBL and the complementary sense bit line SBLB may be disconnected from each other through the first isolation transistor ISO1 and the second isolation transistor ISO2, and the first offset cancellation transistor OC1 and the second offset cancellation transistor OC2. When the bit line sense amplifier 110a is separated from the bit line BL and the complementary bit line BLB, the coupling effect between the bit lines BL can be reduced and the readout rate can be improved.

[0129] Reference Figure 12E , in Figure 11 operation S150, the bit line sense amplifier 110a can perform a restoration operation. For example, the offset cancellation signal P1 can have a logic low level (e.g., LOW as shown in Figure 13B ), and the isolation signal P2 can have a logic high level (e.g., HIGH as shown in Figure 13B ).

[0130] The first isolation transistor ISO1 and the second isolation transistor ISO2 can be turned on in response to the isolation signal P2 having a logic high level (e.g., HIGH as shown in Figure 13B ), and the first offset cancellation transistor OC1 and the second offset cancellation transistor OC2 can be turned off in response to the offset cancellation signal P1 having a logic low level (e.g., LOW as shown in Figure 13B ). In this case, the bit line BL and the complementary sense bit line SBLB can be connected through the first isolation transistor ISO1, and the complementary bit line BLB and the sense bit line SBL can be connected through the second isolation transistor ISO2. Therefore, the voltage of the bit line BL can be increased or decreased to the voltage level of the complementary sense bit line SBLB, and the voltage of the complementary bit line BLB can be increased or decreased to the voltage level of the sense bit line SBL.

[0131] In some example embodiments, after the pre-sensing operation, the sense bit line pair SBL and SBLB of the bit line sense amplifier 110a can be connected to the data line, and data can be output to the local sense amplifier, the global sense amplifier, and / or the data I / O buffer (e.g., the data I / O buffer 295 in Figure 14 ).

[0132] As described above, the bit line sense amplifier 110a can compensate for the offset of the bit line sense amplifier 110a through the offset cancellation operation, can minimize the coupling between the bit lines BL through the pre-sensing operation, and thus can improve its effective sensing margin.

[0133] Reference Figure 13B , the bit line sense amplifier 110a can perform a pre-charge operation (S110), an offset cancellation operation (S120), a charge sharing operation (S130), a pre-sensing operation (S140), and a restoration operation (S150) based on the equalization signal PEQ, the offset cancellation signal P1, the isolation signal P2, and the first control signal LA and the second control signal LAB.

[0134] In Figure 13BAmong them, the x-axis represents time and the y-axis represents the signal level (or voltage level, such as HIGH or LOW). For example, assume that the storage cell stores data with a value of '1' and the threshold voltage of the first NMOS transistor MN1 is larger than the threshold voltage of the second NMOS transistor MN2 by an offset voltage Vos.

[0135] In the first time interval from t0 to t1, the bit-line sense amplifier 110a may perform a pre-charge operation (S110). In this case, the equalization signal PEQ, the offset cancellation signal P1, and the isolation signal P2 may have a logic high level (e.g., HIGH), and the bit-line pair BL and BLB and the sense bit-line pair SBL and SBLB may be pre-charged to the pre-charge voltage VBL. In addition, the first control signal LA and the second control signal LAB may be pre-charged to the pre-charge voltage VBL.

[0136] In the second time interval from t1 to t2, the bit-line sense amplifier 110a may perform an offset cancellation operation (S120). In this case, the isolation signal P2 may have a logic low level (e.g., LOW). The first control signal LA may increase from the pre-charge voltage VBL to the internal power supply voltage VINTA, and the second control signal LAB may decrease from the pre-charge voltage VBL to the ground voltage VSS. The bit-line sense amplifier 110a may perform the above offset cancellation operation. Since the threshold voltage of the first NMOS transistor MN1 is larger than the threshold voltage of the second NMOS transistor MN2 by the offset voltage Vos, during the offset cancellation operation, the voltage of the complementary bit-line BLB may be larger than the voltage of the bit-line BL by the offset voltage Vos. Therefore, the voltages of the bit-line BL and the complementary bit-line BLB may have a certain difference by the offset voltage Vos, and thus the offset noise of the bit-line sense amplifier 110a may be eliminated.

[0137] In the third time interval from t2 to t3, the bit-line sense amplifier 110a may perform a charge sharing operation (S130). In this case, the offset cancellation signal P1 and the isolation signal ISO may have a logic low level (e.g., LOW), the word line (e.g., word line WLi) connected to the storage cell may be activated, and a charge sharing operation may be performed between the charge stored in the cell capacitor of the storage cell and the charge stored in the bit line. Since data with a value of '1' is stored in the storage cell, the voltage level of the bit-line BL may increase by a predetermined level during the charge sharing operation.

[0138] In the fourth time interval from t3 to t4, the bit line sense amplifier 110a may perform a pre-sensing operation (S140). In this case, the first control signal LA may transition from the pre-charge voltage VBL to the internal power supply voltage VINTA, and the second control signal LAB may transition from the pre-charge voltage VBL to the ground voltage VSS. Accordingly, in the bit line sense amplifier 110a, based on the voltage difference between the bit line BL and the complementary bit line BLB, the voltage of the sense bit line SBL may increase to the internal power supply voltage VINTA, and the voltage of the complementary sense bit line SBLB may decrease to the ground voltage VSS.

[0139] In the fifth time interval from t4 to t5, the bit line sense amplifier 110a may perform a restore operation (S150). In this case, the isolation signal P2 may have a logic high level (e.g., HIGH), and the offset cancellation signal P1 may remain at a logic low level (e.g., LOW), and the first isolation transistor ISO1 and the second isolation transistor ISO2 may be turned on. The bit line pair BL and BLB and the sense bit line pair SBL and SBLB may be connected to each other, respectively, and the bit line pair BL and BLB may be charged or discharged to the voltage level of the sense bit line pair SBL and SBLB.

[0140] Figure 14 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0141] Reference Figure 14 , the semiconductor memory device 200 may include a memory cell array 300, a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer (RA MUX) 240, a refresh counter 245, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a sense amplifier circuit (or unit) 285, an input / output (I / O) gating circuit 290, and a data I / O buffer 295. For example, the semiconductor memory device 200 may be one of various volatile memory devices such as a dynamic random access memory (DRAM). In another example, the semiconductor memory device 200 may be any volatile memory device and / or any non-volatile memory device, e.g., a static random access memory (SRAM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.

[0142] The memory cell array 300 may include a first bank array 310 to an eighth bank array 380 (e.g., first to eighth bank arrays 310, 320, 330, 340, 350, 360, 370, and 380). The row decoder 260 may include a first bank row decoder 260a to an eighth bank row decoder 260h respectively connected to the first bank array 310 to the eighth bank array 380. In this case, the first bank row decoder 260a may be connected to the first bank array 310, and the eighth bank row decoder 260h may be connected to the eighth bank array 380. The column decoder 270 may include a first bank column decoder 270a to an eighth bank column decoder 270h respectively connected to the first bank array 310 to the eighth bank array 380. In this case, the first bank column decoder 270a may be connected to the first bank array 310, and the eighth bank column decoder 270h may be connected to the eighth bank array 380. The sense amplifier circuit 285 may include a first bank sense amplifier 285a to an eighth bank sense amplifier 285h respectively connected to the first bank array 310 to the eighth bank array 380. In this case, the first bank sense amplifier 285a may be connected to the first bank array 310, and the eighth bank sense amplifier 285h may be connected to the eighth bank array 380.

[0143] The first bank array 310 to the eighth bank array 380, the first bank row decoder 260a to the eighth bank row decoder 260h, the first bank column decoder 270a to the eighth bank column decoder 270h, and the first bank sense amplifier 285a to the eighth bank sense amplifier 285h may form the first bank to the eighth bank respectively. Each of the first bank array 310 to the eighth bank array 380 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC intersecting the word lines WL and the bit lines BL.

[0144] Although Figure 14 FIG. illustrates the semiconductor memory device 200 including eight banks (and eight bank arrays, eight row decoders, etc.), but the semiconductor memory device 200 may include any number of banks. In another example, the number of banks may be less than eight or greater than eight. For example, the number of banks may be one, two, four, eight, sixteen, or thirty-two, or any number between one and thirty-two.

[0145] The address register 220 may receive from a memory controller (e.g., Figure 16The memory controller 520 therein) receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0146] The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. One of the first bank row decoders 260a to the eighth bank row decoders 260h corresponding to the bank address BANK_ADDR and one of the first bank column decoders 270a to the eighth bank column decoders 270h may be activated in response to the bank control signals.

[0147] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be respectively applied to the first bank row decoders 260a to the eighth bank row decoders 260h.

[0148] One of the activated first bank row decoders 260a to the eighth bank row decoders 260h may decode the row address RA generated from the row address multiplexer 240, and may activate a word line WL corresponding to the row address RA in the corresponding bank array. For example, the activated bank row decoder may generate a word line drive voltage and may apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0149] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch 250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first bank column decoders 270a to the eighth bank column decoders 270h, respectively.

[0150] One of the activated first to eighth bank column decoders 270a to 270h may decode the column address COL_ADDR generated from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0151] The I / O gating circuit 290 may include circuitry configured to gate input / output data. The I / O gating circuit 290 may further include a read data latch configured to store data generated from the first to eighth bank arrays 310 to 380, and may also include write control devices for writing data into the first to eighth bank arrays 310 to 380, respectively.

[0152] Data DAT read from one of the first to eighth bank arrays 310 to 380 may be read out by a sense amplifier connected to a bank array from which the data DAT is read and may be stored in the read data latch. The data DAT stored in the read data latch may be provided to the memory controller via the data I / O buffer 295. Data DAT to be written in one of the first to eighth bank arrays 310 to 380 may be provided from the memory controller to the I / O gating circuit 290 via the data I / O buffer 295, and the I / O gating circuit 290 may write the data DAT into a bank array through a write driver.

[0153] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate control signals for the semiconductor memory device 200 to perform a write operation and / or a read operation. The control logic circuit 210 may include a command decoder 211 and a mode register 212. In this case, the command decoder 211 may decode the command CMD received from the memory controller, and the mode register 212 may set the operation mode of the semiconductor memory device 200. In some example embodiments, the operations described herein as being performed by the control logic circuit 210 may be performed by a processing circuitry. For example, the command decoder 211 may generate control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, and a chip select signal.

[0154] The sense amplifier circuit 285 may be a sense amplifier circuit according to an example embodiment and may include a plurality of bit line sense amplifiers having a split structure in which some sources and / or some active regions of the equalization transistors are separated. Accordingly, defects in the sense amplifier circuit 285 may be prevented and the size of the sense amplifier circuit 285 may be reduced.

[0155] Figure 15 is a diagram showing Figure 14 an example of a memory cell array included in a semiconductor memory device.

[0156] Referring to Figure 14 and Figure 15 , the first bank array 310 included in the memory cell array 300 may include a plurality of word lines WL1, WL2, …, WLm-1, WLm (where m is a positive integer greater than or equal to 2), a plurality of bit lines BL1, BL2, …, BLn-1, BLn (where n is a positive integer greater than or equal to 2 that may be the same as or different from m) that cross the plurality of word lines WL1, WL2, …, WLm-1, WLm, and a plurality of memory cells MC disposed at or near the intersections of the word lines WL1 to WLm and the bit lines BL1 to BLn. For example, each of the plurality of memory cells MC may include a DRAM cell structure. The plurality of word lines WL1 to WLm to which the plurality of memory cells MC are connected may be referred to as rows of the first bank array 310, and the plurality of bit lines BL1 to BLn to which the plurality of memory cells MC are connected may be referred to as columns of the first bank array 310. In this case, each of the plurality of memory cells MC may be connected to one of the plurality of word lines WL1 to WLm and one of the plurality of bit lines BL1 to BLn.

[0157] Although the semiconductor memory device according to the exemplary embodiment has been described based on DRAM, the semiconductor memory device according to the exemplary embodiment may be any volatile memory device and / or any non-volatile memory device, such as, for example, static random access memory (SRAM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0158] Figure 16 is a block diagram showing a memory system according to an exemplary embodiment.

[0159] Referring to Figure 16 , the memory system 510 includes a memory controller 520 and a semiconductor memory device 540. The memory system 510 may further include a plurality of signal lines 530 that electrically connect the memory controller 520 to the semiconductor memory device 540.

[0160] The semiconductor memory device 540 is controlled by the memory controller 520. For example, based on a request from a host (not shown), the memory controller 520 may store (e.g., write or program) data into the semiconductor memory device 540, or may retrieve (e.g., read or read out) data from the semiconductor memory device 540.

[0161] The semiconductor memory device 540 may include a sense amplifier circuit 550. The sense amplifier circuit 550 may be a sense amplifier circuit according to an exemplary embodiment and may include a plurality of bit line sense amplifiers having a separated structure in which some sources and / or some active regions of equalizing transistors are separated. Accordingly, defects in the sense amplifier circuit 550 may be prevented and the size of the sense amplifier circuit 550 may be reduced.

[0162] The plurality of signal lines 530 may include a control line for transmitting a control signal CTRL, a command line for transmitting a command CMD, an address line for transmitting an address ADDR, a data input / output (I / O) line, and a power line for transmitting a power supply voltage PWR. In this case, the memory controller 520 may transmit the command CMD, the address ADDR, and the control signal CTRL to the semiconductor memory device 540 via the command line, the address line, and the control line, may exchange data DAT with the semiconductor memory device 540 via the data I / O line, and may transmit the power supply voltage PWR to the semiconductor memory device 540 via the power line. Although not illustrated in Figure 16 , the plurality of signal lines 530 may further include a data strobe signal (DQS) line for transmitting a DQS signal.

[0163] Figure 17 is a block diagram illustrating an example of a memory module that may be used in a memory system according to an exemplary embodiment.

[0164] Referring to Figure 17 , the memory module 800 may include a buffer chip 890 (e.g., a register clock driver; RCD) mounted on a circuit board 801, a plurality of semiconductor memory devices 851a, 851b, 851c, 851d, 851e, 852a, 852b, 852c, 852d, 852e, 853a, 853b, 853c, 853d, 854a, 854b, 854c, and 854d, module resistor units 860 and 870, a serial presence detect (SPD) chip 880, and / or a power management integrated circuit (PMIC) 885.

[0165] The buffer chip 890 may be connected to the semiconductor memory devices 851a, 851b, 851c, 851d, 851e, 852a, 852b, 852c, 852d, 852e, 853a, 853b, 853c, 853d, 854a, 854b, 854c, and 854d through a memory controller (e.g., Figure 16The memory controller 520) controls the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d and the PMIC 885. For example, the buffer chip 890 may receive a command CMD, an address ADDR, and data DAT from the memory controller to control the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d and the PMIC 885.

[0166] The SPD chip 880 may be a programmable read-only memory (PROM) (e.g., an electrically erasable PROM (EEPROM)). The SPD chip 880 may include initial information and / or device information DI of the memory module 800. In some example embodiments, the SPD chip 880 may include initial information and / or device information DI of the memory module 800, such as module form, module configuration, storage capacity, module type, operating environment, etc.

[0167] When the memory system including the memory module 800 is powered on, the memory controller may read the device information DI from the SPD chip 880 and may identify the memory module 800 based on the device information DI. The memory controller may control the memory module 800 based on the device information DI from the SPD chip 880. For example, the memory controller may identify the types of the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d included in the memory module 800 based on the device information DI from the SPD chip 880.

[0168] Here, the circuit board 801, which is a printed circuit board (PCB), may extend in a second direction D2 perpendicular to the first direction D1. The circuit board 801 may include a first edge portion 803 and a second edge portion 805. The first edge portion 803 and the second edge portion 805 may extend in the first direction D1. The buffer chip 890 may be disposed at the center of the circuit board 801. However, in another example, the buffer chip 890 may be disposed on any part of the circuit board 801. The plurality of semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d may be arranged in a plurality of rows between the buffer chip 890 and the first edge portion 803 and between the buffer chip 890 and the second edge portion 805. In some example embodiments, the operations described herein as being performed by the buffer chip 890 may be performed by a processing circuitry.

[0169] In this example, semiconductor memory devices 851a to 851e and 852a to 852e can be arranged along multiple rows between buffer chip 890 and the first edge portion 803. Semiconductor memory devices 853a to 853d and 854a to 854d can be arranged along multiple rows between buffer chip 890 and the second edge portion 805. In this case, multiple semiconductor memory devices 851a to 851e and 852a to 852e can be provided between the first edge portion 803 and buffer chip 890. Additionally, multiple semiconductor memory devices 853a to 853d and 854a to 854d can be provided between the second edge portion 805 and buffer chip 890. For example, semiconductor memory devices 851a to 851d, 852a to 852d, 853a to 853d, and 854a to 854d can be data chips that store normal data, and semiconductor memory devices 851e and 852e can be parity chips that store parity data or error correction code (ECC) data.

[0170] Buffer chip 890 can provide command / address signals (e.g., CA) to semiconductor memory devices 851a to 851e via command / address transmission lines 861, and can provide command / address signals to semiconductor memory devices 852a to 852e via command / address transmission lines 863. Additionally, buffer chip 890 can provide command / address signals to semiconductor memory devices 853a to 853d via command / address transmission lines 871, and can provide command / address signals to semiconductor memory devices 854a to 854d via command / address transmission lines 873.

[0171] Command / address transmission lines 861 and 863 can be commonly connected to module resistor unit 860 that is set adjacent to the first edge portion 803, and command / address transmission lines 871 and 873 can be commonly connected to module resistor unit 870 that is set adjacent to the second edge portion 805. In this case, one end of command / address transmission lines 861 and 863 can be connected to buffer chip 890, and the other end of command / address transmission lines 861 and 863 can be connected to module resistor unit 860. Similarly, one end of command / address transmission lines 871 and 873 can be connected to buffer chip 890, and the other end of command / address transmission lines 871 and 873 can be connected to module resistor unit 870. Each of module resistor units 860 and 870 can include a termination resistor Rtt / 2 connected to termination voltage Vtt.

[0172] The SPD chip 880 can be set adjacent to the buffer chip 890, and the PMIC 885 can be disposed between the semiconductor memory device 853d and the second edge portion 805. In another example, the PMIC 885 can be disposed on any part of the circuit board 801. The PMIC 885 can generate the power supply voltage VDD based on the input voltage VIN from an external source, and can supply the power supply voltage VDD to the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d.

[0173] In some example embodiments, each of the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d can be a DRAM device, and can include a sense amplifier circuit according to the example embodiments.

[0174] Figure 18 is a block diagram illustrating an electronic system including a memory module according to an example embodiment.

[0175] Reference Figure 18 , the electronic system 900 includes an application processor (AP) 910, a connection module 920, a user interface 930, a non-volatile storage device (NVM) 940, a memory module (MM) 950, and / or a power supply 970. In this case, the memory module (MM) 950 can include a dual in-line memory module (DIMM). For example, the electronic system 900 can be a mobile system.

[0176] The application processor 910 can include a memory controller 911. The application processor 910 can run an application such as at least one of a web browser, a game application, a video player, etc. The connection module 920 can perform wired communication and / or wireless communication with an external device.

[0177] The memory module 950 can store data processed by the application processor 910 and / or operate as a working memory. The memory module 950 can include a plurality of semiconductor memory devices (MD) 951, 952, 953,..., 95q (where q is a positive integer greater than 3) and / or a buffer chip (RCD) 961. The memory module 950 can be Figure 17 the memory module 800 of.

[0178] In some example embodiments, each of the semiconductor memory devices 951 to 95q can be a DRAM device, and can include a sense amplifier circuit according to the example embodiments.

[0179] The non-volatile storage device 940 can store a boot image for booting the electronic system 900. The user interface 930 can include at least one input device (such as a keypad, a touch screen, a stylus) and at least one output device (such as a speaker, a display device, etc.). The power supply 970 can supply an operating voltage to the electronic system 900.

[0180] The electronic system 900 or components of the electronic system 900 can be mounted using various types of packages.

[0181] The example embodiments can be applicable to various electronic devices and systems including semiconductor storage devices. For example, the example embodiments can be applicable to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, etc.

[0182] The example embodiments have been described above and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the example embodiments without substantially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it should be understood that the various example embodiments have been described above and are not to be understood as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A sense amplifier circuit, the sense amplifier circuit comprising a plurality of bit line sense amplifiers, in, Each of the plurality of bit line sense amplifiers comprises: an amplifier circuit electrically connected to the bit line and the complementary bit line, configured to sense a voltage difference between the bit line and the complementary bit line and adjust voltages of the sense bit line and the complementary sense bit line based on the voltage difference; an isolation circuit configured to electrically connect the bit line and the complementary bit line to the complementary sense bit line and the sense bit line, respectively; an offset cancellation circuit configured to electrically connect the bit line and the complementary bit line to the sense bit line and the complementary sense bit line, respectively; and an equalizer circuit configured to equalize the bit line and the complementary bit line to a precharge voltage, The equalizer circuit includes an equalizer transistor having a source, a drain, and a gate configured to receive an equalizer signal, and The active region is formed such that sources of the equalizing transistors of the first and second bit line sense amplifiers are connected to each other, and sources of the equalizing transistors of the first and third bit line sense amplifiers are separated from each other.

2. The sense amplifier circuit according to claim 1, in, The plurality of bit line sense amplifiers include a first group of bit line sense amplifiers and a second group of bit line sense amplifiers, wherein the sources of the first equalizing transistors included in the first group of bit line sense amplifiers are connected to each other, wherein the sources of the second equalizing transistors included in the second group of bit line sense amplifiers are connected to each other, and The source of the first equalizing transistor and the source of the second equalizing transistor are separated from each other.

3. The sense amplifier circuit according to claim 2, wherein: The first group of bit line sense amplifiers includes the first bit line sense amplifier and the second bit line sense amplifier disposed adjacent to each other.

4. The sense amplifier circuit according to claim 3, wherein: The first group of bit line sense amplifiers further includes a fourth bit line sense amplifier and a fifth bit line sense amplifier disposed adjacent to each other, and The fourth bit line sense amplifier and the fifth bit line sense amplifier are spaced apart from the first bit line sense amplifier and the second bit line sense amplifier.

5. The sense amplifier circuit according to claim 2, further comprising: a first active region, the first active region corresponding to the source of the first equalization transistor; a first direct contact, the first direct contact being disposed on the first active region; a first bit line metal pattern, the first bit line metal pattern being disposed on the first direct contact; a second direct contact disposed on the first bit line metal pattern; as well as A second bit line metal pattern is disposed on the second direct contact.

6. The sense amplifier circuit according to claim 5, in, The precharge voltage is provided to the first active region through the first and second direct contacts and the first and second bit line metal patterns.

7. The sense amplifier circuit according to claim 5, further comprising: a second active region, the second active region corresponding to a source of the second equalization transistor; a third direct contact, the third direct contact being disposed on the second active region; a third bit line metal pattern disposed on the third direct contact; as well as A fourth direct contact is disposed on the third bit line metal pattern, wherein the second bit line metal pattern extends to be disposed on the fourth direct contact.

8. The sense amplifier circuit according to claim 7, further comprising: An active cutting region is provided, and the active cutting region is located between the first active region and the second active region.

9. The sense amplifier circuit according to claim 7, in, The precharge voltage is supplied to the second active region through the third and fourth direct contacts and the second and third bit line metal patterns.

10. The sense amplifier circuit according to claim 5, further comprising: a conductive pattern configured to transmit the precharge voltage, and Wherein, the first direct contact is connected to the first active region by penetrating the conductive pattern.

11. The sense amplifier circuit according to claim 1, wherein: The equalizer circuit is connected between the precharge voltage and the complementary sense bit line.

12. The sense amplifier circuit according to claim 1, wherein: The equalizer circuit is connected between the precharge voltage and the read bit line.

13. The sense amplifier circuit according to claim 1, wherein: The amplifying circuit comprises: a first p-type metal oxide semiconductor transistor connected between a control line and the read bit line and including a gate connected to the complementary read bit line; a second p-type metal oxide semiconductor transistor connected between the control line and the complementary read bit line and including a gate connected to the read bit line; a first n-type metal oxide semiconductor transistor connected between a complementary control line and the readout bit line and including a gate connected to the bit line; and A second n-type metal oxide semiconductor transistor is connected between the complementary control line and the complementary readout bit line and includes a gate connected to the complementary bit line.

14. The sense amplifier circuit according to claim 13, wherein: The isolation circuit comprises: a first isolation transistor connected between the bit line and the complementary sense bit line and including a gate configured to receive an isolation signal; and A second isolation transistor is connected between the complementary bit line and the readout bit line and includes a gate configured to receive the isolation signal.

15. The sense amplifier circuit according to claim 14, wherein: The offset cancellation circuit comprises: a first offset cancellation transistor connected between the bit line and the read bit line and including a gate configured to receive an offset cancellation signal; and A second offset cancellation transistor is connected between the complementary bit line and the complementary sense bit line and includes a gate configured to receive the offset cancellation signal.

16. The sense amplifier circuit according to claim 15, further comprising: a first active region, the first active region being disposed in the first region and being in a rectangular shape in a top view with a long side parallel to a first direction and a short side parallel to a second direction, the second direction intersecting the first direction; a second active region and a third active region, the second active region and the third active region being arranged in the first region and a second region adjacent to the first region, each of which is in a rectangular shape with a long side parallel to the second direction and a short side parallel to the first direction in the plan view, the second active region and the third active region being adjacent to the first active region and spaced apart from each other along the first direction; a fourth active region, the fourth active region being disposed in a third region adjacent to the second region and spaced apart from the second active region and the third active region along the second direction; a first gate pattern extending along the first direction on the second active region and the third active region in the first region; a second gate pattern and a third gate pattern, the second gate pattern and the third gate pattern extending along the first direction on the second active region and the third active region in the second region and spaced apart from each other along the second direction; as well as Fourth and fifth gate patterns extend along the second direction on the fourth active region in the third region and are spaced apart from each other along the first direction.

17. The sense amplifier circuit according to claim 16, in, The first active region, the second active region, the third active region, and the first gate pattern in the first region correspond to the equalization transistor, and the first gate pattern is configured to receive the equalization signal, wherein the second active region, the third active region, and the second gate pattern in the second region correspond to one of the first offset cancellation transistor and the second offset cancellation transistor, and the second gate pattern is configured to receive the offset cancellation signal, wherein the second active region, the third active region, and the third gate pattern in the second region correspond to one of the first isolation transistor and the second isolation transistor, and the third gate pattern is configured to receive the isolation signal, and The fourth active region, the fourth gate pattern, and the fifth gate pattern in the third region correspond to one of the first n-type metal oxide semiconductor transistor and the second n-type metal oxide semiconductor transistor.

18. A semiconductor memory device comprising a memory cell array and a sense amplifier circuit, The memory cell array includes a plurality of memory cells, the sense amplifier circuit includes a plurality of bit line sense amplifiers connected to the plurality of memory cells, in, Each of the plurality of bit line sense amplifiers comprises: an amplifier circuit electrically connected to the bit line and the complementary bit line, configured to sense a voltage difference between the bit line and the complementary bit line, and to adjust voltages of the sense bit line and the complementary sense bit line based on the voltage difference; an isolation circuit configured to electrically connect the bit line and the complementary bit line to the complementary sense bit line and the sense bit line, respectively; an offset cancellation circuit configured to electrically connect the bit line and the complementary bit line to the sense bit line and the complementary sense bit line, respectively; and an equalizer circuit configured to equalize the bit line and the complementary bit line to a precharge voltage, The equalizer circuit includes an equalizer transistor having a source, a drain, and a gate configured to receive an equalizer signal, and The active region is formed such that sources of the equalizing transistors of the first and second bit line sense amplifiers are connected to each other, and sources of the equalizing transistors of the first and third bit line sense amplifiers are separated from each other.

19. The semiconductor memory device according to claim 18, wherein: The semiconductor memory device is a dynamic random access memory.

20. A sense amplifier circuit, the sense amplifier circuit comprising a plurality of bit line sense amplifiers, in, Each of the plurality of bit line sense amplifiers comprises: an amplifier circuit electrically connected to the bit line and the complementary bit line, configured to sense a voltage difference between the bit line and the complementary bit line based on a first control signal and a second control signal, and to adjust voltages of the sense bit line and the complementary sense bit line based on the voltage difference; an isolation circuit configured to electrically connect the bit line and the complementary bit line to the complementary sense bit line and the sense bit line, respectively, based on an isolation signal; an offset cancellation circuit configured to electrically connect the bit line and the complementary bit line to the sense bit line and the complementary sense bit line, respectively, based on an offset cancellation signal; and an equalizer circuit electrically connected to the complementary sense bit line and configured to equalize the bit line and the complementary bit line to a precharge voltage, wherein the equalizer circuit comprises an equalizer transistor having a source configured to receive the precharge voltage, a gate configured to receive an equalization signal, and a drain electrically connected to the complementary read bit line, wherein sources of a first equilibration transistor and a second equilibration transistor included in a first bit line sense amplifier and a second bit line sense amplifier adjacent to each other are connected to each other, and first active regions corresponding to the sources of the first equilibration transistor and the second equilibration transistor are integrally formed, wherein sources of a third equilibration transistor and a fourth equilibration transistor included in a third bit line sense amplifier and a fourth bit line sense amplifier adjacent to each other and spaced apart from the first bit line sense amplifier and the second bit line sense amplifier are connected to each other, and second active regions corresponding to the sources of the third equilibration transistor and the fourth equilibration transistor are integrally formed, and The sources of the first and second equilibration transistors and the sources of the third and fourth equilibration transistors are separated from each other, and an active cut region is formed between the first active region and the second active region to separate the first active region from the second active region.

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