Calibration method and system for duty cycle correction circuit and memory

Abstract

The embodiment of the invention provides a duty ratio correction circuit calibration method and system and a memory, and the method comprises the steps: obtaining an internal clock signal outputted by a DLL circuit and a feedback clock signal outputted by a DCC circuit, and determining a duty ratio difference signal according to the internal clock signal and the feedback clock signal; acquiring first actual temperature information and first actual voltage information of the DCC circuit at the target sampling moment, and actual process corner grade information of the DRAM; determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner grade information; and adjusting the initial DCC coding signal according to the duty ratio difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal, thereby avoiding the situation that the calibration of the DCC circuit needs a lot of time to correct the duty ratio imbalance of the clock signal caused by temperature and voltage changes.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of memories and related technical fields. Specifically, the present disclosure relates to a DCC circuit calibration method, system, and memory Background Art

[0002] Dynamic Random Access Memory (DRAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It has the characteristics of random read and write at any time and high speed, and is usually used as a temporary data storage medium for the operating system or other running programs.

[0003] When the internal circuit of a dynamic random access memory uses an external clock signal as an input signal, due to the delay of the internal circuit, the internal clock signal of the dynamic random access memory is delayed. In order to make the internal clock signal of the dynamic random access memory equal to the phase of the external clock signal and determine the reliability of data transmission, a synchronization control circuit, such as a Delay-Locked Loop (DLL) circuit, is embedded in the internal circuit of the dynamic random access memory to synchronize the internal clock signal of the DRAM with the external clock signal. In order to make the high-level duty cycle and the low-level duty cycle of the internal clock signal the same, a Duty Cycle Corrector (DCC) circuit is embedded in the internal circuit of the dynamic random access memory to eliminate duty cycle distortion (such as 60% high level and 40% low level) caused by process deviation, noise, or temperature change.

[0004] In the prior art, the collaborative work of the DCC circuit and the DLL circuit is usually divided into the following stages: when the DLL circuit starts, the DCC circuit first roughly adjusts the duty cycle of the clock signal output by the DLL circuit to ensure that the initial waveform is close to 50%. Subsequently, the DLL circuit performs initial phase locking to align the rising edges of the internal clock signal of the DRAM with the external clock signal. Therefore, the DCC circuit needs to calibrate the clock signal output by the DLL circuit in a timely manner, otherwise errors are likely to accumulate, eventually leading to functional failure. When the DRAM operates at high frequency, the clock cycle is short, and ordinary digital DCC circuits can no longer meet the design requirements. Moreover, the performance of logic devices in the DCC circuit is greatly affected by PVT. Therefore, a large amount of time is required for the DCC circuit to correct the signal duty cycle imbalance caused by temperature and voltage changes during calibration. Summary of the Invention

[0005] Embodiments described herein provide a DCC circuit calibration method, system, and memory that avoid the need for the DCC to spend a large amount of time correcting signal duty cycle imbalances caused by temperature and voltage changes.

[0006] In a first aspect, according to the content of the present disclosure, a method for calibrating a DCC circuit is provided, including: Obtain an internal clock signal output by a DLL circuit and a feedback clock signal output by a DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal; Obtain first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, and actual process corner grade information of a DRAM; Determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner grade information; Adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0007] In some embodiments of the present disclosure, before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner grade information, it further includes: Determine a clock phase difference signal according to the internal clock signal and the feedback clock signal; Obtain second actual temperature information and second actual voltage information of the DLL circuit at a target sampling moment, and determine a target step control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner grade information; Determine a target DLL coding signal according to the clock phase difference signal and the target step control signal; The determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner grade information includes: Determine the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner grade information.

[0008] In some embodiments of the present disclosure, the determining the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner grade information includes: Determine a first actual temperature coding signal, a first actual voltage coding signal, and an actual process corner coding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner grade information; Determine the initial DCC coding signal according to the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal.

[0009] In some embodiments of the present disclosure, determining the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: Determining the first actual temperature encoding signal according to the temperature range where the first actual temperature information is located at the target sampling moment; Determining the first actual voltage encoding signal according to the voltage range where the first actual voltage information is located at the target sampling moment; Determining the actual process corner encoding signal according to the actual process corner level information submitted by the test module.

[0010] In some embodiments of the present disclosure, determining the initial DCC encoding signal according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal includes: Obtaining the test DCC encoding signals corresponding to the test DLL encoding signals, test temperature encoding signals, test voltage encoding signals, and test process corner encoding signals of each target bit in the test stage; Determining the initial DCC encoding signal according to the correspondence between the target bit target DLL encoding signal and the target bit test DLL encoding signal, the correspondence between the first actual temperature encoding signal and the test temperature encoding signal, the correspondence between the first actual voltage encoding signal and the test voltage encoding signal, and the correspondence between the actual process corner encoding signal and the test process corner encoding signal.

[0011] In some embodiments of the present disclosure, determining the target DLL encoding signal according to the clock phase difference signal and the target step control signal includes: Determining the number of target delay units that the adjustable delay chain needs to delay according to the clock phase difference signal and the target step control signal; Determining the target DLL encoding signal according to the number of target delay units that the adjustable delay chain needs to delay and the initial DLL encoding signal of the adjustable delay chain.

[0012] In some embodiments of the present disclosure, determining the number of target delay units that the adjustable delay chain needs to delay according to the clock phase difference signal and the target step control signal includes: Determining the number of unit delay units that the adjustable delay chain needs to delay according to the clock phase difference signal; Determining the number of target delay units that the adjustable delay chain needs to delay according to the number of unit delay units and the target step control signal.

[0013] In some embodiments of the present disclosure, obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal according to the internal clock signal and the feedback clock signal includes: Obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; Determining a duty cycle difference signal according to the duration corresponding to the high level of the internal clock signal and the duration corresponding to the high level of the feedback clock signal.

[0014] In a second aspect, according to the content of the present disclosure, a DCC circuit calibration system is provided, including: A duty cycle difference signal determination module, configured to obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal; An information acquisition module, configured to acquire the first actual temperature information and the first actual voltage information of the DCC circuit at a target sampling moment, and the actual process corner grade information of the DRAM; An initial DCC coding signal determination module, configured to determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner grade information; A target DCC coding signal determination module, configured to adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0015] In a third aspect, according to the content of the present disclosure, a memory is provided, including the DCC circuit calibration system described in the second aspect.

[0016] The DCC circuit calibration method, system, and memory provided by the embodiments of the present disclosure first obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal; then obtain the first actual temperature information and the first actual voltage information of the DCC circuit at a target sampling moment, and the actual process corner grade information of the DRAM; and determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner grade information; finally, adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, avoiding the need for a large amount of time to correct the duty cycle imbalance of the clock signal caused by temperature and voltage changes during DCC circuit calibration. Description of the Drawings

[0017] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure, where: Figure 1 is a schematic flow chart of a DCC circuit calibration method provided by an embodiment of the present disclosure; Figure 2 is a schematic circuit diagram of a circuit for determining an initial DCC coding signal provided by an embodiment of the present disclosure; Figure 3 is a schematic flow chart of another DCC circuit calibration method provided by an embodiment of the present disclosure; Figure 4 is a schematic structural diagram of a DCC circuit calibration system provided by an embodiment of the present disclosure. Detailed implementation manners

[0018] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall also fall within the scope of protection of the present disclosure.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, the statement of joining or coupling two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0020] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0021] Unless otherwise expressly indicated in the context, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural of the term is generally included. Similarly, the terms "comprising" and "including" shall be construed as inclusive rather than exclusive. Likewise, the term "including" and "or" shall be construed as inclusive, unless such construction is expressly prohibited herein. Where the term "example" is used in this specification, particularly when it follows a list of terms, the "example" is merely illustrative and explanatory and should not be considered exclusive or extensive.

[0022] Based on the problems existing in the prior art, an embodiment of the present disclosure provides a DCC circuit calibration method. Figure 1 It is a schematic flowchart of a DCC circuit calibration method provided by an embodiment of the present disclosure. As Figure 1 shown, the DCC circuit calibration method includes: S110. Obtain an internal clock signal output by a DLL circuit and a feedback clock signal output by a DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal.

[0023] In a specific implementation manner, the DCC circuit receives the internal clock signal output by the DLL circuit. After the DCC circuit receives the internal clock signal output by the DLL circuit, the DCC circuit performs phase inversion on the internal clock signal and then outputs the feedback clock signal. At this time, the duty cycle difference signal can be determined according to the internal clock signal output by the DLL circuit and the feedback clock signal output by the DLL circuit.

[0024] Specifically, obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determining the duty cycle difference signal according to the internal clock signal and the feedback clock signal includes: obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; determining the duty cycle difference signal according to the duration corresponding to the high level of the internal clock signal and the duration corresponding to the high level of the feedback clock signal.

[0025] As another specific implementable manner, the duty cycle difference signal can be determined according to the duration corresponding to the low level of the internal clock signal and the duration corresponding to the low level of the feedback clock signal.

[0026] S120. Obtain the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, and the actual process corner grade information of the DRAM.

[0027] In the prior art, a DCC encoding signal is determined based on the relationship between the duration corresponding to the same-level signal in the internal clock signal output by the DLL and the feedback clock signal output by the DCC, and the determined DCC encoding signal is applied to the DCC circuit to control the conduction state of the switch in the DCC circuit, so as to adjust the duty cycle of the clock signal acting on the DLL circuit. Due to interference from external factors such as PVT (the actual temperature information and actual voltage information of the DCC, and the actual process corner level information of the DRAM), a large amount of time is required to correct the duty cycle imbalance of the clock signal caused by changes in temperature and voltage during the calibration of the DCC circuit.

[0028] In combination with the problems existing in the prior art, in the embodiment of the present disclosure, before calibrating the DCC circuit, on the one hand, the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit are obtained, and a duty cycle difference signal is determined according to the internal clock signal and the feedback clock signal. On the other hand, by obtaining the first actual temperature information and the first actual voltage information of the DCC circuit and the actual process corner level information of the DRAM at the target sampling moment, and based on the first actual temperature information, the first actual voltage information and the actual process corner level information, an initial DCC encoding signal is determined. Then, the initial DCC encoding signal is adjusted by the duty cycle difference signal to obtain a target DCC encoding signal acting on the DCC circuit, so as to control the conduction state of the switch in the DCC circuit through the target DCC encoding signal and realize the adjustment of the duty cycle of the clock signal.

[0029] In a specific implementation manner, since the temperature information corresponding to the DCC circuit is different at different times, and affected by the voltage drop of each module in the DRAM, the voltage information corresponding to the DCC circuit is different at different times. Therefore, in order to avoid that a large amount of time is required for the DCC circuit to correct the duty cycle imbalance of the clock signal caused by changes in temperature and voltage during calibration, in the embodiment of the present disclosure, before adjusting the duty cycle of the clock signal, first, an initial DCC encoding signal is determined based on the first actual temperature information, the first actual voltage signal and the actual process corner level information, and then the initial DCC encoding signal is adjusted according to the duty cycle difference signal, so as to improve the efficiency of the DCC circuit in calibrating the duty cycle of the clock signal.

[0030] It should be noted that the actual process corner level information of the DRAM is determined based on the test of the test module during the test stage, that is, the process corner of the DRAM is affected by the manufacturing process of the DRAM. After the DRAM is manufactured, the process corner level information of the DRAM can be determined.

[0031] S140. Determine an initial DCC encoding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner level information.

[0032] In a specific embodiment, specifically, determining an initial DCC encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information; and determining the initial DCC encoding signal according to the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal.

[0033] Among them, determining the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: determining the first actual temperature encoding signal according to the temperature range in which the first actual temperature information is located at the target sampling moment; determining the first actual voltage encoding signal according to the voltage range in which the first actual voltage information is located at the target sampling moment; and determining the actual process corner encoding signal according to the actual process corner level information submitted by the test module.

[0034] Specifically, in DRAM design, the process corner level is simply divided into three levels, namely SS, TT, and FF. During the product test phase of DRAM, the test module can confirm which process corner level the DRAM chip belongs to. The process corner level of DRAM is only affected by the manufacturing process of DRAM. After DRAM is taped out, the parameters of DRAM will not change, that is, the actual process corner level of the taped-out DRAM will not change. For example, when the actual process corner level information of the DRAM submitted by the test module is SS, at this time, the actual process corner encoding signal is Code<2:0>=001; when the actual process corner level information of the DRAM submitted by the test module is TT, at this time, the actual process corner encoding signal is Code<2:0>=010; when the actual process corner level information of the DRAM submitted by the test module is FF, at this time, the actual process corner encoding signal is Code<2:0>=100.

[0035] Specifically, the temperature information is divided into the following three ranges: -40°C - 10°C, 11°C - 70°C, and 71°C - 120°C. When the first actual temperature information is in the range of -40°C - 10°C, at this time, the first actual temperature encoding signal is Code<5:3>=001; when the first actual temperature information is in the range of 11°C - 70°C, at this time, the first actual temperature encoding signal is Code<5:3>=010; when the first actual temperature information is in the range of 71°C - 120°C, at this time, the first actual temperature encoding signal is Code<5:3>=100.

[0036] Specifically, the voltage information is divided into the following three intervals: 1.08V - 1.16V, 1.17V - 1.24V, and 1.25V - 1.32V. When the first actual voltage information is in the interval of 1.08V - 1.16V, at this time, the first actual voltage coding signal is Code<8:6>=001. When the first actual voltage information is in the interval of 1.17V - 1.24V, at this time, the first actual voltage coding signal is Code<8:6>=010. When the first actual voltage information is in the interval of 1.25V - 1.32V, at this time, the first actual voltage coding signal is Code<8:6>=100.

[0037] In addition, according to the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal, the initial DCC coding signal is determined, including: obtaining the test DCC coding signals corresponding to each test temperature coding signal, test voltage coding signal, and test process corner coding signal during the test phase; determining the initial DCC coding signal according to the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process corner coding signal and the test process corner coding signal.

[0038] To determine the initial DCC coding signal corresponding to the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal, it is first necessary to obtain the test DCC coding signals corresponding to each test temperature coding signal, test voltage coding signal, and test process corner coding signal during the test phase, and then determine the initial DCC coding signal from the test DCC coding signals based on the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process corner coding signal and the test process corner coding signal.

[0039] In a specific embodiment, first, the range of the DCC coding signal is determined, and then the number of fuse groups is set according to the range of the DCC coding signal. Specifically, each group of fuse groups corresponds to an output test DCC coding signal. Exemplarily, the DCC coding signal output by the first group of fuse groups is 00010000, the DCC coding signal output by the second group of fuse groups is 00110000, the DCC coding signal output by the third group of fuse groups is 01010000, the DCC coding signal output by the fourth group of fuse groups is 01110000, the DCC coding signal output by the fifth group of fuse groups is 10010000, the DCC coding signal output by the sixth group of fuse groups is 10110000, the DCC coding signal output by the seventh group of fuse groups is 11010000, and the DCC coding signal output by the eighth group of fuse groups is 11110000. Each group of fuse groups includes 27 fuses. The first test temperature coding signal, the first test voltage coding signal, and the test process corner coding signal are arranged and combined to obtain 27 test coding signals, and the test DCC coding signals corresponding to the 27 test coding signals are respectively tested, as Figure 2 shown. After determining the test DCC coding signals corresponding to the 27 test coding signals in the test stage, during the process of adjusting the duty cycle of the clock signal through the DCC circuit, the initial DCC coding signal is determined according to the actual coding signal composed of the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal.

[0040] A specific exemplary case is as follows. If the test coding signal is TestCode<8:0>=000000000, where TestCode<2:0>=000 is the test process corner coding signal, TestCode<5:3>=000 is the first test temperature coding signal, and TestCode<8:6>=000 is the first test voltage coding signal. During the test stage, the test DCC coding signal for the test coding signal TestCode<8:0>=000000000 is determined to be 00010000. During the actual adjustment stage, if the actual coding signal composed of the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal is Code<8:0>=000000000, at this time, control the first fuse in the first group of fuse sets to blow, and output the initial DCC coding signal 00010000 through the first group of fuse sets. If the test coding signal is TestCode<8:0>=000000001, where TestCode<2:0>=001 is the test process corner coding signal, TestCode<5:3>=000 is the first test temperature coding signal, and TestCode<8:6>=000 is the first test voltage coding signal. During the test stage, the test DCC coding signal for the test coding signal TestCode<8:0>=000000001 is determined to be 00110000. During the actual adjustment stage, if the actual coding signal determined based on the first actual temperature coding signal, the first actual voltage coding signal, and the actual process corner coding signal is Code<8:0>=000000001, at this time, control the second fuse in the second group of fuse sets to blow, and output the initial DCC coding signal 00110000 through the second group of fuse sets.

[0041] S150. Adjust the initial DCC coding signal according to the duty cycle difference signal to obtain the target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0042] After determining the initial DCC coding signal and the duty cycle difference signal, adjust the DCC coding signal according to the duty cycle difference signal to determine the target DCC coding signal, so as to control the conduction states of the switches in the DCC circuit through the target DCC coding, and then change the driving ability of the inverter and the transmission line capacitance in the DCC circuit to correct the delay of the rising edge or the falling edge.

[0043] The DCC circuit calibration method provided by the embodiments of the present disclosure first obtains the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determines the duty cycle difference signal according to the internal clock signal and the feedback clock signal; then obtains the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, as well as the actual process corner grade information of the DRAM; and determines the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner grade information; finally, adjusts the initial DCC coding signal according to the duty cycle difference signal to obtain the target DCC coding signal, avoiding the need for a large amount of time to correct the duty cycle imbalance of the clock signal caused by temperature and voltage changes in DCC circuit calibration.

[0044] As a preferred implementation manner, Figure 3 is a schematic flowchart of another DCC circuit calibration method provided by the embodiments of the present disclosure. As shown in Figure 3 shown, before performing the step S140 shown in Figure 1 it also includes: S130. Determine the clock phase difference signal according to the internal clock signal and the feedback clock signal.

[0045] In a specific implementation manner, collect the internal clock signal output from the DLL circuit to the DCC circuit and the feedback clock signal after passing through the DCC circuit, and determine the clock phase difference signal between the feedback clock signal and the internal clock signal through the internal and external clock signals and the feedback clock signal, that is, determine how many unit clock cycles the feedback clock signal and the internal clock signal differ by.

[0046] S131. Obtain the second actual temperature information and the second actual voltage information of the DLL circuit at the target sampling moment, and determine the target step control signal according to the second actual temperature information, the second actual voltage information and the actual process corner grade information.

[0047] Since the duty cycle adjustment of the clock signal by the DCC circuit is performed after the DLL circuit performs the phase adjustment of the clock signal, when the number of delay units adjusted by the DLL circuit cannot be determined, the asymmetry of the rising delay and falling delay of the clock signal will occur due to the different performances of the delay units under different PVT conditions, and then the duty cycle distortion of the clock signal will occur. As a preferred implementation manner, determining the initial DCC coding signal based on the target DLL coding signal acting on the DLL circuit, the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, and the actual process corner grade information of the DRAM can ensure the effectiveness of the determined initial DCC coding signal.

[0048] In the specific implementation process of determining the target DLL coding signal acting on the DLL circuit, first, it is necessary to determine the clock phase difference signal based on the internal clock signal and the feedback clock signal, and obtain the second actual temperature information and the second actual voltage information of the DLL circuit at the target sampling moment, and determine the target step control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information.

[0049] It should be noted that in the above embodiments, the specific process of determining the target step control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information is the same as the method of determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information, and no further examples will be given here.

[0050] S132. Determine the target DLL coding signal according to the clock phase difference signal and the target step control signal.

[0051] In a specific implementation manner, determining the target DLL coding signal according to the clock phase difference signal and the target step control signal includes: determining the number of target delay units that the adjustable delay chain needs to delay according to the clock phase difference signal and the target step control signal; determining the target DLL coding signal according to the number of target delay units that the adjustable delay chain needs to delay and the initial DLL coding signal of the adjustable delay chain.

[0052] A specific example is that if the clock phase difference signal between the internal clock signal and the feedback clock signal is 4 unit clock cycles, then the number of unit delay units that the adjustable delay chain needs to delay is determined to be 4. After determining the number of unit delay units that the adjustable delay chain needs to delay, according to the target step control signal and the number of target delay units that the adjustable delay chain needs to delay, the number of target delay units that the adjustable delay chain needs to delay can be determined. Finally, according to the number of target delay units that the adjustable delay chain needs to delay and the initial DLL coding signal of the adjustable delay chain, the target DLL coding signal is determined.

[0053] At this time Figure 1 The implementation manner of step S140 is as follows: S1401. Determine the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner level information.

[0054] In a specific implementation manner, an initial DCC encoding signal is determined based on a target DLL encoding signal, first actual temperature information, a first actual voltage signal, and actual process corner level information, including: determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information; and determining the initial DCC encoding signal according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal.

[0055] Among them, determining the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: determining the first actual temperature encoding signal according to the temperature range where the first actual temperature information is located at the target sampling moment; determining the first actual voltage encoding signal according to the voltage range where the first actual voltage information is located at the target sampling moment; and determining the actual process corner encoding signal according to the actual process corner level information submitted by the test module.

[0056] Determining the initial DCC encoding signal according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal includes: obtaining the test DCC encoding signals corresponding to the test DLL encoding signals, test temperature encoding signals, test voltage encoding signals, and test process corner encoding signals of each target bit in the test stage; and determining the initial DCC encoding signal according to the correspondence between the target DLL encoding signal of the target bit and the test DLL encoding signal of the target bit, the correspondence between the first actual temperature encoding signal and the test temperature encoding signal, the correspondence between the first actual voltage encoding signal and the test voltage encoding signal, and the correspondence between the actual process corner encoding signal and the test process corner encoding signal.

[0057] In the process of determining the initial DCC encoding signal based on the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal of the DRAM, since the DLL encoding signal is at least 8 bits, at this time, the number of bits of the actual encoding signal composed of the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal of the DRAM is at least 18 bits. At this time, the number of fuses included in each fuse group is 256. Since the fuse group cannot accommodate a relatively large number of fuses, therefore, by selecting the encoding signal of the highest three bits of the target DLL encoding signal (the highest three bits of the target DLL encoding signal are the target bits of the target DLL encoding signal) and the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal of the DRAM to form the actual encoding signal, and determining the initial DCC encoding signal according to this actual encoding signal.

[0058] It should be noted that according to the correspondence between the target DLL encoding signal and the target bit test DLL encoding signal, the correspondence between the first actual temperature encoding signal and the test temperature encoding signal, the correspondence between the first actual voltage encoding signal and the test voltage encoding signal, and the correspondence between the actual process corner encoding signal and the test process corner encoding signal, the specific process of determining the initial DCC encoding signal is the same as the process of determining the initial DCC encoding signal according to the correspondence between the first actual temperature encoding signal and the test temperature encoding signal, the correspondence with the test voltage encoding signal, and the correspondence between the actual process corner encoding signal and the test process corner encoding signal. The difference is that in the embodiments of the present disclosure, the number of fuses included in each fuse group is 81, and the specific implementation process is not specifically limited in the embodiments of the present disclosure.

[0059] The DCC circuit calibration method provided by the embodiments of the present disclosure obtains the target DLL encoding signal acting on the DLL circuit, and then determines the initial DCC encoding signal based on the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal, solving the problem that when the number of delay units for DLL circuit adjustment cannot be determined, the asymmetry of the rising delay and falling delay of the clock signal may occur due to the different performances of the delay units under different PVT conditions, and further the problem of clock signal duty cycle distortion, ensuring the effectiveness of the determined initial DCC encoding signal.

[0060] Based on the above embodiments, the embodiments of the present disclosure further provide a DCC circuit calibration system. Figure 4 It is a schematic structural diagram of a DCC circuit calibration system provided by the embodiments of the present disclosure. As Figure 4 shown, the DCC circuit calibration system includes: A duty cycle difference signal determination module 410, configured to obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determine the duty cycle difference signal according to the internal clock signal and the feedback clock signal; An information acquisition module 420, configured to acquire the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, and the actual process corner level information of the DRAM; An initial DCC encoding signal determination module 430, configured to determine the initial DCC encoding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner level information; A target DCC encoding signal determination module 440, configured to adjust the initial DCC encoding signal according to the duty cycle difference signal to obtain the target DCC encoding signal, so as to control the conduction state of the DCC circuit through the target DCC encoding signal.

[0061] The DCC circuit calibration system provided by the embodiments of the present disclosure first obtains the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determines the duty cycle difference signal according to the internal clock signal and the feedback clock signal; then obtains the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, as well as the actual process corner grade information of the DRAM; and determines the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner grade information; finally, adjusts the initial DCC coding signal according to the duty cycle difference signal to obtain the target DCC coding signal, avoiding the need for a large amount of time for DCC circuit calibration to correct the duty cycle imbalance of the clock signal caused by temperature and voltage changes.

[0062] In a specific embodiment, before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner grade information, it further includes: Determine the clock phase difference signal according to the internal clock signal and the feedback clock signal; Obtain the second actual temperature information and the second actual voltage information of the DLL circuit at the target sampling moment, and determine the target step control signal according to the second actual temperature information, the second actual voltage information and the actual process corner grade information; Determine the target DLL coding signal according to the clock phase difference signal and the target step control signal; The determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal and the actual process corner grade information includes: Determine the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal and the actual process corner grade information.

[0063] In a specific embodiment, the determining the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal and the actual process corner grade information includes: Determine the first actual temperature coding signal, the first actual voltage coding signal and the actual process corner coding signal according to the first actual temperature information, the first actual voltage information and the actual process corner grade information; Determine the initial DCC coding signal according to the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal and the actual process corner coding signal.

[0064] In a specific embodiment, determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process corner encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: Determining the first actual temperature encoding signal according to the temperature range in which the first actual temperature information is located at a target sampling moment; Determining the first actual voltage encoding signal according to the voltage range in which the first actual voltage information is located at a target sampling moment; Determining the actual process corner encoding signal according to the actual process corner level information submitted by a test module.

[0065] In a specific embodiment, determining an initial DCC encoding signal according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process corner encoding signal includes: Obtaining test DCC encoding signals corresponding to test DLL encoding signals, test temperature encoding signals, test voltage encoding signals, and test process corner encoding signals for each target bit in a test stage; Determining the initial DCC encoding signal according to the correspondence between the target bit target DLL encoding signal and the target bit test DLL encoding signal, the correspondence between the first actual temperature encoding signal and the test temperature encoding signal, the correspondence between the first actual voltage encoding signal and the test voltage encoding signal, and the correspondence between the actual process corner encoding signal and the test process corner encoding signal.

[0066] In a specific embodiment, determining the target DLL encoding signal according to the clock phase difference signal and the target step control signal includes: Determining the number of target delay units that an adjustable delay chain needs to delay according to the clock phase difference signal and the target step control signal; Determining the target DLL encoding signal according to the number of target delay units that the adjustable delay chain needs to delay and the initial DLL encoding signal of the adjustable delay chain.

[0067] In a specific embodiment, determining the number of target delay units that the adjustable delay chain needs to delay according to the clock phase difference signal and the target step control signal includes: Determining the number of unit delay units that the adjustable delay chain needs to delay according to the clock phase difference signal; Determining the number of target delay units that the adjustable delay chain needs to delay according to the number of unit delay units and the target step control signal.

[0068] In a specific embodiment, obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal according to the internal clock signal and the feedback clock signal includes: Obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; Determining a duty cycle difference signal according to the duration corresponding to the high level of the internal clock signal and the duration corresponding to the high level of the feedback clock signal.

[0069] Based on the above embodiments, an embodiment of the present disclosure further provides a memory, which includes a DCC circuit calibration system. The DCC circuit calibration system controls the DCC circuit based on the DCC circuit calibration method and has the beneficial effects of any of the above embodiments.

[0070] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0071] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present application, the order numbers of the above steps / processes do not mean the order of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. Moreover, the serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0072] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0073] The above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, various changes and modifications can be made to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A duty cycle correction circuit calibration method, characterized in that: include: Acquire an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal; Acquire first actual temperature information and first actual voltage information of the DCC circuit at the target sampling moment, and actual process corner level information of the DRAM; Determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage information and the actual process angle level information; The initial DCC coding signal is adjusted according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

2. The method according to claim 1, characterized in that: Before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage information and the actual process angle level information, the method further includes: Determine a clock phase difference signal according to the internal clock signal and the feedback clock signal; Acquire second actual temperature information and second actual voltage information of the DLL circuit at a target sampling time, and determine a target step control signal according to the second actual temperature information, the second actual voltage information and the actual process angle level information; Determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal; The determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage information and the actual process angle level information comprises: An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature information, the first actual voltage information and the actual process corner level information.

3. The method according to claim 2, characterized in that The determining an initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage information and the actual process corner level information comprises: Determine a first actual temperature encoding signal, a first actual voltage encoding signal and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information and the actual process angle level information; An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process angle encoding signal.

4. The method according to claim 3, characterized in that The determining, according to the first actual temperature information, the first actual voltage information and the actual process angle level information, a first actual temperature encoding signal, a first actual voltage encoding signal and an actual process angle encoding signal comprises: Determine a first actual temperature encoding signal according to the temperature interval where the first actual temperature information is located at the target sampling time; Determine a first actual voltage encoding signal according to a voltage interval where the first actual voltage information is located at a target sampling time; According to the actual process angle level information submitted by the test module, an actual process angle coding signal is determined.

5. The method according to claim 3, characterized in that: The determining of the initial DCC encoding signal according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal and the actual process angle encoding signal comprises: Acquire the test DCC coding signal corresponding to the test DLL coding signal, the test temperature coding signal, the test voltage coding signal and the test process angle coding signal of each target bit in the test phase; An initial DCC coding signal is determined according to the correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

6. The method according to claim 2, characterized in that Determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal comprises: Determining the target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal; The target DLL coding signal is determined according to the target number of delay units that the adjustable delay chain needs to delay and the initial DLL coding signal of the adjustable delay chain.

7. The method according to claim 6, characterized in that The step of determining the target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step length control signal comprises: Determining the number of unit delay units that need to be delayed in the adjustable delay chain according to the clock phase difference signal; According to the number of unit delay cells and the target step length control signal, the target number of delay cells required to be delayed by the adjustable delay chain is determined.

8. The method according to claim 1, characterized in that: The acquiring the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determining the duty cycle difference signal according to the internal clock signal and the feedback clock signal, comprises: Obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; A duty cycle difference signal is determined according to a duration corresponding to a high level of the internal clock signal and a duration corresponding to a high level of the feedback clock signal.

9. A duty cycle correction circuit calibration system, characterized in that: include: A duty cycle difference signal determination module, used to obtain an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal according to the internal clock signal and the feedback clock signal; An information acquisition module, used to acquire first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, and actual process corner level information of the DRAM; An initial DCC coding signal determining module, configured to determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage information and the actual process angle level information; The target DCC coding signal determination module is used to adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

10. A memory, characterized in that: Includes the duty cycle correction circuit calibration system as described in claim 9.

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