Etching die cutting systems and related methods

Abstract

The invention relates to an etch die dicing system and related methods. Embodiments of a method of dicing a plurality of dies from a substrate may include removing a die stack coupled to the substrate in a die trace by etching the die stack to expose a top surface of a substrate material of the substrate in the die trace. A first width of a top surface of the substrate material may be exposed. The method may also include forming a plurality of dies by cutting the exposed substrate material of the substrate in the die trace using a cut width of a second width. The second width may be less than the first width.

Description

Technical Field

[0001] Aspects of the present document generally relate to plasma die cutting systems and methods. More specific embodiments relate to methods of etching and cutting semiconductor dies from a substrate. Background Art

[0002] Semiconductor devices include integrated circuits present in common electrical and electronic devices such as telephones, desktop computers, tablet computers, other computing devices, and other electronic devices. Semiconductor packages have been designed to protect semiconductor devices from shock, vibration, humidity, and electrostatic discharge. Summary of the Invention

[0003] Embodiments of a method of cutting multiple dies from a substrate may include removing a die stack coupled to the substrate in a die trace to expose a top surface of the substrate material of the substrate in the die trace. A first width of the top surface of the substrate material may be exposed. The method may further include forming multiple dies by cutting the exposed substrate material of the substrate in the die trace with a cut width of a second width. The second width may be less than the first width.

[0004] Embodiments of a method of cutting multiple dies from a substrate may include one, all, or any of the following:

[0005] Removing the die stack may occur before forming the multiple dies.

[0006] The etching may include wet etching or dry etching.

[0007] The etching may further include: forming a patterned layer on the die stack, the patterned layer exposing the die stack; etching the die stack; and removing the patterned layer.

[0008] Forming the patterned layer may include using a photoresist.

[0009] Forming the patterned layer may include using one of screen printing or stencil printing.

[0010] The die stack may include two layers.

[0011] The die stack may include three layers.

[0012] The die stack may include a silicon layer and two metal / oxide layers.

[0013] The die stack may include a complementary metal oxide semiconductor (CMOS) image sensor integrated with an application specific integrated circuit (ASIC) device.

[0014] Removing the die stack may further include removing a silicon layer coupled on the die trace.

[0015] Embodiments of a method of cutting a plurality of die from a substrate may include: removing at least one metal / oxide layer coupled to the substrate by etching the at least one metal / oxide layer to expose a remaining surface of the substrate material of the substrate, and forming a plurality of die by cutting the remaining surface of the substrate material in die tracks. A portion of the remaining surface of the substrate material may remain exposed after cutting.

[0016] Embodiments of a method of cutting a plurality of die from a substrate may include any one, all, or any combination of the following:

[0017] At least one metal / oxide layer may be removed prior to cutting the plurality of die.

[0018] The etching may include wet etching or dry etching.

[0019] The etching may further include: forming a patterned layer on the at least one metal / oxide layer, the patterned layer exposing the at least one metal / oxide layer; etching the at least one metal / oxide layer; and removing the patterned layer.

[0020] Forming the patterned layer may include using a photoresist.

[0021] Forming the patterned layer may include using one of screen printing or stencil printing.

[0022] The at least one metal / oxide layer may include two metal / oxide layers.

[0023] The at least one metal / oxide layer may include three layers.

[0024] Embodiments of a method of cutting a plurality of die from a substrate may include: fully etching the thickness of a die stack to expose a top surface of the substrate material of the substrate and sidewalls of the die stack, and forming a plurality of die by cutting the substrate material in die tracks. After cutting, a portion of the top surface of the substrate and the sidewalls may be retained.

[0025] Embodiments of a method of cutting a plurality of die included in a substrate may include removing at least one layer coupled to the substrate by etching the at least one layer downward into the substrate, wherein a portion of the at least one layer remains coupled to the substrate. The method may further include forming a plurality of die included in the substrate by cutting the substrate material in die tracks, wherein after cutting, a portion of the substrate material remains adjacent to a remaining portion of the at least one layer.

[0026] Embodiments of a method of cutting a plurality of die included in a substrate may include: etching a first region of a die stack to expose the substrate material of the substrate, and forming a plurality of die included in the substrate by cutting a die level in die tracks. The first region may be larger than the region of the die tracks.

[0027] Embodiments of a method of cutting a plurality of dies included in a substrate may include etching a die stack in a die track to expose a top surface of a substrate material of the substrate and sidewalls of at least one layer coupled to the substrate. The method may further include forming a plurality of dies included in the substrate by cutting the substrate material in the die track, wherein a portion of the top surface of the substrate material and the sidewalls of at least one layer are retained after cutting.

[0028] Embodiments of a method of cutting a plurality of dies included in a substrate may include: etching at least one layer coupled to the substrate to provide an exposed surface of the substrate, and cutting a plurality of dies included in the substrate by sawing the exposed surface of the substrate in a die track. The width of the exposed surface of the substrate may be wider than a cutting width of a saw blade used in the sawing.

[0029] For those of ordinary skill in the art, the above and other aspects, features, and advantages will be apparent from the detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments will be described below in conjunction with the drawings, in which like reference numerals represent like elements, and:

[0031] Figure 1 is a cross-sectional side view of an embodiment of a substrate coupled with a plurality of layers;

[0032] Figure 2 is the Figure 1 substrate with a plurality of layers removed in a die track region;

[0033] Figure 3 is the Figure 1 substrate cut into semiconductor dies;

[0034] Figure 4 is a cross-sectional side view of an embodiment of a cut semiconductor die;

[0035] Figure 5 is a top view of an embodiment of a cut semiconductor die;

[0036] Figure 6 and Figure 7 is a cross-sectional side view of a substrate coupled with a plurality of layers;

[0037] Figure 8 is the Figure 6 substrate subjected to electromagnetic radiation exposure;

[0038] Figure 9 is the Figure 8 substrate after a baking process;

[0039] Figure 10 is a cross-sectional side view of a substrate after a developing process that exposes die traces; Figure 9 ;

[0040] Figure 11 is a cross-sectional side view of a substrate after etching in die traces and removal of photoresist; Figure 10 ;

[0041] Figure 12 is a cross-sectional side view of a substrate after dicing; Figure 11 ;

[0042] Figure 13 is Figure 12 a partial view of a substrate;

[0043] Figure 14 is a cross-sectional side view of an embodiment of an etched and diced semiconductor die;

[0044] Figure 15 is Figure 14 a partial view of an etched and diced semiconductor die;

[0045] Figure 16 is a top view of an embodiment of the substrate with one or more layers coupled thereto;

[0046] Figure 17 is a top view of a substrate from which material of one or more layers in a die trace region has been removed; and Figure 16 ;

[0047] Figure 18 is a top view of a substrate after dicing into semiconductor dies; Figure 16 ; DETAILED DESCRIPTION

[0048] The present disclosure, aspects thereof, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art that are consistent with the intended systems and methods for die dicing will be apparent for use with particular embodiments of the present disclosure. Thus, for example, although the present invention discloses particular embodiments, such embodiments and implementation components may include such systems and methods known in the art for die dicing and implementation components and methods consistent with the intended operations and methods, and any shapes, sizes, styles, types, models, versions, measures, concentrations, materials, quantities, method elements, steps, etc. thereof.

[0049] See Figure 1, shows a cross-sectional side view of a substrate 2 coupled to a plurality of layers 4. The term "substrate" refers to a semiconductor substrate, as a semiconductor substrate is a common type of substrate. However, "substrate" is not a specific term used to refer to all types of semiconductor substrates. Similarly, the term "substrate" can refer to a wafer, as a wafer is a common type of substrate. However, "substrate" is not a specific term used to refer to all wafers. By way of non-limiting example, various types of semiconductor substrates that can be used in various embodiments in this document can be circular, rounded, square, rectangular, or any other closed shape. In various embodiments, the substrate 2 can comprise a substrate material, such as (by way of non-limiting example) single-crystalline silicon, silicon dioxide, glass, gallium arsenide, sapphire, ruby, silicon-on-insulator, silicon carbide, polycrystalline, or an amorphous state of any of the foregoing, and any other substrate material that can be used to construct a semiconductor device. In a particular embodiment, the substrate can be a silicon-on-insulator substrate. In various embodiments, the substrate 2 is thinned. In a particular embodiment, the substrate 2 can be less than 30 micrometers (μm) thick, less than 50 μm thick, and / or less than 100 μm thick. In other embodiments, the substrate can be greater than 100 μm thick and / or may not be thinned.

[0050] Referring again to Figure 1 , in various embodiments, an application-specific integrated circuit (hereinafter ASIC) 6 device is shown coupled to a complementary metal-oxide semiconductor (hereinafter CMOS) image sensor 8. The ASIC device 6 includes a substrate 2 and a first metal layer 10 disposed thereon. The CMOS sensor 8 includes a second metal / oxide layer 12 coupled to the first metal / oxide layer 10 and a silicon layer 14 coupled to the second metal / oxide layer 12. The metal / oxide layers 10, 12 and the silicon layer 14 are collectively referred to as layers 4 herein.

[0051] In various embodiments, the top side 3 of the substrate 2 can be coupled to the metal / oxide layers 10, 12. This applies to the case where the final semiconductor device is a back-illuminated (BSI) image sensor device. By way of non-limiting example, the metal / oxide layers 10, 12 can include metal oxides, copper, aluminum, nickel, any other metal, any alloy thereof, their oxides, or any combination thereof. In various embodiments, the substrate 2 can be directly coupled to the first metal / oxide layer 10. In other embodiments (although not shown), other layers such as a metal seed layer can be coupled between the metal / oxide layer 10 and the substrate 2.

[0052] Still referring to Figure 1, the silicon layer 14 of the CMOS sensor 8 is one of the plurality of layers 4. In various embodiments, by way of non-limiting example, the silicon layer 14 may comprise silicon, silicon nitride, oxide, metal electrical test structures, electrical test pads, silicon dioxide, polyimide, metal pads, residual under bump metallization (UBM), any combination thereof, and any other layer or material capable of facilitating electrical or thermal connection between one or more semiconductor dies and / or protecting one or more semiconductor dies from contamination. Thus, as used herein, the terms "silicon material" and "silicon layer" encompass any of the above materials, regardless of whether the material is deposited to serve as a passivation material or whether the material forms only a non-plasma-etchable portion or layer in the die track region.

[0053] The silicon layer 14 may be coupled on the metal / oxide layers 10, 12, as Figure 1 shown. By way of non-limiting example, the silicon layer 14 may include silicon, silicon dioxide, silicon nitride, polyimide, polymer materials, or any other type of semiconductor substrate or passivation layer material. In various embodiments, a plurality of passivation material layers may be included in the plurality of layers 4. Although Figure 1 the embodiment shown in includes three layers in the form of metal / oxide layers 10, 12 and a silicon layer 14 coupled on the substrate 2, other embodiments may include additional metal layers, additional passivation layers, additional other layers, layers without the metal / oxide layers 10, 12, layers without the silicon layer 14, or any combination thereof. These layers may completely cover the substrate 2, cover most of the substrate, or may only partially cover the substrate.

[0054] Although the methods disclosed herein focus on dicing the substrate 2, it should be understood that the substrate 2 may include and / or be coupled to other elements not shown, such as a plurality of semiconductor devices. In such embodiments, the plurality of semiconductor devices may include power semiconductor devices or non-power semiconductor devices. In embodiments where a plurality of power devices are coupled to the substrate, by way of non-limiting example, the power devices may include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), diodes, thyristors, silicon controlled rectifiers (SCRs), or any other type of power semiconductor device.

[0055] The substrate 2 and the plurality of layers 4 include a die track 16 having a die track width W therethrough 16 , and a cut region 18 having a cut width W therethrough 18 . The first width W of the die track 16 16 is wider than the second width W of the cut width 18 . The cut width W 18 is the width of a saw blade or a cutting line (where sawing is not used) for dicing the die. As Figure 1As shown, the metal / oxide layers 10, 12 and silicon layer 14 extend through the area of ​​the die trace 16 and the kerf region 18. In various embodiments, electrical test equipment and corresponding probe pads providing access to the electrical test equipment and structures may be included in at least one of the plurality of layers 4 and in the area of ​​the die trace 16.

[0056] refer to Figure 2 , showing the removal of multiple layers 4 in the die track 16 Figure 1 2. As used herein, when discussing the "removal" of a layer in a die track, it should be understood that this also includes the removal of a portion of a layer in the die track, without requiring the removal of the entire layer. In various embodiments, a method of cutting a plurality of dies included in a substrate includes exposing substrate material of the substrate 2 in the die track 16 by removing a plurality of layers 4 coupled to the substrate 2 in the die track 16. In various embodiments, the full width W may be etched. 16 , less than the full width W 16 , or greater than the cut width W 18 The width of the die track 16 is to expose the top surface 3 of the substrate material of the substrate 2. In embodiments having only a metal / oxide layer instead of having multiple layers or having both multiple layers and a metal / oxide layer or having a metal included in multiple layers, the method may include removing the metal or metal layer in the die track 16. Similarly, in embodiments having only a silicon layer (or some other layer) instead of having multiple layers, the method includes removing the silicon layer (or some other layer) in the die track 16.

[0057] Delamination is the separation between two coupled interfaces within the package and can occur, for example, between any of the layers in layer 4 and the substrate 2 or between the CMOS image sensor 8 and the ASIC device 6 after they have been bonded together. Delamination of the layers can lead to reliability issues of the die. Delamination may occur when there are defects in the layers, specifically metal / oxide layers. The slicing or dicing process is typically the cause of the initial defects in layer 4, which lead to delamination during packaging or during the operation of the semiconductor device. The sidewalls of the cut or the sidewalls of the die traces after the dicing operation may contain dicing damage. Using a saw, laser, water jet, or scribe to remove a portion of the substrate results in debris and cracks in the sidewalls of the die traces and in the layers adjacent to the die traces. If / when the cracks and debris spread into the device portion of the semiconductor die during operation, the presence of the cracks and debris has the potential to compromise the reliability of the resulting semiconductor package (and reduce die strength). Since the saw (or other) mechanical dicing process involves the friction of a rotating blade or the pressing of another object, such as a stylus, against the die surface, only by changing the saw (or other) processing variables (substrate feed rate, blade cut width, cut depth, multiple saw cuts, blade material, etc.) can the chipping and cracking be managed, but the chipping and cracking cannot be completely eliminated.

[0058] Cutting via mechanical slicing can also create defects in the metal and / or oxide layers 10, 12, which can lead to delamination. Cutting via laser scribing can have some advantages over mechanical slicing, but laser scribing still results in small defects due to the thermally induced stress generated during the slicing process. When the die is encapsulated in, for example, an image ball grid array (hereinafter referred to as iBGA) package, even these small defects can lead to delamination. It has been observed that defects larger than 1 micron may spread and cause delamination, while defects smaller than 0.2 micron are less likely to cause delamination.

[0059] To reduce die stack delamination in the iBGA image sensor package, exposure features are introduced into the die stack. A plurality of layers 4 coupled to the substrate 2 are removed from the die trace 16. In other words, the silicon layer 14 of the CMOS sensor 8, the second metal / oxide layer 12, and the first metal / oxide layer 10 of the ASIC device 6 are removed from the die trace 16 (die trace region). In various method and system embodiments, this removal can occur across the entire width of the die trace or across only a portion of the width of the die trace. The layers 4 can be removed by an etching process, such as wet etching or dry etching. The etching process reduces the defects in the metal and / or oxide layers 10, 12 in order to reduce or minimize delamination in the die or in the subsequently formed package. The die trace width W 16 is thus intentionally wider than the cut width W 18 so that the etched die trace width W16 Wider than the width of the dicing blade. By etching an area wider than that required for dicing or another cutting process, contact with the metal and / or oxide layers 10, 12 can be reduced or even eliminated during the dicing process, which reduces or prevents the creation of defects in the metal and / or oxide layers 10, 12, thereby reducing or potentially eliminating the risk of delamination.

[0060] refer to Figure 3 , showing the semiconductor die being cut into Figure 1 A cross-sectional side view of a substrate of FIG. Exposed features / surfaces 20 on the top surface 3 of substrate 2 remain after slicing. The width of exposed features 20, i.e., width W 20 is the etched die track width W 16 The kerf width W removed during the cutting process 18 The difference between the exposed feature width W 20 Sufficient space is provided between the dicing blade or mechanism and the sidewalls 24 of the layer 4 to reduce or eliminate contact with the sidewalls 24 during the dicing process, thereby reducing or preventing the creation of defects in the metal and / or oxide layers 10, 12. This has the effect of reducing or potentially eliminating the risk of delamination. In some embodiments, the exposed features 20 may be partially etched, wherein an over-etch is used to etch the material of the die stack including the metal and / or oxide layers.

[0061] In various embodiments, the kerf width W 18 , core track width W 16 The portions of the metal and / or oxide layers 10 , 12 and / or the silicon layer 14 that are removed in or within the die traces 16 may vary based on the specific method used and the particular dimensions of each feature.

[0062] In various embodiments, a method of cutting a plurality of dies included in a substrate includes cutting a plurality of dies 22 included in a substrate 2 by etching a layer 4 in a die track 16 followed by a cutting and dicing process. In various embodiments, a dicing die 22 may be cut using a dicing die cutter manufactured by Robert Bosch GmbH, Stuttgart Germany under the trade name The substrate material is cut using a plasma etching process marketed by Bosch (the "Bosch process"). In other embodiments, a saw, laser, water jet, or scribing and breaking process may be used to cut the plurality of dies 22 from the substrate 2.

[0063] refer to Figure 4 , shows a cross-sectional side view of a semiconductor die 22. The die 22 includes a substrate 2 having an exposed feature / surface 20 disposed on a top surface 3 of the substrate 2. As shown, the exposed feature 20 has a width W 20, this width is the distance between the sidewall 5 of the substrate 2 and the sidewall 24 of the layer 4. In various embodiments, the exposed feature 20 may be present on the top surface 3 surrounding the perimeter of the substrate 2 such that the sidewall 24 of the layer 4 is spaced from the sidewall 5 of the substrate 2 by the width W 20 . In various embodiments, the exposed feature 20 may be located in a designated area or partially surround the perimeter of the substrate 2.

[0064] Figure 5 A top view of a diced semiconductor die 22 including the exposed feature / surface 20 is shown. The exposed feature / surface 20 is disposed on the top surface 3 of the substrate 2. As shown, the exposed feature / surface 20 has a width W 20 , this width is the distance between the perimeter 28 of the substrate 2 and the layer 4. In various embodiments, the exposed feature / surface 20 may be present on the top surface 3 surrounding the perimeter 28 of the substrate 2 such that the sidewall 24 of the layer 4 is spaced from the perimeter 28 of the substrate 2 by the width W 20 . In various embodiments, the exposed feature / surface 20 may be located in a designated area or partially surround the perimeter 28 of the substrate 2. In various embodiments, the width W of the exposed surface / feature 20 20 is generally uniform around the perimeter 28, but may vary as needed or due to the manufacturing process. Refer to Figures 6 to 15 , a method of dicing a plurality of dies from a substrate similar to Figures 1 to 5 is shown. Refer to Figure 6 and Figure 7 , a cross-sectional side view of a substrate 32 coupled to one or more layers 34 is shown. The substrate 32 may be the same as or similar to any substrate type disclosed herein, and the one or more layers 34 may include any type of layer disclosed herein. Additionally, a photoresist layer 36 has been applied to the top surface 38 of the die stack 30. As Figure 7 shown, three layers 34 are coupled to the substrate 32, and a photoresist material layer 36 is disposed on the top surface 38 of the layer 34. Refer to Figure 8 , a cross-sectional side view of the substrate during imaging of the photoresist layer 36 using electromagnetic radiation Figure 6 is shown. The image / mask pattern 40 shown above the photoresist layer 36 includes a pattern of die track regions (if a positive photoresist material is used) or a pattern of die regions (if a negative photoresist material is used). During imaging, the photoresist layer 36 is exposed to electromagnetic radiation 42 such as UV light to cause a chemical reaction in the exposed areas of the photoresist, which will ultimately produce the desired pattern in the photoresist layer 36. Then, in use as Figure 10Before the shown developing process removes the exposed photoresist material (in the case of a positive photoresist) or removes the unexposed photoresist material (in the case of a negative photoresist), the die stack 30 undergoes a post-exposure bake process as shown in Figure 9 .

[0065] The bake process occurs after exposure to light or other electromagnetic radiation 42. During the bake process, the die stack 30 having the exposed photoresist material 36 thereon is heated. Post-exposure baking can reduce the presence of standing waves present in the photoresist material 36 after exposure. Post-exposure baking can also be beneficial when using negative photoresist technology to help retain the exposed photoresist and provide clear features after the developing process.

[0066] Now referring to Figure 10 , a substrate is shown after the developing process of the photoresist layer 36 has occurred, which now forms the pattern of the die traces / die trace regions that will later be etched into the die stack 30. The developing process involves treating the photoresist layer 36 with a chemical that promotes a chemical reaction, where the exposed (or unexposed) portions of the photoresist layer 36 are dissolved and removed in a rinse process, thus leaving the desired mask or pattern in place. The developed pattern in the photoresist layer 36 acts as a physical mask that protects the regions on the die stack 30 from chemical erosion during subsequent etching. As shown in Figure 10 , the exposed regions 44 of the photoresist layer 36 are removed after the developing process.

[0067] Figure 11 shows the die stack 30 after etching the die stack 30 using any of the etching methods disclosed herein and after removing the photoresist layer 36 using (by way of non-limiting example) ashing, solvent stripping, or any combination thereof. As a result of the etching, the top surface 31 of the substrate 32 is exposed in the die traces 50 / die trace regions. The die traces 50 now correspond to Figure 10 the exposed regions 44 of the photoresist 36 as shown.

[0068] Referring to Figures 12 to 15 , a cross-sectional side view of the substrate of Figure 11 is shown after being cut into semiconductor dies. The method for cutting the plurality of dies 60 included in the substrate 32 can include cutting the plurality of dies 60 using any of the methods disclosed herein. As shown in Figure 12 and Figure 13 , the die trace width W 50 is intentionally wider than the kerf width W 52is wide, such that the etched area / exposed area of the substrate is wider than the width of a dicing blade or other cutting process (laser / plasma etching / water jet / scribe and break). As a result of the etching process, an exposed feature / surface 62 of the substrate 32 is created between the sidewall 35 of the layer 34 and the edge or sidewall 33 of the substrate 32. The top surface 31 of the substrate 32 is exposed into the exposed feature 62. By etching an area wider than the area required for dicing or cutting, contact with the layer 34 can be reduced or even eliminated during the dicing process using a blade, which reduces or prevents the creation of defects in the layer 34, thereby reducing or eliminating the risk of delamination in the die 60.

[0069] Now referring Figure 13 , the exposed feature 62 on the top surface 31 of the substrate 32 is retained after the dicing process. The width of the exposed feature 62, i.e., the width W 62 is the etched die track width W 50 versus the kerf width W Figure 13 removed during the cutting process as shown in 52 . The exposed feature width W 62 provides sufficient space between the dicing blade or mechanism and the sidewall 35 of the layer 34 to reduce or eliminate contact with the sidewall 35 during the cutting process, thus reducing or preventing the creation of defects in the layer 34, which reduces or eliminates the risk of delamination, especially in the case of using a saw blade. In some embodiments, the exposed feature 62 may also be etched in the case of using an over-etch process to etch the die stack. In various embodiments, the kerf width W 52 , the die track width W 50 or the removed portion of the layer 34 in the die track 50 may vary based on the specific method used and the dimensions of the die track, etc.

[0070] Referring Figure 14 and Figure 15 , a cross-sectional side view of an embodiment of the semiconductor die 60 is shown. The die 60 includes a substrate 32 having an exposed feature / surface 62 disposed on the top surface 31 of the substrate 32. As Figure 15 shown, the exposed feature 62 has a width W 62 which is the distance between the sidewall 33 of the substrate 32 and the sidewall 35 of the layer 34. In various embodiments, the exposed feature 62 may be present on the top surface 31 adjacent to the perimeter of the substrate 32 such that the sidewall 35 of the layer 34 is spaced a distance W 62 from the sidewall 33 or perimeter of the substrate 32. In various embodiments, the exposed feature 62 may be located in a designated area or entirely or partially around the perimeter of the substrate 32.

[0071] Referring Figures 16 to 18 , shown is in relation to Figures 1 to 15A top view of a semiconductor substrate at various points during the implementation of a method of cutting a plurality of die from a substrate, similar or identical to the method shown. Specifically refer to Figure 16 , which shows a top view of a portion of the substrate having one or more layers 72 coupled to the substrate 70. The portion of the substrate 70 shown includes intersecting die tracks 80 (die track intersection points). The substrate 70 can be any type of substrate disclosed herein, and the one or more layers 72 can include any type of layer disclosed herein. Refer to Figure 17 , which shows the substrate with the material of one or more layers 72 removed from the die tracks 80 Figure 16 . In various method embodiments, etching using any etching method disclosed herein (including any patterning method for etching) is used to remove one or more layers 72. Figure 17 shows how the exposed substrate material of the substrate 70 in the die track 80 / die track region appears by removing one or more layers 72 coupled to the substrate 70 in the die tracks 80.

[0072] Refer to Figure 18 , which shows the substrate 70 Figure 16 after the substrate material has been cut into semiconductor dies 84. As Figure 18 shown, the method includes cutting a plurality of dies 84 from the substrate 70 using any method disclosed herein. As Figure 18 shown, the cut 82 is narrower than the die tracks 80. Thus, the cut width W 82 is narrower than the die track width W 80 . Thus, the top surface 76 of the substrate 70 is exposed by a previous etching process, thereby forming a region wider / greater than the cut width W 82 . The resulting die 84 includes the substrate 70 having exposed features 74 disposed on the top surface 76 of the substrate 70. The exposed features 74 have a width W 74 , which is the distance between the cut width W 82 and the die track width W 80 . In various embodiments, the exposed features 74 are present on the top surface 76 adjacent to the perimeter of the substrate 70 such that the sidewalls 78 of the layer 72 are spaced from the sidewalls 71 of the substrate 70 by a distance W 74 . In various embodiments, the exposed features 74 can be located in a designated area, entirely or partially surrounding the perimeter of the substrate 70. As shown in the embodiment shown in Figure 18 , after cutting, the exposed features 74 are clearly visible on the top surface 76 of each die 84.

[0073] Multiple die cut from the substrates disclosed herein may include any type of semiconductor die, including any type disclosed herein. The exposed features / surfaces are created before the slicing or dicing process occurs while the die are still located in the substrate or wafer. By etching the layers in the die stack with a width greater than that required for dicing, the reliability of the die can be improved because less damage is caused to the individual layers compared to dicing multiple die by sawing, laser, or other dicing methods. Additionally, the die can be strengthened because the etching can provide a defect-free or substantially defect-free surface finish and / or the exposed features can reduce or eliminate defects that can cause delamination in the die stack. Further, the photolithography techniques used to create the exposed features provide an accurate and controlled implementation of the features. The improved reliability and strength of the die can be particularly important when the die are used in power semiconductor devices. Power semiconductor devices such as IGBTs can be coupled to large lead frames and can include large heat sinks. The larger components of the semiconductor package can result in additional strain on the semiconductor die, which can cause the die, especially thinned die, to fail if not completely defect-free.

[0074] The exposed features on the die stack can reduce or eliminate the initial defects that can cause delamination. This improvement can enhance the overall reliability of iBGA packages, thus ensuring their performance and lifespan. Therefore, due to the increasing popularity of iBGA packages in automated applications, the exposed features on the substrate can be widely adopted. The reliability of iBGA packages has been improved by implementing the exposed features on the die stack, which may also give confidence to customers.

[0075] The method of dicing multiple die disclosed herein can be used in a variety of designs for thinned (or non-thinned) substrates with one or more layers coupled thereto.

[0076] Where the above description refers to specific embodiments of systems and methods for die dicing and related methods and implementing components, sub-components, methods, and sub-methods, it should be apparent that various modifications can be made without departing from their essence, and these embodiments, implementing components, sub-components, methods, and sub-methods can be applied to other systems and methods for die dicing and related methods.

Claims

1. A method for cutting a plurality of dies from a substrate, the method comprising: removing the die stack coupled to the substrate in a die street by etching the die stack to expose a top surface of a substrate material of the substrate in the die street, wherein a first width of the top surface of the substrate material is exposed; as well as A plurality of dies is formed by cutting exposed substrate material of the substrate in the die streets using a kerf width of a second width, wherein the second width is less than the first width. The method of claim 1 , wherein the die stack is removed prior to forming the plurality of dies. The method according to claim 1 , wherein the etching comprises wet etching or dry etching.

4. The method of claim 1, wherein etching further comprises: forming a patterned layer on the die stack, the patterned layer exposing the die stack; etching the die stack; as well as The patterned layer is removed. The method of claim 4 , wherein forming the patterned layer comprises using a photoresist. The method of claim 4 , wherein forming the patterned layer comprises using one of screen printing or stencil printing. The method of claim 1 , wherein the die stack comprises two layers. The method of claim 1 , wherein the die stack comprises three layers.

9. The method of claim 1, wherein the die stack comprises a silicon layer and two metal / oxide layers.

10. The method of claim 1, wherein the die stack comprises a complementary metal oxide semiconductor (CMOS) image sensor coupled to an application specific integrated circuit (ASIC) device.

11. The method of claim 1 , wherein removing the die stack further comprises removing a silicon layer coupled to the die streets.

12. A method for cutting a plurality of dies from a substrate, the method comprising: removing at least one metal / oxide layer coupled to a substrate by etching the at least one metal / oxide layer to expose a remaining surface of a substrate material of the substrate; as well as A plurality of dies is formed by cutting the remaining surface of the substrate material of the substrate in die streets, wherein a portion of the remaining surface of the substrate material remains exposed after cutting.

13. The method of claim 12, wherein the at least one metal / oxide layer is removed prior to singulating the plurality of dies. The method of claim 12 , wherein the etching comprises wet etching or dry etching.

15. The method of claim 12, wherein etching further comprises: forming a patterned layer on the at least one metal / oxide layer, the patterned layer exposing the at least one metal / oxide layer; etching the at least one metal / oxide layer; as well as The patterned layer is removed. The method of claim 15 , wherein forming the patterned layer comprises using a photoresist. The method of claim 15 , wherein forming the patterned layer comprises using one of screen printing or stencil printing.

18. The method of claim 12, wherein the at least one metal / oxide layer comprises two metal / oxide layers.

19. The method of claim 12, wherein the at least one metal / oxide layer comprises three layers.

20. A method of cutting a plurality of dies from a substrate, the method comprising: completely etching the thickness of the die stack to expose a top surface of the substrate material of the substrate and sidewalls of the die stack; as well as A plurality of dies is formed by cutting the substrate material in die streets, wherein a portion of the top surface of the substrate and the sidewalls remain after cutting.

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