Package substrate and method of manufacturing the same

Abstract

The present disclosure provides a packaging substrate and a manufacturing method thereof. The packaging substrate includes a carrier, a first dielectric layer, a second dielectric layer, a plurality of first circuit layers, and a plurality of second circuit layers. The carrier has opposite first and second sides. The first dielectric layer is formed on the first side of the carrier. The second dielectric layer is formed on the second side of the carrier. The plurality of first circuit layers is formed on the first dielectric layer. The plurality of second circuit layers is formed on the second dielectric layer. The copper volume of the first circuit layers formed on the first dielectric layer is equal to or greater than the copper volume of the second circuit layers formed on the second dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a packaging substrate and its manufacturing method, and more particularly to a packaging substrate and its manufacturing method that reduces warpage by controlling the copper volume difference between different circuit layers and different regions of the same layer. Background Technology

[0002] With the booming development of the electronics industry, electronic products are trending towards thinner, lighter, and smaller forms, while focusing on high performance, high functionality, and high speed. Therefore, to meet the demands for high integration and miniaturization in semiconductor devices, packaging substrates with high-density and fine-pitch lines, such as embedded trace substrates (ETS) packaging substrates, are often used in packaging processes. However, embedded trace packaging substrates are prone to warping during manufacturing, which adversely affects the performance and reliability of electronic products. Existing research attempts to mitigate this warping problem by controlling the fiber orientation and sequence of internal materials, but the warping issue persists.

[0003] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Summary of the Invention

[0004] The purpose of this disclosure is to provide a packaging substrate and its manufacturing method to solve at least one of the above-mentioned problems.

[0005] This disclosure provides a packaging substrate, comprising: a carrier having opposing first and second sides; a first dielectric layer formed on the first side of the carrier; a second dielectric layer formed on the second side of the carrier; a plurality of first circuit layers formed on the first side, wherein at least one of the plurality of first circuit layers is formed in the first dielectric layer and at least another of the plurality of first circuit layers is formed on the first dielectric layer; and a plurality of second circuit layers formed on the second side, wherein at least one of the plurality of second circuit layers is formed in the second dielectric layer and at least another of the plurality of second circuit layers is formed on the second dielectric layer; wherein the copper volume of the first circuit layer formed on the first dielectric layer is equal to or greater than the copper volume of the second circuit layer formed on the second dielectric layer.

[0006] The aforementioned packaging substrate further includes a first solder mask layer formed on the first dielectric layer and exposing the first circuit layer, and a second solder mask layer formed on the second dielectric layer and exposing the second circuit layer, wherein the volume of the first solder mask layer is smaller than the volume of the second solder mask layer.

[0007] As described above, the top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the first circuit layer in the first intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the first solder mask in the first intermediate region, the copper volume of the second circuit layer in the second surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, and the volume of the second solder mask in the second surrounding region is equal to the volume of the second solder mask in the second intermediate region.

[0008] As described above, the top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the second solder mask in the second intermediate region, and the area of ​​the first intermediate region and the first surrounding region is equal to the area of ​​the second intermediate region and the second surrounding region.

[0009] As described above, in the packaging substrate, the number of the plurality of first line layers is even and the number of the plurality of second line layers is even, or the number of the plurality of first line layers is odd and the number of the plurality of second line layers is even, and the odd number is greater than the even number.

[0010] This disclosure also provides a method for manufacturing a packaging substrate, comprising: providing a carrier having opposing first sides and second sides; forming a first dielectric layer and a plurality of first circuit layers on the first side of the carrier, and forming a second dielectric layer and a plurality of second circuit layers on the second side of the carrier, wherein at least one of the plurality of first circuit layers is formed in the first dielectric layer and at least another of the plurality of first circuit layers is formed on the first dielectric layer, and at least one of the plurality of second circuit layers is formed in the second dielectric layer and at least another of the plurality of second circuit layers is formed on the second dielectric layer; wherein the copper volume of the first circuit layer formed on the first dielectric layer is equal to or greater than the copper volume of the second circuit layer formed on the second dielectric layer.

[0011] The aforementioned method for manufacturing a packaging substrate further includes forming a first solder mask layer on the first dielectric layer that exposes the first circuit layer, and forming a second solder mask layer on the second dielectric layer that exposes the second circuit layer, wherein the volume of the first solder mask layer is smaller than the volume of the second solder mask layer.

[0012] As described above in the method for manufacturing a packaging substrate, the top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the first circuit layer in the first intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the first solder mask in the first intermediate region, the copper volume of the second circuit layer in the second surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, and the volume of the second solder mask in the second surrounding region is equal to the volume of the second solder mask in the second intermediate region.

[0013] As described above in the method for manufacturing a packaging substrate, the top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the second solder mask in the second intermediate region, and the area of ​​the first intermediate region and the first surrounding region is equal to the area of ​​the second intermediate region and the second surrounding region.

[0014] As described above in the method for manufacturing the packaging substrate, the number of the plurality of first circuit layers is even and the number of the plurality of second circuit layers is even, or the number of the plurality of first circuit layers is odd and the number of the plurality of second circuit layers is even, and the odd number is greater than the even number.

[0015] In summary, by controlling the copper volume of different circuit layers or different regions within the same layer, the risk of warpage on high and low temperature substrates can be reduced, thereby improving the reliability and yield of subsequent products and reducing production costs. Furthermore, the copper volume of the aforementioned circuit layers can be controlled by the electroplating process, and the rectifier control current mode of the electroplating equipment is single-mode, which can optimize the uniformity and thickness distribution of the electroplated layer. Attached Figure Description

[0016] Figures 1A to 1D This is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate disclosed herein.

[0017] Figure 2 This is a cross-sectional schematic diagram of another embodiment of the packaging substrate disclosed herein.

[0018] Figure 3 This is a schematic diagram of the top surface of the packaging substrate disclosed herein.

[0019] Figure 4 This is a schematic diagram of the bottom surface of the packaging substrate disclosed herein.

[0020] The attached figures are labeled as follows:

[0021] 1,2 package substrate

[0022] 1a,1a',1b circuit structure

[0023] 11, 13, 17 First Line Layer

[0024] 12 First dielectric layer

[0025] 120, 220 blind holes

[0026] 121 First Dielectric Material

[0027] 122 Second Dielectric Material

[0028] 14, 16, 24 conductive pillars

[0029] 15 First solder mask layer

[0030] 21,23 Second Line Layer

[0031] 22 Second dielectric layer

[0032] 25 Second solder resist layer

[0033] 9. Bearing components

[0034] 9a First side

[0035] 9b Second side

[0036] 90 plate body

[0037] 91 Release layer

[0038] 92 Metal Layer

[0039] A Top Surface

[0040] A1 First Surrounding Zone

[0041] A2 First Intermediate Zone

[0042] B Bottom surface

[0043] B1 Second Ring Road

[0044] B2 Second Intermediate Zone. Detailed Implementation

[0045] The following specific embodiments illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification.

[0046] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0047] Figures 1A to 1D This is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate 1 disclosed herein. In this embodiment, the number of first circuit layers 11 and 13 is even, and the number of second circuit layers 21 and 23 is even, that is, the circuit structures 1a and 1b are symmetrical.

[0048] like Figure 1A As shown, a carrier 9 is provided, wherein a release layer 91 is respectively formed on two opposing surfaces of the plate 90, and a metal layer 92 is formed on the release layer 91. The carrier 9 has opposing first sides 9a and second sides 9b. A plurality of first circuit layers 11 and a plurality of second circuit layers 21 are respectively formed on the first side 9a and the second side 9b of the carrier 9.

[0049] In this embodiment, the carrier 9 is a temporary carrier plate, and its plate body 90 may be, for example, an organic polymer plate containing bis(maleimide) triazine (BT), glass fiber prepreg (PP), or other plates. The release layer 91 may be, for example, a thick copper layer of copper foil, and the metal layer 92 may be, for example, a thin copper layer, which is formed on the release layer 91 by electroplating or deposition.

[0050] In this embodiment, patterned resist layers with opening areas can be formed on the first side 9a and the second side 9b of the carrier 9, respectively, and the first circuit layer 11 and the second circuit layer 21 can be formed in the opening area by electroplating metal (such as copper) or other means, and then the patterned resist layers can be removed.

[0051] like Figure 1B As shown, a first dielectric layer 12 and a second dielectric layer 22 are formed on the first side 9a and the second side 9b of the carrier 9, respectively. Then, multiple blind vias 120 and 220 are formed on the first dielectric layer 12 and the second dielectric layer 22, respectively, to expose the first circuit layer 11 and the second circuit layer 21, for example, by means of laser.

[0052] In this embodiment, the first dielectric layer 12 and the second dielectric layer 22 are ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0053] like Figure 1C As shown, copper is electroplated on the first dielectric layer 12 and in the plurality of blind vias 120 to integrally form the first circuit layer 13 and the conductive pillars 14. Similarly, copper is electroplated on the second dielectric layer 22 and in the plurality of blind vias 220 to integrally form the second circuit layer 23 and the conductive pillars 24.

[0054] In this embodiment, the first circuit layer 13, the second circuit layer 23, and the conductive pillars 14 and 24 adopt the redistribution layer (RDL) specification, and the conductive pillars 14 and 24 are conical in shape.

[0055] like Figure 1D As shown, a first solder mask 15 is formed on the first dielectric layer 12 to expose the first circuit layer 13, thereby forming circuit structure 1a. At the same time, a second solder mask 25 is formed on the second dielectric layer 22 to expose the second circuit layer 23, thereby forming circuit structure 1b.

[0056] In this embodiment, the copper volume of the first circuit layer 13 formed on the first dielectric layer 12 is equal to or greater than the copper volume of the second circuit layer 23 formed on the second dielectric layer 22. The copper volume is calculated by multiplying the residual copper ratio by the copper thickness. For example, the copper volume of the first circuit layer 13 is the residual copper ratio of the first circuit layer 13 on the first dielectric layer 12 multiplied by the copper thickness of the first circuit layer 13 itself, and the copper volume of the second circuit layer 23 is the residual copper ratio of the second circuit layer 23 on the second dielectric layer 22 multiplied by the copper thickness of the second circuit layer 23 itself. One or both of the residual copper ratio and copper thickness can be adjusted according to the desired amount of warpage to be suppressed, thereby obtaining the required copper volume.

[0057] In this embodiment, the volume of the first solder mask layer 15 is smaller than the volume of the second solder mask layer 25.

[0058] Subsequently, the release layer 91 can be used to separate the substrate 90 of the carrier 9 from the circuit structures 1a and 1b, and the metal layer 92 can be removed by etching, so that the circuit structures 1a and 1b can be used for subsequent applications. For example, multiple solder balls can be provided and electrically connected to the first circuit layers 11 and 13 or the second circuit layers 21 and 23, and multiple solder balls can be placed on electronic devices such as semiconductor chips, passive components, silicon interposers, circuit boards or other components to form an electronic package.

[0059] In summary, by controlling the copper volume of the first circuit layer 13 and the second circuit layer 23, the risk of warpage of the high and low temperature carrier board can be reduced, thereby improving the reliability and yield of subsequent products and reducing production costs. Furthermore, the copper volume of the first circuit layers 11 and 13 and the second circuit layers 21 and 23 can be controlled by the electroplating process, and the rectifier of the electroplating equipment uses a single current control method, which can optimize the uniformity and thickness distribution of the electroplated layer.

[0060] Figure 2 This is a cross-sectional schematic diagram of the packaging substrate 2 of this disclosure. In this embodiment, the number of first circuit layers 11, 13, and 17 is odd, the number of second circuit layers 21 and 23 is even, and the number of first circuit layers 11, 13, and 17 is greater than the number of second circuit layers 21 and 23, that is, the circuit structures 1a' and 1b are asymmetrical.

[0061] In this embodiment, the same as Figures 1A to 1C The manufacturing process involves sequentially forming a first circuit layer 11, a first dielectric material 121, a conductive pillar 14, and a first circuit layer 13 on the first side 9a of the carrier 9, and sequentially forming a second circuit layer 21, a second dielectric layer 22, a conductive pillar 24, and a second circuit layer 23 on the second side 9b of the carrier 9. Next, using a layer-addition method, a second dielectric material 122, a conductive pillar 16, and a first circuit layer 17 are sequentially formed on the first dielectric material 121, wherein the first dielectric material 121 and the second dielectric material 122 constitute the first dielectric layer 12. Then, a first solder mask layer 15 exposing the first circuit layer 17 is formed on the first dielectric layer 12 to form a circuit structure 1a'. Simultaneously, a second solder mask layer 25 exposing the second circuit layer 23 is formed on the second dielectric layer 22 to form a circuit structure 1b.

[0062] In this embodiment, the copper volume of the first circuit layer 17 formed on the first dielectric layer 12 is equal to or greater than the copper volume of the second circuit layer 23 formed on the second dielectric layer 22. The copper volume is calculated by multiplying the residual copper ratio by the copper thickness. For example, the copper volume of the first circuit layer 17 is the residual copper ratio of the first circuit layer 17 on the first dielectric layer 12 multiplied by the copper thickness of the first circuit layer 17 itself, and the copper volume of the second circuit layer 23 is the residual copper ratio of the second circuit layer 23 on the second dielectric layer 22 multiplied by the copper thickness of the second circuit layer 23 itself. One or both of the residual copper ratio and copper thickness can be adjusted according to the desired amount of warpage to be suppressed, thereby obtaining the required copper volume.

[0063] In this embodiment, the volume of the first solder mask layer 15 is smaller than the volume of the second solder mask layer 25.

[0064] In one embodiment, the packaging substrate 1 has a top surface A and a bottom surface B opposite to each other, wherein the top surface A corresponds to a first side 9a and the bottom surface B corresponds to a second side 9b. Figure 3As shown, the top surface A is defined with a first intermediate region A2 (for example, there can be two) and a first surrounding region A1 surrounding the first intermediate region A2. Figure 4 As shown, the bottom surface B defines a second intermediate region B2 (for example, there can be two) and a second surrounding region B1 surrounding the second intermediate region B2.

[0065] The copper volume of the first circuit layers 11, 13, and 17 in the first surrounding region A1 is equal to the copper volume of the first circuit layers 11, 13, and 17 in the first intermediate region A2. The volume of the first solder mask layer 15 in the first surrounding region A1 is equal to the volume of the first solder mask layer 15 in the first intermediate region A2. The copper volume of the second circuit layers 21 and 23 in the second surrounding region B1 is equal to the copper volume of the second circuit layers 21 and 23 in the second intermediate region B2. The volume of the second solder mask layer 25 in the second surrounding region B1 is equal to the volume of the second solder mask layer 25 in the second intermediate region B2.

[0066] In another embodiment, the copper volume of the first circuit layers 11, 13, and 17 of the first surrounding region A1 is equal to the copper volume of the second circuit layers 21 and 23 of the second intermediate region B2. The volume of the first solder mask layer 15 of the first surrounding region A1 is equal to the volume of the second solder mask layer 25 of the second intermediate region B2. And the area of ​​the first intermediate region A2 and the first surrounding region A1 is equal to the area of ​​the second intermediate region B2 and the second surrounding region B1.

[0067] In summary, by controlling the copper volume of the first circuit layer 13 and the second circuit layer 23, controlling the copper volumes of the first circuit layers 11, 13, and 17 in the first surrounding area A1 and the first intermediate area A2 to be the same, controlling the volume of the first solder mask layer 15 in the first surrounding area A1 and the first intermediate area A2 to be the same, and controlling the copper volumes of the second circuit layers 21 and 23 in the second surrounding area B1 and the second intermediate area B2 to be the same, or controlling the volume of the second solder mask layer 25 in the second surrounding area B1 and the second intermediate area B2 to be the same, the risk of warping of the high and low temperature carrier board can be reduced, thereby improving the reliability and yield of subsequent products and reducing production costs. Furthermore, the copper volumes of the first circuit layers 11, 13, and 17 and the second circuit layers 21 and 23 can be controlled by the electroplating process, and the control current mode of the rectifier of the electroplating equipment is single, which can optimize the uniformity and thickness distribution of the electroplated layer.

[0068] The above embodiments are illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be as set forth in the claims.

Claims

1. A packaging substrate, characterized in that... include: The support member has a first side and a second side facing each other; A first dielectric layer is formed on the first side of the carrier; A second dielectric layer is formed on the second side of the carrier; Multiple first line layers are formed on the first side, and at least one of the multiple first line layers is formed in the first dielectric layer and at least another layer of the multiple first line layers is formed on the first dielectric layer, wherein the number of the multiple first line layers is odd. as well as Multiple second circuit layers are formed on the second side, and at least one of the multiple second circuit layers is formed in the second dielectric layer and at least another layer of the multiple second circuit layers is formed on the second dielectric layer. The number of the multiple second circuit layers is even, and the odd number is greater than the even number. Wherein, the copper volume of the outermost first circuit layer formed on the first dielectric layer is equal to or greater than the copper volume of the outermost second circuit layer formed on the second dielectric layer.

2. The packaging substrate as described in claim 1, characterized in that, The packaging substrate further includes a first solder resist layer formed on the first dielectric layer and exposing the first circuit layer, and a second solder resist layer formed on the second dielectric layer and exposing the second circuit layer, wherein the volume of the first solder resist layer is smaller than the volume of the second solder resist layer.

3. The packaging substrate as described in claim 2, characterized in that, The top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the first circuit layer in the first intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the first solder mask in the first intermediate region, the copper volume of the second circuit layer in the second surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, and the volume of the second solder mask in the second surrounding region is equal to the volume of the second solder mask in the second intermediate region.

4. The packaging substrate as described in claim 2, characterized in that, The top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the second solder mask in the second intermediate region, and the area of ​​the first intermediate region and the first surrounding region is equal to the area of ​​the second intermediate region and the second surrounding region.

5. A method for manufacturing a packaging substrate, characterized in that... include: Provide a support member having opposing first and second sides; as well as A first dielectric layer and a plurality of first circuit layers are formed on the first side of the carrier, and a second dielectric layer and a plurality of second circuit layers are formed on the second side of the carrier, wherein at least one of the plurality of first circuit layers is formed in the first dielectric layer and at least another of the plurality of first circuit layers is formed on the first dielectric layer, and at least one of the plurality of second circuit layers is formed in the second dielectric layer and at least another of the plurality of second circuit layers is formed on the second dielectric layer; Wherein, the number of the plurality of first circuit layers is odd, the number of the plurality of second circuit layers is even, the odd number is greater than the even number, and the copper volume of the outermost first circuit layer formed on the first dielectric layer is equal to or greater than the copper volume of the outermost second circuit layer formed on the second dielectric layer.

6. The method for manufacturing the packaging substrate as described in claim 5, characterized in that, The manufacturing method further includes forming a first solder mask layer on the first dielectric layer that exposes the first circuit layer, and forming a second solder mask layer on the second dielectric layer that exposes the second circuit layer, wherein the volume of the first solder mask layer is smaller than the volume of the second solder mask layer.

7. The method for manufacturing the packaging substrate as described in claim 6, characterized in that, The top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the first circuit layer in the first intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the first solder mask in the first intermediate region, the copper volume of the second circuit layer in the second surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, and the volume of the second solder mask in the second surrounding region is equal to the volume of the second solder mask in the second intermediate region.

8. The method for manufacturing the packaging substrate as described in claim 6, characterized in that, The top surface of the packaging substrate defines a first intermediate region and a first surrounding region surrounding the first intermediate region, and the bottom surface of the packaging substrate defines a second intermediate region and a second surrounding region surrounding the second intermediate region. The copper volume of the first circuit layer in the first surrounding region is equal to the copper volume of the second circuit layer in the second intermediate region, the volume of the first solder mask in the first surrounding region is equal to the volume of the second solder mask in the second intermediate region, and the area of ​​the first intermediate region and the first surrounding region is equal to the area of ​​the second intermediate region and the second surrounding region.

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