Methods and architectures for mixed solder and solder-free die stacks

Abstract

Methods and architectures for mixed solder and solder-free die stacks. An apparatus includes a semiconductor die solderless bonded (using a Hybrid Bonded Interconnect (HBI) technique) to a base die at a bottom surface. The semiconductor die includes a region having a through silicon via (TSV) exposed at an upper surface. The semiconductor die and the TSV are configured to have solder attachment features attached thereto, such as a DRAM or a high bandwidth memory (HBM). Solder attachment features are stacked on the semiconductor die and soldered to the semiconductor die at the TSVs.

Description

BACKGROUND OF THE INVENTION

[0001] When a large die is diced into smaller dielets for throughput (or other) reasons, they need to be connected together with a high wiring density such that functionally they act like a single monolithic die. One of the important factors determining the wiring density is the minimum distance between bumps, called the interconnect pitch. To advance Moore's Law, the interconnect pitch must be shrunk, and below a pitch of about 25 μm, solder-based interconnects or solder attachment processes start to experience technical problems in the form of failures and faults. Hybrid bonding (also known as direct bonding interconnect (DBI)) is a desired packaging technology for scaling down the interconnect pitch, but there is still a technical need to integrate hybrid bonding interconnect (HBI) components with solder attachment components. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A The side-by-side placement of solder attachment components is shown.

[0003] Figure 1B Exemplary multi-die assemblies are provided in accordance with various embodiments, where semiconductor dies are hybrid fusion bonded together.

[0004] Figure 2 A first exemplary multi-die assembly 200 solution for hybrid solder and solderless die stacks is shown.

[0005] Figure 3 and Figure 4 Additional exemplary multi-die assemblies for hybrid solder and solderless die stacks are provided in accordance with various embodiments.

[0006] Figure 5 Exemplary process steps of a method for hybrid solder and solderless die stacks in accordance with embodiments described herein are shown.

[0007] Figure 6 An image is provided to show the Figure 5 process described in.

[0008] Figure 7 is a top view of a wafer and die that may be included in any embodiment disclosed herein.

[0009] Figure 8 is a simplified cross-sectional side view showing an implementation of an integrated circuit on a die that may be included in any embodiment disclosed herein.

[0010] Figures 9A to 9D is a simplified perspective view of exemplary planar transistors, FinFET transistors, all-around gate transistors, and stacked all-around gate transistors that may be implemented in various embodiments.

[0011] Figure 10is a cross-sectional side view of a microelectronic component that may include any of the embodiments disclosed herein.

[0012] Figure 11 is a block diagram of an example electrical device that may include any of the embodiments disclosed herein. Detailed Description

[0013] In some cases, such as for increasing yield, the functionality of a large monolithic die is implemented using multiple smaller dielets connected together at a high wiring density. One of the important factors determining the wiring density is the minimum distance between bumps, referred to as the interconnect pitch. The solder-based side-by-side placement of solder attachment components employed in various multi-die assemblies may introduce long lateral distances (referred to as the interconnect pitch) for some signals. To advance Moore's Law, the interconnect pitch must be reduced, and below a pitch of about 25 μm, solder-based interconnects or solder attachment processes begin to experience technical problems in the form of failures and malfunctions.

[0014] Hybrid bonding (also known as direct bonding interconnect (DBI)) is a packaging technology that involves bonding the surfaces of two semiconductor devices together under applied pressure and / or elevated temperature, typically as a die stacking solution, resulting in dielectric-to-dielectric and metal-to-metal bonds. HBI advantageously enables "small" pitches (defined herein as pitches less than 10 microns + / - 10%, and in some cases, pitches less than 1 micron + / - 10%). However, for various reasons, there are many components that retain solder attachment components with solder-based interconnects. Thus, while HBI is a desirable packaging technology for stacking die and reducing the interconnect pitch, there is still a technical need to integrate hybrid bonding interconnect (HBI) components with solder attachment components. In other words, there is a need for hybrid solder and solderless die stacking architectures and methods of manufacturing the same.

[0015] The embodiments disclosed herein present a technical solution to the above-described technical problems in the form of methods and architectures for hybrid solder and solderless die stacking. The proposed embodiments create an HBI die complex having two or more semiconductor die, and stack solder attachment components such as DRAM or high bandwidth memory (HBM) on the HBI die complex. These concepts are elaborated in more detail below.

[0016] The following describes exemplary embodiments with reference to the following drawings, where like reference numerals represent like elements. The drawings are not necessarily to scale and may depend on the spatial orientation and relative positioning of the features. As can be understood, certain terms such as "ceiling" and "floor", as well as "upper", "uppermost", "lower", "above", "below", "bottom", and "top" refer to the direction based on viewing the reference drawings. In addition, terms such as "front", "back", "rear", "side", "vertical", and "horizontal" may describe the orientation and / or position of portions of components within a consistent but arbitrary reference system, which becomes clear by referring to the text describing the components in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0017] The following detailed description is not intended to limit the application and use of the disclosed technology. It is apparent that novel embodiments may be practiced without each detail described herein. For the sake of brevity, well-known structures and devices may be shown in block diagram form to assist in their description.

[0018] Figure 1A Illustrate (using cross-sectional images or the Z-X reference frame) the technical problems presented by solder attachment components placed side by side. In the illustration, the IC die 102 has a bump region 1, and a second die such as a high-bandwidth memory (HBM) 104 has a bump region 2. The dedicated circuitry system indicated as PHY in the illustration provides translation support between the input / output (I / O) speed and voltage of the components (IC die 102 and HBM 104). Generally, the component 106 is used to scale the wiring and interconnections between the components (IC die 102 and HBM 104); the component 106 can be an organic or silicon interposer, an organic substrate, or a silicon bridge embedded in a substrate (not shown).

[0019] As Figure 1A shown, placing these side by side may cause long lateral distances for some signals. For example, the lateral distance 112 combines the distance 108 between the dies, plus the distance to the edge 110 of the bump region, plus the distance across the bump region specifying bump region 2 at the maximum distance. Scaling the interconnect pitch can help reduce the lateral distance that can be achieved by hybrid bonding. However, due to the side-by-side placement, the lateral path caused by 110 and bump region 2 cannot be avoided.

[0020] In Figure 1BIn [the figure], the exemplary semiconductor die 132 includes an “active” or die area 134 of front-end-of-line (FEOL) semiconductor processing and structures, where individual devices (e.g., integrated circuit systems such as transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. The die area 134 is covered with a dielectric and / or oxide layer interspersed with conductive interconnects (vias and traces), built onto the HB surface 133 (note that the die / core 132 is flipped, so “built onto” is relative, and the HB surface 133 appears as the lower surface of the die 132 in the multi-die assembly 130). At least one hybrid-bonding conductive contact 107-1 is exposed at the HB surface 133. Similarly, the die 136 is similarly constructed and has an HB surface 137, which has at least one corresponding hybrid-bonding conductive contact 107-2. The hybrid-bonding conductive contacts 107-1 and 107-2 (referred to herein simply as conductive contacts 107) are conductive and typically include a metal such as copper (Cu). The conductive contacts 107 are surrounded by a dielectric material at their respective HB surfaces (in a plan view). In other words, there is dielectric material adjacent to the metal / Cu contacts 107.

[0021] The die 132 is hybrid-bonded to the die 136. Thus, at the HB interface 135: the insulating or dielectric material of the die 132 is bonded to the insulating or dielectric material of the die 136 (e.g., SiOx to SiOx, SiOxNy to SiOxNy, etc.), and the conductive contact 107-1 from the die 132 is directly metal-bonded to the corresponding conductive contact 107-2 from the die 136, and there is no solder material at this HB interface 135. As shown, at least one conductive contact 107-1 is coupled, for example, via a through-silicon via (TSV) 109-1 to the integrated circuit system of the die area 134 and is exposed at the HB hybrid-bonding surface 133. In various aspects of the present disclosure, the conductive contact 107-1 is used to provide a circuit path from a corresponding node in the die area 134 through the bonding layer and is exposed at the surface (the lower surface in the illustration) of the HB to the HB surface 137 of the semiconductor die 136. In various applications, a multi-die assembly 130 is created, where the semiconductor die 134 is flipped and HB hybrid-bonded to the semiconductor die 136.

[0022] In some embodiments, the semiconductor die 136 includes an active integrated circuit system; in other embodiments, the semiconductor die 136 is passive (e.g., referred to as a "base die") having wiring and vias to support interconnects and power routing passing therethrough (e.g., via TSVs or through dielectric vias (TDV 109-2)). In various embodiments, the bottom surface (in the illustration) of the semiconductor die 136 has a plurality of solder balls or bumps electrically connected to internal wiring such as TDV 109-2. By implementing the above-described hybrid bonding interconnect (HBI) architecture on the first semiconductor die 132 and the second semiconductor die 136, a multi-die assembly 130 can be created using a hybrid bonding process. In some embodiments, the multi-die assembly 130 may be at least part of what is referred to as an "HBI complex".

[0023] As described above, there are technical challenges when an HBI complex (e.g., multi-die assembly 130) is to be assembled with a solder attachment component such as high bandwidth memory HBM 104. Accordingly, aspects of the present disclosure present technical solutions. In the following figures, the HB interfaces described in conjunction with Figure 1B have been simplified to patterned layers HBI 207 / 307 / 407.

[0024] Figure 2 A first exemplary multi-die assembly 200 solution for hybrid solder and solderless die stacking is shown. The multi-die assembly 200 is similar to the multi-die assembly 130 with the addition of a solder attachment component 208. The semiconductor die 202 is hybrid bonded to the upper surface of the base die 206 on its bottom surface as indicated by HBI 207 (in the assembled multi-die assembly 200, there may be more than one semiconductor die HBI bonded to the base die 206 as shown by the second semiconductor die 220).

[0025] Advantageously, embodiments achieve hybrid solder and solderless die stacking by attaching the solder bump region 210 of the solder attachment component 208 to the upper surface of the semiconductor die 202. In view of this, embodiments of the semiconductor die 202 can be modified as described herein. As shown, the region 209 of the upper surface of the semiconductor die 202 is configured with through-silicon vias (TSVs) to connect the component 208 to the die 202 via a die-to-die physical interface (D2D PHY) as shown. The vertical double arrows indicate the presence of an operative electrical path for signals traveling from the base die 206 through the semiconductor die 202 to the solder attachment component 208. As previously mentioned, in various embodiments, the solder attachment component 208 is an HBM, DRAM, or solder-based die.

[0026] In some embodiments, an optional redistribution layer (RDL) 212 is included between the upper surface of the semiconductor die 202 and the solder bump region 210 of the solder attach component 208. The optional RDL 212 may include one or more dielectric layers interleaved with one or more layers of conductive wiring and vias, as is commonly understood by those skilled in the art. The optional RDL 212 is depicted as white in some horizontal lines. Signal communication between the solder attach component 208, the semiconductor die 202, and both and among the base die 206 may employ the optional RDL 212 in embodiments implementing it.

[0027] The stacking capability of the embodiments advantageously reduces the size / area of the required base die 206, reduces interconnect length and pitch, and improves performance. Embodiments can be identified by visual inspection to observe the stacking of the semiconductor die and the solder attach component, and / or to discover the HBM stacked on and soldered to the HBI complex.

[0028] To achieve a planar top surface of the multi-die assembly 200, a fill material is employed. In various embodiments, the fill material includes multiple sheets of silicon referred to as structural silicon 240, which are attached to the upper surface of the semiconductor die 202 (and die 220, when present) using a layer of solder bumps 216. Each sheet of structural silicon 240 can be a dummy or passive sheet of silicon, i.e., one in which there are no transistors or metal wires. In other embodiments, the fill material is alternatively a metal block (e.g., copper or aluminum) to enhance heat removal from the die 202 and component 208. In a cross-sectional image of the device multi-die assembly 200, the fill material can be found at the periphery of the solder attach die 208 and above the semiconductor die 202. The solder bumps 216 can be found above the upper surface of the semiconductor die 202 and below the fill material. In a top view, the surface area of the solder attach die 208 is smaller than the surface area of the semiconductor die 202, and outside the solder attach die 208, the upper surface of the semiconductor die 202 is covered with a layer of solder bumps 216 and a layer including the fill material. When implemented, the optional RDL 212 extends across the entire upper surface of one or more semiconductor dies 202 / 220 under the layer of solder bumps 216. Thus, the multi-die assembly 200 is a device showing an exemplary architecture for hybrid solder and solderless die stacking.

[0029] In the completed multi-die assembly / device, an oxide or other dielectric 214 may be present around the periphery of the semiconductor die 202 / 220. A molding compound 218 may enclose or surround the multi-die assembly on the base die 206 (e.g., around the components (202, 208, 220)), and the package side bumps 238 may be soldered to an organic substrate printed circuit board in a device or more complex system.

[0030] Figure 3 and Figure 4 illustrates additional exemplary multi-die component solutions for hybrid solder and solderless die stacks that can be implemented in various packages and devices. Thermal, electrical, and design considerations can inform the architectural decisions between the Figure 2 , Figure 3 and Figure 4 embodiments. When comparing Figure 2 with Figure 3 and Figure 4 , the following objects are similar: semiconductor dies 202 / 302 / 402, base dies 206 / 306 / 406, solder attachment components (208 / 308 / 408), and solder bump regions 210 / 310 / 410; in addition, the hybrid bonding indicated by HBI 207 / 307 / 407 (i.e., regions 209 / 309 / 409 in the first semiconductor die 202 / 302 / 402) is where the upper surface is configured with through-silicon vias (TSVs) above a suitable die-to-die physical interface (D2D PHY), as shown; the vertical double arrows indicate the presence of an operating circuit path for signals traveling from the base die 206 / 306 / 406 through the semiconductor die 202 / 302 / 402 to the solder attachment component 208 / 308 / 408, optional redistribution layer (RDL) 212 / 312 / 412, solder bumps 216 / 316 / 416, oxides 214 / 314 / 414, fill material, mold 218 / 318 / 418, and package side bumps 238 / 338 / 448.

[0031] In Figure 3 , in embodiment 300, the solder attachment component 308 can represent one or more stacked HBMs and / or system-on-chips (SOCs) in a 3D die complex, as shown. In an embodiment, the semiconductor die 302 is active, and the semiconductor die 320 is passive. In another embodiment, the semiconductor die 302 is passive.

[0032] In Figure 4 the variant shown, i.e., embodiment 400, the passive semiconductor die 420 can utilize through-dielectric vias (TDVs) that pass through the oxide 414 layer of the die complex and land on pads on the base die 406 (arrow 450 indicates that the TDV has a path to the upper surface of the base die 408, where each TDV lands on a corresponding pad of the base die 408). The pitch conversion from the TDV to the high-density HBM microbump pattern can be done on the RDL 416.

[0033] As Figure 4As shown, any of the embodiments of devices 200, 300, and 400 can be further assembled onto an organic substrate or printed circuit board (PCB) 422 (e.g., see Figure 10 , circuit board 1002) in a package or device. One or more additional integrated circuit (IC) dies can also be attached to the organic substrate / PCB / circuit board 1002, and the entire silicon complex can be a hermetic seal with a molded or polymeric underfill material. Other hermetic seals can include dielectric materials, metals, ceramics, plastics, or combinations thereof. Additionally, a thermal management solution (not shown) including cooling components such as vapor chambers, heat pipes, heat sinks, or liquid-cooled cold plates can be attached to the multi-die package. As part of the thermal management solution, a thermal interface material (TIM) can be located on top of the die. The TIM can be any suitable material, such as a silver particle-filled thermal compound, thermal grease, phase change material, indium foil, or graphite sheet. The thermal management solution can be a conformal solution that accommodates the height differences of the integrated circuit dies that the thermal management solution cools. For example, the thermal management solution can include a substantially planar cooling component having TIMs of different thicknesses between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar, and the profile of the cooling component can vary with the thickness of the integrated circuit die that the cooling component cools. In such an embodiment, the TIM can have a substantially uniform thickness between the cooling component and the integrated circuit die of different thicknesses. The thermal management solution can also include an integrated heat sink.

[0034] Figure 5 is a method for hybrid solder and solderless die stacking according to embodiments described herein, and Figure 6 provides an image supporting Figure 5 the tasks described in. At 502, one or more semiconductor dies (602, 620) are hybrid bonded 607 to a base die 606, creating an HBI complex 600. As described above, semiconductor die 602 has TSVs and D2DPHYs. At 504, the gaps between the semiconductor dies on the base die 606 are filled with an oxide 614 or other dielectric. The oxide 614 can include silicon dioxide or an organic mold. Then, referring to embodiment 630, the oxide 614 is polished to a planarized surface 632, exposing the TSVs (and / or TDVs, depending on the embodiment). At 506, one or more optional RDLs 612 can be implemented as one or more layers covering embodiment 630, creating embodiment 650. The RDL 612 can remedy misalignment between the solder bump locations on the solder attachment components and the TSVs in the semiconductor die 602. The RDL 612 can also allow for fan-in or fan-out of signals in the conductive traces.

[0035] At 508, solder attachment component 608 is soldered to embodiment 650 via solder bumps 610, creating a hybrid solder and solderless stacked die complex. At 508, gap 672 is identified and filled. Gaps appear when the surface area of semiconductor die 602 / 620 and / or base die 606 is greater than the surface area of solder attachment component 608. The gap can be filled by attaching a filler material (structural silicon or a metal block with solder bumps 616). At 510, embodiment 670 can be molded and subjected to backside grinding, and at 512, the embodiment can optionally have package side bumps added and can be further attached to an organic substrate or a printed circuit board (PCB).

[0036] Embodiment 670 can further be used in microelectronic components such as Figure 10 shown and / or in devices such as Figure 11 shown.

[0037] Thus, methods and architectures for hybrid solder and solderless die stacking have been described. The following description and associated figures provide more details for the components cited above.

[0038] Figure 7 is a top view of wafer 700 and die 702 that can be included in any embodiment disclosed herein. Wafer 700 can be composed of semiconductor material and can include one or more die 702 formed on the surface of wafer 700. After the fabrication of integrated circuit components on wafer 700 is complete, wafer 700 can undergo a singulation process, where die 702 are separated from each other to provide discrete "chips", or are designated as integrated circuit components for packaging. Each die 702 that includes integrated circuit components can include one or more transistors (e.g., some of the transistors 840 discussed below Figure 8 , support circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 700 or die 702 can include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Additionally, multiple devices can be combined on a single die 702. For example, a memory array formed by multiple memory devices can be formed on the same die as a processor unit (e.g., Figure 11on the same die 702 as the processor unit 1102) or other logic configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, die 702 may be attached to a wafer 700 that includes other dies, and then the wafer 700 is singulated, and this manufacturing process is referred to as die-to-wafer assembly technology.

[0039] Figure 8 is a cross-sectional side view of an integrated circuit 800 that may be included in any embodiment disclosed herein. One or more of the integrated circuits 800 may be included in one or more dies 702 ( Figure 7 ). The integrated circuit 800 may be formed on a die substrate 802 (e.g., Figure 7 of the wafer 700), and may be included in a die (e.g., Figure 7 of the die 702).

[0040] The die substrate 802 may be a semiconductor substrate composed of a semiconductor material system, and the semiconductor material system includes, for example, an n-type or p-type material system (or a combination of both). The die substrate 802 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials that may or may not be combined with silicon may be used to form the die substrate 802, and the alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 802. Although several examples of materials that may form the die substrate 802 are described herein, any material that can be used as a substrate for the integrated circuit 800 may be used. The die substrate 802 may be a portion of a singulated die (e.g., Figure 7 of the die 702) or a wafer (e.g., Figure 7 of the wafer 700).

[0041] The integrated circuit 800 may include one or more device layers 804 disposed on the die substrate 802. The device layer 804 may include features of one or more transistors 840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 802. The transistors 840 may include, for example, one or more source and / or drain (S / D) regions 820, a gate 822 for controlling the current flow between the S / D regions 820, and one or more S / D contacts 824 for routing electrical signals to / from the S / D regions 820.

[0042] The gate 822 can be formed of at least two layers, namely a gate dielectric and a gate electrode. The gate dielectric can include a single layer or a stack of layers. One or more layers can include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate oxide, barium titanate oxide, strontium titanate oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process can be performed on the gate dielectric to improve its quality.

[0043] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 840 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode can include a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, can be included for other purposes.

[0044] For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0045] In some embodiments, when viewed as a cross-section of the transistor 840 along the source-channel-drain direction, the gate electrode can include a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the die substrate 802 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 802. In other embodiments, at least one of the metal layers forming the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the die substrate 802 and does not include sidewall portions that are substantially perpendicular to the top surface of the die substrate 802. In other embodiments, the gate electrode can include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0046] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0047] S / D regions 820 may be formed within the die substrate 802 adjacent to the gates 822 of respective transistors 840. For example, an implantation / diffusion process or an etching / deposition process may be used to form the S / D regions 820. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 802 to form the S / D regions 820. An annealing process to activate the dopants and further diffuse them into the die substrate 802 may follow the ion implantation process. In the latter process, the die substrate 802 may first be etched to form a recess at the location of the S / D regions 820. Then an epitaxial deposition process may be performed to fill the recess with a material for fabricating the S / D regions 820. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to fabricate the S / D regions 820. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form the S / D regions 820. In additional embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 820.

[0048] Electrical signals such as power and / or input / output (I / O) signals may be routed to and / or from devices (e.g., transistors 840) of the device layer 804 through one or more interconnect layers (shown as interconnect layers 806 - 810 in Figure 8 ). For example, the conductive features (e.g., gates 822 and S / D contacts 824) of the device layer 804 may be electrically coupled to the interconnect structures 828 of the interconnect layers 806 - 810. One or more interconnect layers 806 - 810 may form the metallization stack (also referred to as the "ILD stack") 819 of the integrated circuit 800.

[0049] Interconnect structures 828 may be arranged within the interconnect layers 806 - 810 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Figure 8 the specific configuration of the interconnect structures 828 depicted in Figure 8A specific number of interconnect layers 806 - 810 are depicted, but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than the depicted interconnect layers.

[0050] In some embodiments, the interconnect structure 828 may include lines 828a and / or vias 828b filled with a conductive material such as metal. The lines 828a may be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of the die substrate 802 on which the device layer 804 is formed. For example, the lines 828a may route electrical signals in a direction in and out of the page and / or in a cross - page direction. The vias 828b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 802 on which the device layer 804 is formed. In some embodiments, the vias 828b may electrically couple the lines 828a of different interconnect layers 806 - 810 together.

[0051] As Figure 8 shown, the interconnect layers 806 - 810 may include dielectric material 826 disposed between the interconnect structures 828. In some embodiments, the dielectric material 826 between the interconnect structures 828 in different interconnect layers among the interconnect layers 806 - 810 may have different compositions; in other embodiments, the compositions of the dielectric material 826 between different interconnect layers 806 - 810 may be the same. The device layer 804 may also include dielectric material 826 disposed between the transistors 840 and the bottom layer of the metallization stack. The dielectric material 826 included in the device layer 804 may have a different composition from the dielectric material 826 included in the interconnect layers 806 - 810; in other embodiments, the composition of the dielectric material 826 in the device layer 804 may be the same as the dielectric material 826 included in any one of the interconnect layers 806 - 810.

[0052] The first interconnect layer 806 (referred to as metal 1 or "M1") may be directly formed on the device layer 804. In some embodiments, as shown, the first interconnect layer 806 may include lines 828a and / or vias 828b. The lines 828a of the first interconnect layer 806 may be coupled to the contacts (e.g., S / D contacts 824) of the device layer 804. The vias 828b of the first interconnect layer 806 may be coupled to the lines 828a of the second interconnect layer 808.

[0053] The second interconnect layer 808 (referred to as Metal 2 or "M2") can be formed directly on the first interconnect layer 806. In some embodiments, the second interconnect layer 808 can include vias 828b to couple the lines 828a of the second interconnect layer 808 to the lines 828a of the third interconnect layer 810. Although, for clarity, the lines 828a and vias 828b are depicted structurally as lines within the respective interconnect layers, in some embodiments, the lines 828a and vias 828b can be continuous structurally and / or materially (e.g., filled simultaneously during a dual-damascene process).

[0054] According to similar techniques and configurations described in connection with the second interconnect layer 808 or the first interconnect layer 806, a third interconnect layer 810 (referred to as Metal 3 or "M3") (and additional interconnect layers as needed) can be formed continuously on the second interconnect layer 808. In some embodiments, the interconnect layers in the metallization stack 819 that are "higher" (i.e., further from the device layer 804) in the integrated circuit 800 can be thicker than the lower interconnect layers in the metallization stack 819, where the lines 828a and vias 828b in the higher interconnect layers are thicker than the lines 828a and vias 828b in the lower interconnect layers.

[0055] The integrated circuit 800 can include a solder resist material 834 (e.g., polyimide or a similar material) and one or more conductive contacts 836 formed on the interconnect layers 806 - 810. In Figure 8 , the conductive contacts 836 are shown taking the form of bond pads. The conductive contacts 836 can be electrically coupled to the interconnect structure 828 and are configured to route electrical signals of transistors (single or multiple) 840 to external devices. For example, a solder bond can be formed on one or more of the conductive contacts 836 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit 800 to another component (e.g., a printed circuit board). The integrated circuit 800 can include additional or alternative structures for routing electrical signals from the interconnect layers 806 - 810; for example, the conductive contacts 836 can include other similar features (e.g., pillars) for routing electrical signals to external components.

[0056] In some embodiments where the integrated circuit 800 is a double-sided die, the integrated circuit 800 can include another metallization stack (not shown) on the opposite side of the device layer (single or multiple) 804. This metallization stack can include multiple interconnect layers as discussed above with reference to the interconnect layers 806 - 810 to provide a conductive path (e.g., including conductive lines and vias) between the device layer (single or multiple) 804 and additional conductive contacts (not shown) on the side of the integrated circuit 800 opposite the conductive contacts 836.

[0057] In other embodiments where integrated circuit 800 is a double-sided die, integrated circuit 800 may include one or more through-silicon vias (TSVs) that pass through die substrate 802; these TSVs may contact the device layer(s) 804 and may provide a conductive path between the device layer(s) 804 and additional conductive contacts (not shown) on the side of integrated circuit 800 opposite conductive contacts 836. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from conductive contacts on the side of integrated circuit 800 opposite conductive contacts 836 to transistors 840 and any other components integrated into the die of integrated circuit 800, and metallization stack 819 may be used to route I / O signals from conductive contacts 836 to transistors 840 and any other components integrated into the die of integrated circuit 800.

[0058] Multiple integrated circuits 800 may be stacked using one or more TSVs in respective stacked devices, which provide connections from one of the devices to any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM dies may provide connections between the respective HBMs and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0059] Figures 9A to 9D are simplified perspective views of an exemplary planar transistor, FinFET transistor, all-around gate transistor, and stacked all-around gate transistor. Figures 9A to 9D The transistors shown are formed on a substrate 916 having a surface 908. Isolation regions 914 separate the source and drain regions of the transistors from other transistors and the bulk region 918 of substrate 916.

[0060] Figure 9A is a perspective view of an exemplary planar transistor 900 that includes a gate 902 that controls the flow of current between source region 904 and drain region 906. Transistor 900 is planar because source region 904 and drain region 906 are planar relative to substrate surface 908.

[0061] Figure 9BPerspective view of an example FinFET transistor 920 including a gate 922 that controls current flow between a source region 924 and a drain region 926. Transistor 920 is non-planar because source region 924 and drain region 926 include "fins" that extend upward from substrate surface 908. Since gate 922 surrounds three sides of a semiconductor fin that extends from source region 924 to drain region 926, transistor 920 can be considered a triple-gate transistor. Figure 9B One S / D fin extending through gate 922 is shown, but multiple S / D fins can extend through the gate of a FinFET transistor.

[0062] Figure 9C Perspective view of a gate-all-around (GAA) transistor 940 including a gate 942 that controls current flow between a source region 944 and a drain region 946. Transistor 940 is non-planar because source region 944 and drain region 946 are elevated from substrate surface 908.

[0063] Figure 9D Perspective view of a GAA transistor 960 including a gate 962 that controls current flow between multiple elevated source regions 964 and multiple elevated drain regions 966. Transistor 960 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 940 and 960 are considered gate-all-around transistors because the gate surrounds all sides of a semiconductor portion that extends from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 948 and 968 for transistors 940 and 960, respectively), transistors 940 and 960 can alternatively be referred to as nanowire transistors, nanosheet transistors, or nanoribbon transistors.

[0064] Figure 10 Cross-sectional side view of a microelectronic component 1000 that can include any of the embodiments disclosed herein. Microelectronic component 1000 includes a plurality of integrated circuit components disposed on a circuit board 1002, which can be a motherboard, a system board, a main board, etc. Microelectronic component 1000 can include components disposed on a first side 1040 of circuit board 1002 and on an opposite second side 1042 of circuit board 1002; generally, components can be disposed on one or both of sides 1040 and 1042.

[0065] In some embodiments, the circuit board 1002 can be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 1002. In other embodiments, the circuit board 1002 can be a non-PCB substrate. Figure 10 The microelectronic assembly 1000 shown in includes an on-interposer package structure 1036 coupled to the first surface 1040 of the circuit board 1002 by a coupling component 1016. The coupling component 1016 can electrically and mechanically couple the on-interposer package structure 1036 to the circuit board 1002 and can include solder balls (as Figure 10 shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female parts of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0066] The on-interposer package structure 1036 can include an integrated circuit component 1020 coupled to the interposer 1004 by a coupling component 1018. The coupling component 1018 can take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1016. Although a single integrated circuit component 1020 is shown in Figure 10 , multiple integrated circuit components can be coupled to the interposer 1004; in fact, additional interposers can be coupled to the interposer 1004. The interposer 1004 can provide an intermediate substrate for bridging the circuit board 1002 and the integrated circuit component 1020.

[0067] The integrated circuit component 1020 can be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (e.g., Figure 7 die 702 of Figure 8 integrated circuit 800) and / or one or more other suitable components.

[0068] The unpackaged integrated circuit component 1020 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1004. In embodiments where the integrated circuit component 1020 includes multiple integrated circuit dies, the dies can be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 1020 can also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These individual integrated circuit dies can be referred to as "dielets". In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnection between the dies can be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination thereof. The packaged multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0069] The interposer 1004 can extend the connections to a wider pitch or reroute the connections to different connections. For example, the interposer 1004 can couple the integrated circuit component 1020 to a set of ball grid array (BGA) conductive contacts of a coupling component 1016 for coupling to the circuit board 1002. In Figure 10 the illustrated embodiment, the integrated circuit component 1020 and the circuit board 1002 are attached to opposite sides of the interposer 1004; in other embodiments, the integrated circuit component 1020 and the circuit board 1002 can be attached to the same side of the interposer 1004. In some embodiments, three or more components can be interconnected through the interposer 1004.

[0070] In some embodiments, the interposer 1004 can be formed as a PCB, including a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1004 can be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1004 can be formed of alternative rigid or flexible materials, which can include the same materials used in semiconductor substrates as described above, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1004 can include metal interconnects 1008 and vias 1010, including but not limited to through vias 1010-1 (which extend from the first face 1050 of the interposer 1004 to the second face 1054 of the interposer 1004), blind vias 1010-2 (which extend from the first face 1050 or the second face 1054 of the interposer 1004 to an internal metal layer), and buried vias 1010-3 (which connect internal metal layers).

[0071] In some embodiments, the interposer 1004 can include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect connections on the first face of the silicon interposer to the opposite second face of the silicon interposer. In some embodiments, the interposer 1004 including the silicon interposer can further include one or more wiring layers to route connections on the first face of the interposer 1004 to the opposite second face of the interposer 1004.

[0072] The interposer 1004 can further include embedded devices 1014, including passive devices and active devices. Such devices can include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 1004. The on-interposer package structure 1036 can take the form of any on-interposer package structure known in the art.

[0073] The integrated circuit assembly 1000 can include an integrated circuit component 1024 coupled to the first face 1040 of the circuit board 1002 through a coupling component 1022. The coupling component 1022 can take the form of any of the embodiments discussed above with reference to the coupling component 1016, and the integrated circuit component 1024 can take the form of any of the embodiments discussed above with reference to the integrated circuit component 1020.

[0074] Figure 10The integrated circuit assembly 1000 shown includes a stacked package structure 1034 coupled to the second side 1042 of the circuit board 1002 by a coupling member 1028. The stacked package structure 1034 may include an integrated circuit component 1026 and an integrated circuit component 1032 coupled together by a coupling member 1030 such that the integrated circuit component 1026 is disposed between the circuit board 1002 and the integrated circuit component 1032. The coupling members 1028 and 1030 may take the form of any of the embodiments of the coupling member 1016 discussed above, and the integrated circuit components 1026 and 1032 may take the form of any of the embodiments of the integrated circuit component 1020 discussed above. The stacked package structure 1034 may be configured according to any stacked package structure known in the art.

[0075] Figure 11 is a block diagram of an example electrical device 1100 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 1100 may include one or more of the disclosed embodiments, semiconductor components, package components, microelectronic component 1000, integrated circuit component 1020, integrated circuit 800, integrated circuit die 702, or structures disclosed herein. A plurality of components are Figure 11 shown as being included in the electrical device 1100, but any one or more of these components may be omitted or replicated depending on the application requirements. In some embodiments, some or all of the components included in the electrical device 1100 may be attached to one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-chip (SoC) die. In various embodiments, the electrical device 3000 is encapsulated by or integrated with a housing.

[0076] Additionally, in various embodiments, the electrical device 1100 may not include Figure 11 one or more of the components shown, but the electrical device 1100 may include interface circuitry for coupling to one or more components. For example, the electrical device 1100 may not include a display device 1106, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1106 may be coupled. In another set of examples, the electrical device 1100 may not include an audio input device 1124 or an audio output device 1108, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1124 or the audio output device 1108 may be coupled.

[0077] The electrical device 1100 may include one or more processor units 1102 (e.g., one or more processing units). As used herein, the terms "processor unit", "processing unit", or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processor unit 1102 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller crypto processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit may be referred to as an XPU (or xPU).

[0078] The electrical device 1100 may include a memory 1104, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid state memory, and / or hard disk drives. In some embodiments, the memory 1104 may include memory located on the same integrated circuit die as the processor unit 1102. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0079] In some embodiments, the electrical device 1100 may include one or more processor units 1102 that are heterogeneous or asymmetric with another processor unit 1102 in the electrical device 1100. There may be a variety of differences between the processor units 1102 in the system, according to a series of quality factors including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1102 in the electrical device 1100.

[0080] In some embodiments, the electrical device 1100 may include a communication component 1112 (e.g., one or more communication components). For example, the communication component 1112 may manage wireless communications for transmitting data to and from the electrical device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data using modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0081] The communication component 1112 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project, and any revisions, updates, and / or modifications (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products undergoing compliance and interoperability testing for the IEEE 802.16 standard. The communication component 1112 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication component 1112 may operate according to Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1112 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. In other embodiments, the communication component 1112 may operate according to other wireless protocols. The electrical device 1100 may include an antenna 1122 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0082] In some embodiments, the communication component 1112 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, the communication component 1112 may include multiple communication components. For example, a first communication component 1112 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1112 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1112 may be dedicated to wireless communications, and the second communication component 1112 may be dedicated to wired communications.

[0083] The electrical device 1100 may include a power source, such as a battery / power circuitry 1114. The battery / power circuitry 1114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1100 to an energy source (e.g., AC line power) that is separate from the electrical device 1100.

[0084] The electrical device 1100 may include a display device 1106 (or corresponding interface circuitry, as described above). The display device 1106 may include one or more embedded or externally connected visual indicators, either wired or wireless, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0085] The electrical device 1100 may include an audio output device 1108 (or corresponding interface circuitry, as described above). The audio output device 1108 may include any embedded or externally connected device, either wired or wireless, that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0086] The electrical device 1100 may include an audio input device 1124 (or corresponding interface circuitry, as described above). The audio input device 1124 may include any embedded or externally connected device, either wired or wireless, that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output). The electrical device 1100 may include a Global Navigation Satellite System (GNSS) device 1118 (or corresponding interface circuitry, as described above), such as a Global Positioning System (GPS) device. The GNSS device 1118 may communicate with a satellite-based system and may determine the geographical location of the electrical device 1100 based on information received from one or more GNSS satellites, as is known in the art.

[0087] The electrical device 1100 may include another output device 1110 (or a corresponding interface circuitry, as described above). Examples of other output devices 1110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0088] The electrical device 1100 may include another input device 1120 (or a corresponding interface circuitry, as described above). Examples of other input devices 1120 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a single field-of-view or stereo camera), a trackball, a touchpad, a touch tablet, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a skin conductance response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0089] The electrical device 1100 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smartphone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a two-in-one convertible computer, a portable all-in-one computer, a netbook computer, a ultrabook computer, a personal digital assistant (PDA), a ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, a tray, or a chassis computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart home appliance, a consumer electronics or equipment, a manufacturing equipment). In some embodiments, the electrical device 1100 may be any other electronic device that processes data. In some embodiments, the electrical device 1100 may include a plurality of discrete physical components. Given the range of devices that the electrical device 1100 may embody in various embodiments, in some embodiments, the electrical device 1100 may be referred to as a computing device or a computing system.

[0090] Although at least one embodiment has been presented in the foregoing detailed description, it should be understood that there are numerous variations. It should also be understood that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Instead, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the disclosed embodiments. Various changes may be made to the functions and arrangements of the elements without departing from the scope of the present disclosure as set forth in the appended claims and their legal equivalents.

[0091] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other, with no layer or component therebetween. For example, layer X adjacent to layer Y refers to the layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase "located on" (in an alternative, "located under", "located over / above", or "located adjacent to", in the context where a first layer or component is located on a second layer or component) includes (i) configurations where the first layer or component is directly physically attached to the second layer (i.e., adjacent), and (ii) components and configurations where the first layer or component is attached (e.g., coupled) to the second layer or component via one or more intervening layers or components.

[0092] Similarly, the word "covered" is used herein to denote a spatial relationship, being the past tense of cover, having been distributed over or superimposed on an object. Covering does not imply any particular process for placement. If a first layer is covered on a second layer, then the first layer is also "located on" the second layer, as described above.

[0093] A term or value modified by the word "substantially" includes arrangements, orientations, spacings, or positions that differ from the meaning of the unmodified term or value by plus or minus 20%. A term or value modified by the word "about" includes values that are less than or equal to 10% of the term or value to values that are greater than or equal to 10% of the term or value.

[0094] As used herein, the term "electronic component" may refer to an active electronic circuit (e.g., a processing unit, a memory, a storage device, a FET) or a passive electronic circuit (e.g., a resistor, an inductor, a capacitor).

[0095] As used herein, the term "integrated circuit component" may refer to an electronic component configured on a semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any of the computing system components described or referenced herein or any other computing system components, such as a processor unit (e.g., a system-on-chip (SoC), a processor core, a graphics processing unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0096] Non-limiting examples of unpackaged integrated circuit components include a single monolithic integrated circuit die (also referred to herein simply as a "die"); the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may enable the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0097] Non-limiting examples of packaged integrated circuit components include one or more integrated circuit dies mounted on a package substrate, where the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. Typically, the housing includes an integrated heat sink (IHS); a packaged integrated circuit component typically has bumps, leads, or pins attached to the package substrate (either directly or via wires attaching the bumps, leads, or pins to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or backplane) or another component.

[0098] As used herein, phrases such as "an embodiment", "various embodiments", "some embodiments", etc. indicate that some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third", etc. describe common objects and indicate different instances of the referenced similar objects; unless explicitly stated, it does not imply a given sequence in time, space, ranking, or any other way. In patent application terminology, "connected" indicates elements that are in direct physical or electrical contact with each other, and "coupled" indicates elements that cooperate or interact with each other, and the coupled elements may or may not be in direct physical or electrical contact. Additionally, the terms "comprising", "including", "having", etc. are used synonymously to denote non-exclusive inclusion.

[0099] As used in this application and the claims, a list of items joined by the term "at least one of..." or the term "one or more of..." can represent any combination of the listed items. For example, the phrase "at least one of A, B, or C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C.

[0100] As used in this application and the claims, the phrase "each" or "respective" followed by a list of items described or stated as having a property, characteristic, etc. means that all items in the list have the stated or described property, characteristic, etc. For example, the phrase "each of A, B, or C includes a sidewall" or "respective of A, B, or C includes a sidewall" means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0101] The operating theories, scientific principles, or other theoretical descriptions presented herein with reference to the devices or methods of the present disclosure have been provided for purposes of better understanding and are not intended to limit the scope. The devices and methods in the appended claims are not limited to those that operate in the manner described by such operating theories.

[0102] The following examples relate to additional embodiments of the technology disclosed herein.

[0103] Example

[0104] Example 1 is a device including: a first die; a second die including an integrated circuit, the second die being on and hybrid bonded to the first die; wherein the second die further includes an upper surface and a plurality of through-silicon vias (TSVs) exposed at the upper surface; and a third die soldered to the upper surface of the second die.

[0105] Example 2 includes the subject matter of Example 1 and further includes hybrid bond interconnects in the second die and solder bumps on the third die; and wherein the second die further includes a die-to-die physical interface (D2D PHY) between the hybrid bond interconnects and the solder bumps.

[0106] Example 3 includes the subject matter of Example 1 or Example 2, wherein the first die includes active circuitry.

[0107] Example 4 includes the subject matter of Example 1 or Example 2, wherein the first die is passive.

[0108] Example 5 includes the subject matter described in any of Examples 1-4, and further includes a redistribution layer (RDL) between the third die and the upper surface of the second die.

[0109] Example 6 includes the subject matter described in any of Examples 1-5, and further includes a filler material at the periphery of the third die and over the second die.

[0110] Example 7 includes the subject matter described in Example 6, wherein the filler material includes silicon, and further includes a molding compound between the silicon and the third die.

[0111] Example 8 includes the subject matter described in Example 1, wherein the filler material includes metal, and further includes one or more solder bumps between the filler material and the second die.

[0112] Example 9 includes the subject matter described in any of Examples 1-8, wherein the third die is a dynamic random access memory (DRAM) component.

[0113] Example 10 includes the subject matter described in any of Examples 1-8, wherein the third die is a high bandwidth memory (HBM) component.

[0114] Example 11 is a multi-die assembly, including: a first die including an upper surface configured for hybrid bonding interconnection; a semiconductor die on the upper surface of the first die and hybrid bonded to the first die; and a solder attachment component on top of the semiconductor die and attached to the semiconductor die via solder bumps; wherein the semiconductor die includes a plurality of through-silicon vias (TSVs), and each TSV is attached to a corresponding solder bump.

[0115] Example 12 includes the subject matter described in Example 11, wherein the semiconductor die further includes a die-to-die physical interface (D2D PHY) between the hybrid bonding interconnection and the solder bumps.

[0116] Example 13 includes the subject matter described in Example 11, wherein the surface area of the solder attachment component is smaller than the surface area of the semiconductor die, and further includes: a solder bump layer covering the upper surface of the semiconductor die outside the solder attachment component; and a filler material covering the solder bump layer.

[0117] Example 14 includes the subject matter described in Example 13, and further includes: a second die on the upper surface of the first die side by side with the semiconductor die and hybrid bonded to the first die.

[0118] Example 15 includes the subject matter described in Example 14, and further includes: the solder bump layer also covers the upper surface of the second die; and the filling material also covers the solder bump layer covering the second die.

[0119] Example 16 includes the subject matter described in Example 11, and further includes: a second die, disposed side by side with the semiconductor die on the upper surface of the first die and hybrid bonded to the first die, wherein the second die includes a plurality of through-dielectric vias (TDVs) extending through the second die.

[0120] Example 17 includes the subject matter described in Example 16, and further includes: a solder bump layer, covering the upper surface of the semiconductor die outside the solder attachment component and covering the upper surface of the second die; and a filling material, covering the solder bump layer covering the second die.

[0121] Example 18 is a microelectronic component including the subject matter described in Example 15, and further includes a molding compound surrounding the multi-die assembly.

[0122] Example 19 is a method, including: stacking active semiconductor dies on a base die; hybrid bonding the active semiconductor dies to the base die to create a hybrid bonded interconnect (HBI) complex; stacking high bandwidth memory (HBM) on top of the semiconductor dies; soldering the HBM to the semiconductor dies to create a hybrid solder and solderless stacked die complex; and filling the gaps in the hybrid solder and solderless stacked die complex.

[0123] Example 20 includes the subject matter described in Example 19, and further includes: covering the hybrid solder and solderless stacked die complex with a molding compound.

Claims

1. A device comprising: a first die including a first surface having a first insulating material and metal contacts therein; a second die comprising an integrated circuit and a lower surface comprising a second insulating material having a plurality of conductive contacts therein; The second die is on the first die, each of the plurality of conductive contacts is directly bonded to a corresponding metal contact on the first surface, and the first insulating material is directly bonded to the second insulating material; wherein the second die further comprises an upper surface and a plurality of through silicon vias (TSVs) exposed at the upper surface; as well as A third die is on the upper surface of the second die, the third die being attached to the second die via the plurality of TSV solders.

2. The device according to claim 1, wherein: The plurality of conductive contacts are hybrid bonded conductive contacts and further include: solder bumps on the third die; Wherein, the second die further includes a die-to-die physical interface (D2D PHY) between the hybrid bonded conductive contacts and the solder bumps.

3. The device according to claim 1 or claim 2, wherein: The first die includes active circuitry.

4. The device according to claim 1 or claim 2, wherein: The first die is passive. 5 . The apparatus of claim 1 , further comprising a redistribution layer (RDL) between the third die and the upper surface of the second die. 6 . The apparatus of claim 1 , further comprising a fill material at a periphery of the third die and over the second die.

7. The device according to claim 6, wherein: The fill material includes silicon and further includes a molding compound between the silicon and the third die.

8. The apparatus of claim 7, further comprising one or more additional solder bumps between the silicon and the second die.

9. The device according to claim 1, wherein: The third die is a dynamic random access memory (DRAM) component.

10. The device according to claim 1, wherein: The third die is a high bandwidth memory (HBM) component.

11. A multi-die assembly comprising: a first die including an upper surface configured as a first hybrid bonding interface; a semiconductor die on the upper surface of the first die, the semiconductor die having a second hybrid bonding interface; the first hybrid bonding interface is bonded to the second hybrid bonding interface; as well as a solder attach component located on top of the semiconductor die and attached to the semiconductor die via solder bumps; The semiconductor die includes a plurality of through silicon vias (TSVs), and each TSV is attached to a corresponding solder bump.

12. The multi-die assembly of claim 11, wherein: The semiconductor die also includes a die-to-die physical interface (D2D PHY) between the second hybrid bonding interface and the solder bumps.

13. The multi-die assembly of claim 11, wherein: The solder attach feature has a surface area that is less than a surface area of ​​the semiconductor die, and further comprising: a solder bump layer overlying the upper surface of the semiconductor die outside of the solder attach feature; and A filling material covers the solder bump layer.

14. The multi-die assembly of claim 13, further comprising: A second die is juxtaposed with the semiconductor die on the upper surface of the first die and hybrid bonded to the first die.

15. The multi-die assembly of claim 14, further comprising: The solder bump layer also covers the upper surface of the second die; and The fill material also overlies the solder bump layer overlying the second die.

16. The multi-die assembly of claim 11, further comprising: A second die is juxtaposed with the semiconductor die on the upper surface of the first die and hybrid bonded to the first die, wherein the second die includes a plurality of through dielectric vias (TDVs) extending through the second die.

17. The multi-die assembly of claim 16, further comprising: a solder bump layer overlying the upper surface of the semiconductor die outside the solder attach feature and overlying an upper surface of the second die; as well as A filling material overlying the solder bump layer overlying the second die.

18. A microelectronic assembly comprising the multi-die assembly of claim 15, further comprising a molding compound surrounding the multi-die assembly.

19. A method comprising: stacking an active semiconductor die having a first hybrid bonding interface on a base die having a second hybrid bonding interface; bonding metal in the first hybrid bonding interface to metal in the second hybrid bonding interface; bonding the dielectric in the first hybrid bonding interface to the dielectric in the second hybrid bonding interface, thereby creating a hybrid bonded interconnect (HBI) composite; stacking a high bandwidth memory (HBM) on an upper surface of the active semiconductor die; as well as The HBM is soldered to the active semiconductor die, thereby creating a hybrid stacked die composite.

20. The method according to claim 19, further comprising: The hybrid stacked die composite is covered with a molding compound.

21. The method of claim 19 or claim 20, wherein: The base die includes active circuitry.

22. The method of claim 19, wherein: The upper surface of the active semiconductor die includes a region having a plurality of through-silicon vias (TSVs); and The HBM occupies the region and is electrically connected to the plurality of TSVs.

23. The method according to claim 22, wherein: Each TSV of the plurality of TSVs provides an electrical path to a die-to-die physical interface (D2D PHY) in the active semiconductor die.

24. The method according to claim 22 or claim 23, further comprising: A gap around the HBM on the upper surface of the active semiconductor die is filled with a structural silicon material or a structural metal material.

25. The method of claim 19 or claim 20, further comprising: Prior to stacking the high bandwidth memory (HBM) on the upper surface of the active semiconductor die, the upper surface of the active semiconductor die is covered with a redistribution layer.

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