A Control Method for a DC Solid-State Circuit Breaker with a Limited-Voltage Protection Circuit

Abstract

The present invention discloses a DC solid-state circuit breaker with a limited-voltage protection circuit and its control method, including a solid-state switch module; the solid-state switch module includes the same first sub-module and second sub-module, both of which include a SiC JFET device J, a capacitor C , C <subgt;gd< / subgt;, and C <subgt;gs< / subgt>, a comparator U , a MOSFET device Q, a resistor R <subgt;g< / subgt>, and a resistor r <subgt;a< / subgt> and r <subgt;b; R The first end of <subgt;g is used to receive a driving signal, R The second end of <subgt;g is connected to the C first end, C the second end of <subgt;gd, and C the first end of <subgt;gs and then connected to the gate of J; r The second end of <subgt;a and r the first end of <subgt;b are connected as a comparison voltage sampling point; r The first end of <subgt;a is connected to the C first end of <subgt;gd and the drain of J; r The second end of <subgt;b is connected to the C second end of <subgt;gs, the source of Q, and the source of J; C The second end is connected to the drain of Q; U The output end is connected to the gate of Q; U The positive input is the comparison voltage, and the negative input is the reference voltage; the source of J in the first sub-module is connected to the drain of J in the second sub-module.

Description

Technical Field

[0001] The present invention relates to the technical field of DC distribution system protection, and particularly relates to a DC solid-state circuit breaker with a voltage-limiting protection circuit and a control method thereof. Background Art

[0002] In recent years, DC microgrids have attracted much attention due to their ability to efficiently integrate distributed energy and energy storage units. However, the low-impedance characteristic of DC microgrids results in high short-circuit fault current amplitudes and fast rising speeds, making it difficult for traditional mechanical circuit breakers to meet the fast protection requirements of DC microgrids due to their millisecond-level turn-off delays. In contrast, the SSCB (Solid-State Circuit Breaker) based on power semiconductor devices has become an ideal solution due to its fast response and arc-free characteristics.

[0003] Currently, wide-bandgap semiconductors (such as SiC devices) are widely used in SSCBs due to their low conduction losses and high junction temperature tolerances. However, limited by manufacturing processes, the voltage withstand capabilities of commercial SiC discrete devices are insufficient, and the overall voltage withstand level needs to be improved through series connection. However, factors such as parasitic parameter differences between series devices can lead to voltage imbalance during the turn-off process, causing local overvoltage and seriously threatening device reliability. Existing passive voltage equalization schemes (such as RC buffer circuits) can alleviate some problems, but they are insufficient in adapting to the dynamic turn-off process and are difficult to effectively suppress transient overshoots.

[0004] Therefore, there is an urgent need for a new technical solution to solve the technical problem of how to limit the voltage overshoot of series switch devices. Summary of the Invention

[0005] The present invention provides a DC solid-state circuit breaker with a voltage-limiting protection circuit and a control method thereof to solve the technical problem of how to limit the voltage overshoot of series switch devices.

[0006] To achieve the above object, the present invention provides a DC solid-state circuit breaker with a voltage-limiting protection circuit, including a solid-state switch module;

[0007] The solid-state switch module includes a first sub-module and a second sub-module. The first sub-module and the second sub-module have the same structure and both include SiC JFET discrete devices , capacitors , and , comparators , low-voltage MOSFET devices , drive resistors , and sampling resistors , and ; The first end of is used to receive a drive signal, and the second end of The first end of and the second end of are connected to the first end of and then connected to the gate of The second end of and the first end of are connected as the sampling point of the comparison voltage; The first end of is connected to the drain of The second end of is connected to the second end of the source of and the source of The second end of is connected to the drain of The output end of is connected to the gate of The negative input of

[0008] is the comparison voltage, and the positive input is the preset reference voltage; In the first sub-module, the source of is connected to the drain of in the second sub-module; the DC bus current flows into from the drain of in the first sub-module and flows out from the source of

[0009] Preferably, it further includes a sampling module, an isolation module, an FPGA module and a driving module;

[0010] The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module; the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information.

[0011] Preferably, it further includes a switch protection module, and the switch protection module includes a metal oxide varistor and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel at both ends of the solid-state switch module.

[0012] The present invention also provides a control method for a DC solid-state circuit breaker with a voltage-limiting protection circuit. Based on the DC solid-state circuit breaker of the present invention, it includes:

[0013] When it is determined that a DC bus fault occurs, the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module, and control the SiC JFET discrete devices of the first sub-module and the second sub-module to turn off;

[0014] When an overvoltage situation occurs in the first sub-module or the second sub-module, the sub-module in which the overvoltage situation occurs is recorded as a faulty sub-module; the comparator of the faulty sub-module outputs a low level to control the low-voltage MOSFET device of the faulty sub-module to conduct. At this time, the capacitor in the faulty sub-module is connected to the gate and source of the SiC JFET discrete device .

[0015] Preferably, when there is no overvoltage situation in the solid-state switch module, the comparators of the first sub-module and the second sub-module both output a high level to control the low-voltage MOSFET devices of the first sub-module and the second sub-module to turn off, and the SiC JFET discrete devices of the first sub-module and the second sub-module both maintain a normal turn-off speed.

[0016] Preferably, when the DC solid-state circuit breaker is connected to the DC bus, it includes:

[0017] When there is a difference in the magnitudes between the driving resistors of the first sub-module and the second sub-module , it will cause an overvoltage situation in the sub-module with the smaller driving resistor, which becomes a faulty sub-module; the normal sub-module is recorded as the normal sub-module;

[0018] When the DC solid-state circuit breaker is connected to the DC bus, it includes seven consecutive stages in time:

[0019] Stage 1: When there is no fault in the DC bus, the DC solid-state circuit breaker does not operate;

[0020] Stage 2: When a fault occurs in the DC bus, the bus current starts to rise, and the DC solid-state circuit breaker does not operate;

[0021] Stage 3: When the bus current rises to a preset threshold, the SiC JFET discrete devices of the first sub-module and the second sub-module receive a turn-off signal, and the gate-source voltages of both start to drop;

[0022] Stage 4: The gate-source voltage of the SiC JFET discrete device of the faulty sub-module reaches the Miller platform voltage; the of the faulty sub-module stops reverse charging, starts charging, the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise;

[0023] Stage 5: The SiC JFET discrete device of the normal sub-module ​The gate-source voltage of the normal submodule reaches the Miller platform voltage; Stop reverse charging, Start charging, SiC JFET discrete device Start shutting down, and the comparison voltage starts to rise;

[0024] Stage 6: Faulty Submodule SiC JFET Discrete Device The Miller platform ends, the fault submodule Charging is completed. Start reverse charging;

[0025] Phase 7: Normal sub-module SiC JFET discrete devices The Miller platform ends, the normal submodule Charging is completed. Reverse charging starts; SiC JFET discrete devices of the faulty submodule and the normal submodule All continue to shut down, due to the driving resistance of the faulty submodule The smaller the voltage, the faster the shutdown speed, which causes the comparison voltage of the faulty submodule to be higher than the comparison voltage of the normal submodule, and then causes the comparison voltage of the faulty submodule to be higher than the preset reference voltage. Output low level, the capacitor Access to SiC JFET discrete devices Gate and source to mitigate failures in SiC JFET discrete devices in submodules The turn-off speed.

[0026] Preferably, stage three includes:

[0027] Since the SiC JFET discrete devices in the first submodule and the second submodule The gate-source voltage of the fault submodule has not reached the Miller platform voltage, so the DC solid-state circuit breaker has not yet shut off the fault current; the SiC JFET discrete devices in the fault submodule and the normal submodule The comparison voltage of the comparator is 0. The outputs are all high level, low voltage MOSFET devices All are turned off, capacitors and All through the corresponding drive resistor Reverse charging, according to the KVL law, exists:

[0028] ;

[0029] in, and Represent the driving resistance of the normal submodule and the faulty submodule respectively; and represent the capacitances of the normal sub-module and the faulty sub-module respectively ; and represent the gate-source voltages of the SiC JFET discrete devices in the normal sub-module and the faulty sub-module respectively, that is the voltages across and ; and represent the drive signals received by the drive resistors in the normal sub-module and the faulty sub-module respectively

[0030] Therefore, due to the smaller drive resistor of the faulty sub-module, the rate of decrease of the gate-source voltage of the faulty sub-module in stage three is greater than that of the normal sub-module

[0031] The present invention has the following beneficial effects:

[0032] For the DC solid-state circuit breaker with a voltage-limiting protection circuit of the present invention, when a short-circuit fault occurs, it can realize the connection and disconnection of the capacitor on the drive side of the switching device through a closed-loop control method, thereby adjusting the turn-off speed of the switching device, slowing down the voltage change rate of the device with a faster turn-off speed, and limiting the voltage overshoot of the switching device. By connecting SiC JFETs in series, the capacity, withstand voltage and power level of the DC solid-state circuit breaker are effectively improved. Compared with the topology structure adopting the passive voltage-limiting control method, the addition of active devices in the present invention greatly reduces the degree of voltage overshoot of the series switching devices. When the DC solid-state circuit breaker responds to a line short-circuit fault, it can timely cut off the short-circuit fault; and during the fault-cutting stage of the DC solid-state circuit breaker, if the device voltage has an overvoltage situation, it can timely adjust the voltage turn-off rate and limit the degree of uneven branch voltage

[0033] The control method of the DC solid-state circuit breaker with a voltage-limiting protection circuit of the present invention, based on the DC solid-state circuit breaker of the present invention, has the same beneficial effects as the method of the present invention

[0034] In addition to the purposes, features and advantages described above, the present invention has other purposes, features and advantages. The following will refer to the accompanying drawings to further elaborate on the present invention in detail Brief Description of the Drawings

[0035] The drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0036] Figure 1It is a schematic structural diagram of the solid-state switch module according to the preferred embodiment of the present invention.

[0037] Figure 2 It is a schematic structural diagram of the DC solid-state circuit breaker with a voltage-limiting protection circuit according to the preferred embodiment of the present invention.

[0038] Figure 3 It is a schematic diagram of the theoretical waveforms of the voltages on the capacitor and during the seven stages of the turn-off process according to the preferred embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the simulation circuit topology according to the preferred embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the simulation result diagram with voltage-limiting control according to the preferred embodiment of the present invention.

[0041] Figure 6 It is a schematic diagram of the simulation result diagram without voltage-limiting control according to the preferred embodiment of the present invention. Detailed implementation manners

[0042] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings. However, the present invention can be implemented in many different ways defined and covered by the claims.

[0043] Refer to Figure 1 , in the preferred embodiment of the present invention, a DC solid-state circuit breaker with a voltage-limiting protection circuit is provided, including a solid-state switch module;

[0044] The solid-state switch module includes a first sub-module and a second sub-module. The structures of the first sub-module and the second sub-module are the same, and both include SiC JFET discrete devices , capacitors and , comparators , low-voltage MOSFET devices , drive resistors , and sampling resistors and . Among Figure 1 the above devices, the sampling resistors and of the first sub-module and the second sub-module are and and and respectively; the remaining devices are all represented by subscript 1 from the first sub-module and all represented by subscript 2 from the second sub-module.

[0045] and are SiC JFET discrete devices respectively The parasitic capacitance between the internal gate-drain and gate-source. SiC JFET discrete device It also includes a capacitance between the drain and source inside .

[0046] The first end of [] is used to receive the drive signal, The second end of [] is connected to The first end of [], The second end of [], and After being connected to the first end of [], it is connected to the gate of []; The second end of [] and The first end of [] are connected as the sampling point of the comparison voltage; The first end of [] is connected to The first end of [], and The drain of []; The second end of [] is connected to The second end of [], The source of [], and The source of []; The second end of [] is connected to The drain of []; The output end of [] is connected to The gate of []; The negative input of [] is the comparison voltage, and the positive input is the preset reference voltage . Comparator is used to adjust the voltage drop rate across the gate-source of the SiC JFET discrete device , control the turn-off speed of the SiC JFET discrete device to limit the turn-off voltage overshoot.

[0047] In the preferred embodiment of the present invention, it is assumed that the first sub-module is a normal sub-module and the second sub-module is a faulty sub-module. In Figure 1 , represents the drive signal received by the drive resistor in the first sub-module, represents the drive signal received by the drive resistor in the second sub-module; represents the drain of the SiC JFET discrete device in the first sub-module, represents the source of the SiC JFET discrete device in the second sub-module; represents the comparison voltage of the first sub-module, represents the comparison voltage of the second sub-module.

[0048] In the first sub-module The source electrode is connected to the second sub-module of the drain; the DC bus current flows in from the drain of the first sub-module and flows out from the source electrode of the second sub-module .

[0049] See Figure 2 , in the preferred embodiment of the present invention, the DC solid-state circuit breaker further includes a sampling module, an isolation module, an FPGA module, a driving module, and a switch protection module.

[0050] The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module. The isolation module transmits information through optical fibers to prevent interference between strong and weak currents and ensure the safety of the device; the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information. The high-speed FPGA can improve the operation speed of the fault algorithm. The driving module has a negative voltage driving ability and can drive SiC JFET discrete devices well.

[0051] The switch protection module includes a metal oxide varistor (MOV) and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel across both ends of the solid-state switch module. The switch protection module is used to clamp the overvoltage of the device, protect the solid-state switch from damage by transient overvoltage, and slow down the dv / dt in the current turn-off process, and absorb the remaining energy in the line inductance.

[0052] In Figure 2 , represents the DC bus; represents the line current; represents the sampling point; represents the load; represents the metal oxide varistor; and represent the buffer absorption circuit.

[0053] The DC solid-state circuit breaker with a voltage-limiting protection circuit according to the present invention can, when a short-circuit fault occurs, realize the connection and disconnection of the capacitor on the driving side of the switching device through a closed-loop control method, thereby adjusting the turn-off speed of the switching device, slowing down the voltage change rate of the device with a relatively fast turn-off speed, and limiting the voltage overshoot of the switching device. By connecting SiC JFETs in series, the capacity, withstand voltage and power rating of the DC solid-state circuit breaker are effectively improved. Compared with the topology structure adopting a passive voltage-limiting control method, the addition of active devices in the present invention greatly reduces the voltage overshoot degree of the series switching devices. When the DC solid-state circuit breaker responds to a line short-circuit fault, it can promptly cut off the short-circuit fault; and during the fault-cutting stage of the DC solid-state circuit breaker, if the device voltage undergoes an overvoltage situation, the voltage turn-off rate can be adjusted in a timely manner to limit the unevenness degree of the branch voltage.

[0054] In a preferred embodiment of the present invention, a control method for a DC solid-state circuit breaker with a voltage-limiting protection circuit is further provided. Based on the DC solid-state circuit breaker of the present invention, it includes:

[0055] When it is determined that a fault occurs in the DC bus, the FPGA module controls the driving module to send a driving signal to the solid-state switch module to control the SiC JFET discrete devices of the first sub-module and the second sub-module to turn off.

[0056] When an overvoltage situation occurs in the first sub-module or the second sub-module, the sub-module where the overvoltage situation occurs is recorded as the faulty sub-module; the comparator of the faulty sub-module outputs a low level to control the low-voltage MOSFET device of the faulty sub-module to conduct, and at this time, the capacitor in the faulty sub-module is connected to the gate and source of the SiC JFET discrete device .

[0057] When no overvoltage situation occurs in the solid-state switch module, the comparators of the first sub-module and the second sub-module both output a high level to control the low-voltage MOSFET devices of the first sub-module and the second sub-module to turn off, and the SiC JFET discrete devices of the first sub-module and the second sub-module both maintain a normal turn-off speed.

[0058] When the DC solid-state circuit breaker is connected to the DC bus, it includes:

[0059] When there is a difference in the magnitudes between the driving resistors of the first sub-module and the second sub-module , it will cause one of the driving resistors When an overvoltage occurs in a smaller sub-module, it becomes a faulty sub-module; a normal sub-module is denoted as a normal sub-module. Ignoring the delay of the sampling module and the comparator, when the DC solid-state circuit breaker is connected to the DC bus, it includes seven consecutive stages:

[0060] During the seven stages of the turn-off process, the and theoretical waveforms of the voltages on the Figure 3 . Among them, and respectively represent the voltages on the in the first sub-module and the second sub-module; and respectively represent the voltages on the in the first sub-module and the second sub-module; represents the Miller platform voltage; represents the turn-off threshold voltage; represents the final turn-off voltage;

[0061] Stage 1 ( ): When there is no fault in the DC bus, the DC solid-state circuit breaker does not operate.

[0062] Stage 2 ( ): When a fault occurs in the DC bus, the bus current starts to rise, and the DC solid-state circuit breaker does not operate.

[0063] In Stage 2, the on-resistance of the SiC JFET is very small and can be basically ignored. The current in the circuit rises rapidly. According to the KVL law, we can obtain:

[0064] ;

[0065] Among them, represents the DC bus voltage, represents the line current during the fault, represents the load resistance during the fault, represents the line inductance.

[0066] Under the initial conditions: , , the solution after the first-order Taylor expansion is:

[0067] ;

[0068] Among them, [[ID=7�]]represents the rated current.

[0069] That is, the line current is: [[ID=⁷⁹]]

[0070] ;

[0071] Stage 3 ( ): The bus current rises to reach the preset threshold, and the SiC JFET discrete devices of the first sub-module and the second sub-module receive the turn-off signal, and the gate-source voltages both start to drop.

[0072] In Stage 3:

[0073] Since the gate-source voltages of the SiC JFET discrete devices in the first sub-module and the second sub-module do not reach the Miller plateau voltage, the DC solid-state circuit breaker has not turned off the fault current yet; the comparison voltages of the SiC JFET discrete devices in the faulty sub-module and the normal sub-module are both 0, the outputs of the comparators are both high level, and the low-voltage MOSFET devices are both turned off, and the capacitors and are both reversely charged through the corresponding drive resistors According to the KVL law, there is:

[0074] ;

[0075] where, and represent the drive resistors of the normal sub-module and the faulty sub-module respectively; and represent the capacitors of the normal sub-module and the faulty sub-module respectively ; and represent the gate-source voltages of the SiC JFET discrete devices in the normal sub-module and the faulty sub-module , that is, the voltages across and ; and represent the drive signals received by the drive resistors in the normal sub-module and the faulty sub-module respectively;

[0076] Therefore, due to the smaller drive resistor of the faulty sub-module, the gate-source voltage of the faulty sub-module drops faster than that of the normal sub-module in Stage 3.

[0077] Stage 4 ( ): The gate-source voltage of the SiC JFET discrete device in the faulty sub-module reaches the Miller plateau voltage; the of the faulty sub-module stops reverse charging, Start charging, SiC JFET discrete device Start turning off, the comparison voltage starts to rise. At this time, the comparison voltage is less than the preset reference voltage, so the comparator output of the faulty sub-module is high level, controlling the low-voltage MOSFET device Turn off, driving-side capacitor Not connected to the circuit, the turn-off speed remains normal. The preset reference voltage is half of the DC bus voltage

[0078] Stage Five ( ): The gate-source voltage of the SiC JFET discrete device in the normal sub-module reaches the Miller plateau voltage; the of the normal sub-module stops reverse charging, starts charging, SiC JFET discrete device starts turning off, the comparison voltage starts to rise

[0079] Stage Six ( ): The Miller plateau of the SiC JFET discrete device in the faulty sub-module ends, the of the faulty sub-module ends charging, starts reverse charging

[0080] Stage Seven ( ): The Miller plateau of the SiC JFET discrete device in the normal sub-module ends, the of the normal sub-module ends charging, starts reverse charging; the SiC JFET discrete devices in the faulty sub-module and the normal sub-module both continue to turn off. Since the driving resistance of the faulty sub-module is smaller, the turn-off speed is faster, resulting in the comparison voltage of the faulty sub-module being higher than that of the normal sub-module. Furthermore, the comparison voltage of the faulty sub-module is higher than the preset reference voltage, and the comparator of the faulty sub-module outputs a low level, connecting the capacitor to the gate and source of the SiC JFET discrete device to slow down the turn-off speed of the SiC JFET discrete device in the faulty sub-module

[0081] The control method of the DC solid-state circuit breaker with a voltage-limiting protection circuit according to the present invention, based on the DC solid-state circuit breaker of the present invention, has the same beneficial effects as the method of the present invention

[0082] Verification part:

[0083] ​​​​To verify the effectiveness of the proposed SSCB overvoltage protection control scheme, the feasibility of this topology will be verified through PSpice simulation. The simulation circuit topology is as Figure 4 shown. The solid-state switch module of the present invention is used as an overvoltage protection control topology and connected to the test circuit. The topology is turned on and off through VPULSE drive. VPULSE is the VPULSE pulse voltage source inside PSpice, and DC uses the built-in VDC DC voltage source of PSpice. represents the line resistance. Point A connects to the driving resistance of the first sub-module and the second sub-module in the solid-state switch module at the first end; Point D connects to the P in the solid-state switch module ; Point S connects to the N in the solid-state switch module .

[0084] The device parameters in the simulation circuit are shown in Table 1. The simulation model of the SiC JFET comes from United SiC Company in the United States, and the bus voltage is set to 1200V. The control signal is output through VPULSE to both ends of GS of the overvoltage protection control topology to drive the series JFET to turn off. By observing the turn-off waveform of the overvoltage protection control topology, the turn-off effect of this topology in the test circuit can be examined, and the feasibility of this topology circuit can be verified.

[0085] Table 1 Device Parameter Table of the Simulation Circuit

[0086] ;

[0087] The simulation results of the turn-off process of the overvoltage protection control topology are as Figure 5 , 6 shown. The simulation causes the uneven branch current by adjusting the driving resistance , . Figure 5 is the simulation result diagram with overvoltage protection control, Figure 6 is the simulation result diagram without overvoltage protection control.

[0088] It can be seen through Figure 6 that when the driving resistances R g1 and R g2 are not equal, there will be a deviation in the voltage division between the two devices J1 and J2. During the turn-off process, J is turned off first, resulting in the voltage division of J2 exceeding the ideal value. By comparing Figure 5 , it can be obtained that after adding overvoltage protection control, the turn-off speed of J2 slows down, and the degree of voltage unevenness is greatly reduced, verifying the feasibility of the overvoltage protection control method proposed in this paper.

[0089] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A control method for a DC solid-state circuit breaker with a pressure-limiting protection circuit, characterized in that, The DC solid-state circuit breaker includes a solid-state switch module, a sampling module, an isolation module, an FPGA module, and a driving module; The solid-state switch module includes a first sub-module and a second sub-module. The first sub-module and the second sub-module have the same structure and both include SiC JFET discrete devices. a capacitor and a comparator a low-voltage MOSFET device a driving resistor and a sampling resistor and ; The first end of is used to receive a driving signal. The second end of is connected to the first end of , the second end of and the first end of , and then connected to the gate of ; The second end of and the first end of are connected as a sampling point for the comparison voltage; The first end of is connected to the first end of and the drain of ; The second end of is connected to the second end of , the source of and the source of ; The second end of is connected to the drain of ; The output end of is connected to the gate of ; The negative input of is the comparison voltage, and the positive input is a preset reference voltage. In the first sub-module whose source is connected to the drain of the second sub-module The DC bus current flows into the drain of the first sub-module and flows out from the source of the second sub-module ​ The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module; The FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information; The method includes: when it is determined that a DC bus fault occurs, controlling, by the FPGA module, the drive module to send a drive signal to the solid-state switch module to control the SiC JFET discrete devices of the first sub-module and the second sub-module to turn off; when an overvoltage condition occurs in the first sub-module or the second sub-module, the sub-module in which the overvoltage condition occurs is recorded as the faulty sub-module; the comparator of the faulty sub-module outputs a low level to control the low-voltage MOSFET device of the faulty sub-module to turn on. At this time, the capacitor in the faulty sub-module is connected to the gate and source of the SiC JFET discrete device .

2. The control method of the DC solid-state circuit breaker with a pressure-limiting protection circuit according to claim 1, characterized in that, The DC solid-state circuit breaker further includes a switch protection module, and the switch protection module includes a metal oxide varistor and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel across both ends of the solid-state switch module.

3. The control method of the DC solid-state circuit breaker with a limited voltage protection circuit according to claim 2, characterized in that, When there is no overvoltage condition in the solid-state switch module, the comparators of the first sub-module and the second sub-module both output high levels to control the low-voltage MOSFET devices Q of the first sub-module and the second sub-module to turn off, and the SiC JFET discrete devices of the first sub-module and the second sub-module both maintain a normal turn-off speed.

4. The control method of the DC solid-state circuit breaker with a limited-voltage protection circuit according to claim 3, characterized in that, When the DC solid-state circuit breaker is connected to the DC bus, it includes: When there is a difference in the magnitude between the driving resistors of the first sub-module and the second sub-module it will cause an overvoltage situation in the sub-module with the smaller driving resistor which becomes a faulty sub-module; the normal sub-modules are denoted as normal sub-modules; When the DC solid-state circuit breaker is connected to the DC bus, it includes seven consecutive stages: Stage 1: When the DC bus does not fail, the DC solid-state circuit breaker does not work; Stage 2: When the DC bus fails and the bus current starts to rise, the DC solid-state circuit breaker does not work; Stage 3: The bus current rises to reach the preset threshold, and the SiC JFET discrete devices of the first sub-module and the second sub-module receive the turn-off signal, and the gate-source voltages of both start to decrease; Stage Four: Faulty Sub-module SiC JFET Discrete Device The gate-source voltage of stops reverse charging, starts charging, and the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise; Phase Five: Normal Sub-module SiC JFET Discrete Device The gate-source voltage reaches the Miller plateau voltage; the stops reverse charging, starts charging, and the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise; Phase Six: Faulty Sub-module SiC JFET Discrete Device The Miller plateau of ends, and the charging of the faulty sub-module ends, and reverse charging begins; Stage Seven: Normal Sub-module SiC JFET Discrete Device The Miller plateau of ends, and the charging of the normal sub-module ends, and reverse charging begins; the SiC JFET discrete devices of the faulty sub-module and the normal sub-module both continue to be turned off. Since the driving resistance of the faulty sub-module is smaller and the turn-off speed is faster, the comparison voltage of the faulty sub-module is higher than that of the normal sub-module, which in turn causes the comparison voltage of the faulty sub-module to be higher than the preset reference voltage. The comparator of the faulty sub-module outputs a low level, connecting the capacitor to the gate and source of the SiC JFET discrete device to slow down the turn-off speed of the SiC JFET discrete device in the faulty sub-module .

5. The control method of the DC solid-state circuit breaker with a limited voltage protection circuit according to claim 4, characterized in that, The third stage includes: Since the gate-source voltages of the SiC JFET discrete devices in the first sub-module and the second sub-module have not reached the Miller plateau voltage, the DC solid-state circuit breaker has not interrupted the fault current yet; the comparison voltages of the SiC JFET discrete devices in the faulty sub-module and the normal sub-module are both 0, the outputs of the comparators are both high level, the low-voltage MOSFET devices are all turned off, and the capacitors and are both reversely charged through the corresponding drive resistors . According to the KVL law, there is: ； Among them, and respectively represent the driving resistors of the normal sub-module and the faulty sub-module; and respectively represent the capacitors of the normal sub-module and the faulty sub-module ; and respectively represent the gate-source voltages of the SiCJFET discrete devices in the normal sub-module and the faulty sub-module That is, and the voltages across the two ends; and respectively represent the driving signals received by the driving resistors in the normal sub-module and the faulty sub-module; Therefore, due to the drive resistance of the faulty sub-module is small, the rate of decrease of the gate-source voltage of the faulty sub-module in stage three is greater than that of the normal sub-module.

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