Over-temperature protection circuit and chip

Abstract

The invention provides an over-temperature protection circuit and a chip, the over-temperature protection circuit comprises a first branch module, a second branch module and a comparator, the first branch module comprises N first branches, and the second branch module comprises N second branches and a third branch; the first branch comprises a first triode, the second branch comprises a second triode, and the third branch comprises a third triode; wherein N is a positive integer; the first branch module is used for outputting a first voltage, and the first voltage is the sum of base-emitter voltages of the first triodes in the N first branches; the second branch module is used for outputting a second voltage, and the second voltage is the sum of the base-emitter voltage of the second triodes in the N second branches and the base-emitter voltage of the third triodes; and the comparator is used for outputting an over-temperature protection signal according to a comparison result of the first voltage and the second voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuits, and more particularly, to an over-temperature protection circuit and a chip. Background Art

[0002] In recent years, with the development of electronic technology, the integration degree of the system on chip has been continuously increasing, and power consumption has become a key factor affecting the stable operation of the chip. Since there is a certain thermal resistance when the dissipated power of the chip is dissipated into the surrounding environment, especially in power circuits such as power management and motor drive, the circuit of the chip will generate higher heat. If this heat cannot be dissipated in time, it will cause the local temperature of the circuit to rise. If this temperature rises to the threshold that the device can withstand, all parameters of the transistor will change. In the light case, the working state of the transistor is abnormal, and in the severe case, the PN junction in the transistor will be broken down, causing permanent damage to the device. Therefore, the over-temperature protection circuit plays an important role in the normal operation of the chip, so that the chip can be prevented from overheating and suffering thermal damage through the over-temperature protection circuit.

[0003] In the actual operation process of the chip, the accuracy of the over-temperature protection circuit affects the reliability of the chip operation, and is also an important index in chip design. Summary of the Invention

[0004] An object of embodiments of the present disclosure is to provide an over-temperature protection circuit and a chip.

[0005] According to a first aspect of embodiments of the present disclosure, there is provided an over-temperature protection circuit, including a first branch module, a second branch module, and a comparator. The first branch module includes N first branches, and the second branch module includes N second branches and a third branch; the first branch includes a first triode, the second branch includes a second triode, and the third branch includes a third triode; where N is a positive integer;

[0006] The first branch module is configured to output a first voltage, and the first voltage is the sum of the base-emitter voltages of the first triodes in the N first branches;

[0007] The second branch module is configured to output a second voltage, and the second voltage is the sum of the base-emitter voltages of the second triodes in the N second branches and the base-emitter voltage of the third triode;

[0008] The comparator is configured to output an over-temperature protection signal according to a comparison result between the first voltage and the second voltage.

[0009] Optionally, the over-temperature protection circuit further includes a bias voltage input terminal for inputting a bias voltage,

[0010] The first branch further includes a first PMOS transistor, the second branch includes a second PMOS transistor, and the third branch further includes a third PMOS transistor;

[0011] The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the bias voltage input terminal;

[0012] The first PMOS transistor and the first triode are serially connected between the power supply terminal and the ground terminal of the overtemperature protection circuit, the second PMOS transistor and the second triode are serially connected between the power supply terminal and the ground terminal, and the third PMOS transistor and the third triode are serially connected between the power supply terminal and the ground terminal.

[0013] Optionally, when N = 1, the collectors of the first triode, the second triode, and the third triode are all connected to the ground terminal of the overtemperature protection circuit;

[0014] The collector of the first triode is connected to the base of the first triode, the collector of the second triode is connected to the base of the second triode, and the emitter of the second triode is connected to the base of the third triode;

[0015] The emitter of the first triode is connected to the first input terminal of the comparator, and the emitter of the third triode is connected to the second input terminal of the comparator.

[0016] Optionally, when N > 1, the collectors of the first triode, the second triode, and the third triode are all connected to the ground terminal of the overtemperature protection circuit;

[0017] The collector of the first triode in the first first branch is connected to the base of the first triode in the first first branch, and the collector of the second triode in the first second branch is connected to the base of the second triode in the first second branch;

[0018] The emitter of the first triode in the i-th first branch is connected to the base of the first triode in the (i + 1)-th first branch, and the emitter of the second triode in the i-th second branch is connected to the base of the second triode in the (i + 1)-th second branch, where i is a positive integer less than N;

[0019] The emitter of the first triode in the N-th first branch is connected to the first input terminal of the comparator, the emitter of the second triode in the N-th second branch is connected to the base of the third triode, and the emitter of the third triode is connected to the second input terminal of the comparator.

[0020] Optionally, the first branch further includes a fourth PMOS transistor and a fifth PMOS transistor, and the over-temperature protection circuit further includes an inverter;

[0021] The fourth PMOS transistor and the fifth PMOS transistor are connected in series between the power supply terminal and the first triode, and the gate of the fourth PMOS is connected to the bias voltage input terminal;

[0022] The output terminal of the comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the gate of the fifth PMOS transistor.

[0023] Optionally, the over-temperature protection circuit further includes a bias voltage generation module, and the bias voltage generation module is configured to generate the bias voltage.

[0024] Optionally, the bias voltage generation module includes a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor. The sixth PMOS transistor and the first NMOS transistor are connected in series between the power supply terminal and the ground terminal. The seventh PMOS transistor, the second NMOS transistor, and the first resistor are connected in series between the power supply terminal and the ground terminal. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor. The gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, and the drain of the seventh PMOS transistor are all connected to the bias voltage input terminal.

[0025] Optionally, the over-temperature protection circuit further includes an alarm module, and the alarm module is configured to issue an alarm according to the over-temperature protection signal.

[0026] Optionally, the size ratio of the first PMOS transistor to the second PMOS transistor is determined according to the temperature when the over-temperature protection circuit outputs the over-temperature protection signal.

[0027] According to a second aspect of the present disclosure, there is provided a chip including the over-temperature protection circuit according to the first aspect of the present disclosure.

[0028] Through the embodiments of the present disclosure, an over-temperature protection signal can be output when the temperature exceeds the temperature threshold to perform over-temperature protection on the chip provided with the over-temperature protection circuit, and reduce the dependence of the over-temperature protection circuit on other characteristics except temperature, thereby improving the accuracy of the over-temperature protection circuit.

[0029] Other features and advantages of the present invention will become clear through the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings. Description of the Drawings

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0031] Figure 1 is a block diagram of an over-temperature protection circuit according to an embodiment of the present disclosure;

[0032] Figure 2 is a circuit diagram of an over-temperature protection circuit according to an embodiment of the present disclosure;

[0033] Figure 3 is a circuit diagram of an over-temperature protection circuit according to another embodiment of the present disclosure;

[0034] Figure 4 is a block diagram of an over-temperature protection circuit according to another embodiment of the present disclosure;

[0035] Figure 5 is a circuit diagram of a bias voltage generation module according to an embodiment of the present disclosure. Detailed Description of the Invention

[0036] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0037] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention, its application, or its use.

[0038] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be considered as part of the specification.

[0039] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Accordingly, other examples of the exemplary embodiments may have different values.

[0040] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, further discussion thereof in subsequent drawings is not required.

[0041] The present disclosure provides an over-temperature protection circuit, as Figure 1As shown, the over-temperature protection circuit 1000 may include a first branch module 1100, a second branch module 1200, and a comparator 1300. Among them, the first branch module 1100 includes N first branches 1110-1 to 1110-N, and the second branch module 1200 includes N second branches 1210-1 to 1210-N and a third branch 1220. The first branch includes a first triode, and the second branch includes a second triode, that is, the jth first branch includes the first triode Q1-j, and the jth second branch includes the second triode Q2-j. The third branch 1220 includes a third triode Q3. Wherein, N is a positive integer, and j is a positive integer less than or equal to N.

[0042] The first branch module 1100 is used to output a first voltage, and the first voltage is the sum of the base-emitter voltages of the first triodes in the N first branches.

[0043] The second branch module 1200 is used to output a second voltage, and the second voltage is the sum of the base-emitter voltages of the second triodes in the N second branches and the base-emitter voltage of the third triode Q3.

[0044] The comparator A1 is used to output an over-temperature protection signal Vo according to the comparison result of the first voltage and the second voltage.

[0045] In one embodiment, the positive input terminal of the comparator A1 is the first input terminal, the negative input terminal of the comparator A1 is the second input terminal, the first branch module 1100 is connected to the positive input terminal of the comparator A1, and the third branch 1220 in the second branch module 1200 is connected to the negative input terminal of the comparator A1. Then, the comparator A1 may output a high level when the first voltage is greater than the second voltage, and output a low level when the first voltage is less than the second voltage. Among them, the over-temperature protection signal Vo is a high-level signal.

[0046] In this embodiment, when the temperature of the over-temperature protection circuit 1000 is lower than the temperature threshold, the first voltage is less than the second voltage, and the comparator A1 does not output the over-temperature protection signal Vo; when the temperature of the over-temperature protection circuit 1000 exceeds the temperature threshold, the first voltage is greater than the second voltage, and the comparator A1 outputs the over-temperature protection signal Vo.

[0047] In another embodiment, the positive input terminal of the comparator A1 is the second input terminal, the negative input terminal of the comparator A1 is the first input terminal, the first branch module 1100 is connected to the negative input terminal of the comparator A1, and the third branch 1220 in the second branch module 1200 is connected to the positive input terminal of the comparator A1. Then, the comparator A1 may output a high level when the first voltage is less than the second voltage, and output a low level when the first voltage is greater than the second voltage. Among them, the over-temperature protection signal Vo is a low-level signal.

[0048] In this embodiment, when the temperature of the over-temperature protection circuit 1000 is lower than the temperature threshold, the first voltage is greater than the second voltage, and the comparator A1 does not output the over-temperature protection signal Vo; when the temperature of the over-temperature protection circuit 1000 exceeds the temperature threshold, the first voltage is less than the second voltage, and the comparator A1 outputs the over-temperature protection signal Vo.

[0049] Through this embodiment, an over-temperature protection signal can be output when the temperature exceeds the temperature threshold to perform over-temperature protection on the chip provided with the over-temperature protection circuit, reduce the dependence of the over-temperature protection circuit on other characteristics except temperature, and improve the accuracy of the over-temperature protection circuit.

[0050] In the following embodiments, it will be explained by taking the positive input terminal of the comparator A1 as the first input terminal and the negative input terminal of the comparator A1 as the second input terminal as an example.

[0051] In some embodiments, as Figure 2 and Figure 3 shown, the over-temperature protection circuit 1000 further includes a bias voltage input terminal Vb for inputting a bias voltage. The first branch further includes a first PMOS transistor, the second branch includes a second PMOS transistor, and the third branch further includes a third PMOS transistor M3; that is, the jth first branch 1110-j includes a first PMOS transistor M1-j, and the jth second branch 1210-j includes a second PMOS transistor M2-j.

[0052] The gates of the first PMOS transistors M1-1 to M1-N, the gates of the second PMOS transistors M2-1 to M2-N, and the gates of the third PMOS transistors M3-1 to M3-N are all connected to the bias voltage input terminal Vb.

[0053] The first PMOS transistors M1-1 to M1-N and the first triodes Q1-1 to Q1-N are connected in series between the power supply terminal VCC and the ground terminal GND of the over-temperature protection circuit. The second PMOS transistors M2-1 to M2-N and the second triodes Q2-1 to Q2-N are connected in series between the power supply terminal VCC and the ground terminal GND. The third PMOS transistor M3 and the third triode Q3 are connected in series between the power supply terminal VCC and the ground terminal GND.

[0054] Specifically, as Figure 2 and Figure 3 shown, the jth first PMOS transistor M1-j and the jth first triode Q1-j are connected in series between the power supply terminal VCC and the ground terminal GND. The jth second PMOS transistor M2-j and the jth second triode Q2-j are connected in series between the power supply terminal VCC and the ground terminal GND. The third PMOS transistor M3 and the third triode Q3 are connected in series between the power supply terminal VCC and the ground terminal GND.

[0055] Further, the source of the j-th first PMOS transistor M1-j is connected to the power supply terminal VCC, the drain of the j-th first PMOS transistor M1-j is connected to the emitter of the j-th first triode Q1-j, and the collector of the j-th first triode Q1-j is connected to the ground terminal GND; the source of the j-th second PMOS transistor M2-j is connected to the power supply terminal VCC, the drain of the j-th second PMOS transistor M2-j is connected to the emitter of the j-th second triode Q2-j, and the collector of the j-th second triode Q2-j is connected to the ground terminal GND; the source of the third PMOS transistor M3 is connected to the power supply terminal VCC, the drain of the third PMOS transistor M3 is connected to the emitter of the third triode Q3-j, and the collector of the third triode Q3 is connected to the ground terminal GND.

[0056] When N is 1, as Figure 2 shown, the collectors of the first triode Q1, the second triode Q2, and the third triode Q3 are all connected to the ground terminal GND.

[0057] The collector of the first triode Q1 is connected to the base of the first triode Q1, the collector of the second triode Q2 is connected to the base of the second triode Q2, and the emitter of the second triode Q2 is connected to the base of the third triode Q3.

[0058] The emitter of the first triode Q1 is connected to the positive input terminal of the comparator A1, and the emitter of the third triode Q3 is connected to the negative input terminal of the comparator A1.

[0059] In this embodiment, the size ratio of the first PMOS transistor M1 to the second PMOS transistor M2 is K1:1, and the base area ratio of the first triode Q1 to the second triode Q2 is 1:K2. The differential input voltage of the comparator A1 can be expressed as:

[0060] V1 diff =V BE1 -(V BE2 +V BE3 )=V T ·ln(K1·K2)-V BE3

[0061] where V1 diff is the differential input voltage of the comparator A1 when N is 1, V BE1 is the base-emitter voltage of the first triode Q1, V BE2 is the base-emitter voltage of the second triode Q2, V BE3 is the base-emitter voltage of the third triode Q3, and V T is the positive temperature coefficient voltage.

[0062] In this embodiment, when the temperature of the overtemperature protection circuit 1000 is lower than the temperature threshold, the first voltage V BE1 is less than the second voltage (V BE2 +V BE3 ), comparator A1 outputs a low level, that is, no overtemperature protection signal Vo is output; when the temperature of the overtemperature protection circuit 1000 exceeds the temperature threshold, the first voltage V BE1 is greater than the second voltage (V BE2 +V BE3 ), and comparator A1 outputs a high-level overtemperature protection signal Vo.

[0063] Furthermore, the size ratio of the first PMOS transistor M1 to the second PMOS transistor M2, and the base area ratio of the first triode Q1 to the second triode Q2 can be determined according to the temperature when the overtemperature protection circuit outputs the overtemperature protection signal, that is, determined according to the temperature threshold.

[0064] In this embodiment, by reasonably configuring the ratios K1 and K2 between devices, the adjustment of the temperature threshold can be achieved.

[0065] In the case where N is greater than 1, as Figure 3 shown, the collectors of the first triodes Q1-1 to Q1-N, the collectors of the second triodes Q2-1 to Q2-N, and the collector of the third triode Q3 are all connected to the ground terminal GND.

[0066] The collector of the first triode Q1-1 in the first first branch 1110-1 is connected to the base of the first triode Q1-1 in the first first branch 1110-11, and the collector of the second triode Q2-1 in the first second branch 1210-1 is connected to the base of the second triode Q2-1 in the first second branch 1210-1. The emitter of the first triode Q1-i in the i-th first branch 1110-i is connected to the base of the first triode Q1-i+1 in the (i + 1)-th first branch 1110-i+1, and the emitter of the second triode Q2-i in the i-th second branch 1210-i is connected to the base of the second triode Q2-i+1 in the (i + 1)-th second branch 1210-i+1, where i is a positive integer less than N; the emitter of the first triode Q1-N in the N-th first branch 1110-N is connected to the positive input terminal of comparator A1, the emitter of the second triode Q2-N in the N-th second branch 1210-N is connected to the base of the third triode Q3, and the emitter of the third triode Q3 is connected to the negative input terminal of comparator A1.

[0067] Further, the first branch further includes a fourth PMOS transistor and a fifth PMOS transistor. The fourth PMOS transistor and the fifth PMOS transistor are connected in series between the power supply terminal and the first triode. The gate of the fourth PMOS transistor is connected to the bias voltage input terminal Vb; the gate of the fifth PMOS transistor is connected to the output terminal of the comparator A1.

[0068] As Figure 3 shown, the source of the fourth PMOS transistor M4-j in the j-th first branch 1110-j is connected to the power supply terminal VCC. The drain of the fourth PMOS transistor M4-j in the j-th first branch 1110-j is connected to the source of the fifth PMOS transistor M5-j in the j-th first branch 1110-j. The drain of the fifth PMOS transistor M5-j in the j-th first branch 1110-j is connected to the emitter of the first triode Q1-j in the j-th first branch 1110-j.

[0069] Still further, as Figure 3 shown, the over-temperature protection circuit 1000 further includes an inverter A2. The output terminal of the comparator A1 is connected to the input terminal of the inverter A2, and the output terminal of the inverter A2 is connected to the gates of the fifth PMOS transistors M5-1 to M1-5.

[0070] In this embodiment, the size ratio of the first PMOS transistor to the second PMOS transistor is K3:1, the size ratio of the fourth PMOS transistor to the second PMOS transistor is K4:1, and the base areas of the first triode and the second triode are the same.

[0071] In this embodiment, when the temperature of the over-temperature protection circuit 1000 is lower than the temperature threshold, the comparator A1 outputs a low level, and the hysteresis switches, that is, the fifth PMOS transistors M5-j, are all in the off state. The differential input voltage of the comparator A1 can be expressed as:

[0072] V diff,h = N·V BE1 -(N·V BE2 + V BE3 ) = N·V T ·ln(K3) - V BE3

[0073] where V diff,h is the differential input voltage of the comparator A1 when N is greater than 1 and the fifth PMOS transistor M5-j is off, V BE1 is the base-emitter voltage of a first triode, V BE2 is the base-emitter voltage of a second triode, V BE3 is the base-emitter voltage of a third triode, V T is the positive temperature coefficient voltage.

[0074] When the temperature of the overtemperature protection circuit 1000 exceeds the temperature threshold, the comparator A1 outputs a high level, and the hysteresis switches, i.e., the fifth PMOS transistor M5-j, are all in the on state. The differential input voltage of the comparator A1 can be expressed as:

[0075] V diff,l = N·V BE1 -(N·V BE2 +V BE3 ) = N·V T ·ln(K3 + K4)-V BE3

[0076] where V diff,h is the differential input voltage of the comparator A1 when N > 1 and the fifth PMOS transistor M5-j is off, V BE1 is the base-emitter voltage of a first triode, V BE2 is the base-emitter voltage of a second triode, V BE3 is the base-emitter voltage of a third triode, V T is the positive temperature coefficient voltage.

[0077] In this embodiment, when the temperature of the overtemperature protection circuit 1000 is lower than the temperature threshold, the first voltage N·V BE1 is less than the second voltage (N·V BE2 +V BE3 ), the comparator A1 outputs a low level, that is, does not output the overtemperature protection signal Vo; when the temperature of the overtemperature protection circuit 1000 exceeds the temperature threshold, the first voltage N·V BE1 is greater than the second voltage (N·V BE2 +V BE3 ), the comparator A1 outputs a high-level overtemperature protection signal Vo.

[0078] Furthermore, the size ratios of the first PMOS transistor to the second PMOS transistor and the fourth PMOS transistor to the second PMOS transistor can be determined according to the temperature when the overtemperature protection circuit outputs the overtemperature protection signal, that is, determined according to the temperature threshold.

[0079] In this embodiment, by reasonably configuring the ratios K3 and K4 between the devices, the adjustment of the temperature threshold can be achieved.

[0080] In this embodiment, by setting multiple triode branches and introducing the coefficient N in front of V T , the positive temperature coefficient of the differential input voltage of the comparator is effectively improved, that is, the gain of the differential input of the comparator is increased, making the temperature threshold of the overtemperature protection circuit more accurate.

[0081] In addition, only when the temperature of the overtemperature protection circuit drops to make Vdiff,l <0, the output of comparator A1 will be pulled low, stopping the output of the over-temperature protection signal Vo, releasing the over-temperature alarm, and realizing temperature hysteresis.

[0082] In some embodiments, the PMOS tube and the NMOS tube in the over-temperature protection circuit may also be replaced by other types of switches or switch tubes, such as IGBT tubes, triodes, relays, etc.

[0083] Through the over-temperature protection circuit of the embodiment of the present disclosure, the dependence of the over-temperature protection circuit on other characteristics other than temperature (such as external bias voltage and current) can be reduced, thereby improving the accuracy of the over-temperature protection circuit.

[0084] In one embodiment of the present disclosure, Figure 4 As shown, the over-temperature protection circuit 1000 further includes a bias voltage generating module 1400 , and the bias voltage generating module 1400 is used to generate a bias voltage.

[0085] In one embodiment, Figure 5 As shown, the bias voltage generating module 1400 includes a sixth PMOS tube M6, a seventh PMOS tube M7, a first NMOS tube N1, a second NMOS tube N2 and a first resistor R1. The sixth PMOS tube M6 and the first NMOS tube N1 are connected in series between a power supply terminal VCC and a ground terminal GND. The seventh PMOS tube M7, the second NMOS tube N2 and the first resistor R1 are connected in series between the power supply terminal VCC and the ground terminal GND. The gate of the first NMOS tube N1 is connected to the drain of the first NMOS tube N1 and the gate of the second NMOS tube N2. The gate of the sixth PMOS tube M6, the gate of the seventh PMOS tube M7 and the drain of the seventh PMOS tube M7 are all connected to the bias voltage input terminal Vb.

[0086] Specifically, the source of the sixth PMOS tube M6 and the source of the seventh PMOS tube M7 are both connected to the power supply terminal VCC, the drain of the sixth PMOS tube M6 is connected to the drain of the first NMOS tube N1, the drain of the seventh PMOS tube M7 is connected to the drain of the second NMOS tube N2, the source of the first NMOS tube N1 is connected to the ground terminal GND, and the first resistor R1 is connected between the source of the second NMOS tube N2 and the ground terminal GND.

[0087] In this embodiment, the sixth PMOS tube M6 and the seventh PMOS tube M7 have the same size, so that the current flowing through the first NMOS tube N1 and the second NMOS tube N2 are the same. The size ratio of the first NMOS tube N1 and the second NMOS tube N2 is 1:K5. Then, the current flowing through the first NMOS tube N1 and the second NMOS tube N2 can be expressed as:

[0088]

[0089] Among them, I is the current flowing through the first NMOS transistor N1 and the second NMOS transistor N2, μ n is the carrier mobility, C OX is the gate oxide capacitance per unit area, W / L is the aspect ratio of the MOS transistor, and R 1 is the resistance value of the first resistor R1.

[0090] The present disclosure only shows one circuit implementation of the bias voltage generation module 1400, does not limit the circuit form of the bias voltage generation module, and can also be implemented by other circuit forms.

[0091] In an embodiment of the present disclosure, as Figure 4 shown, the overtemperature protection circuit 1000 further includes an alarm module 1500, and the alarm module 1500 is used to give an alarm according to the overtemperature protection signal Vo.

[0092] In this embodiment, the alarm module 1500 may include at least one of the following devices: a light-emitting diode, a buzzer, a display screen, etc.

[0093] <Chip Embodiment>

[0094] This embodiment provides a chip, and the chip may include the aforementioned overtemperature protection circuit 1000.

[0095] In some embodiments, a power device may be provided in the chip, and the overtemperature protection circuit 1000 may be provided near the power device.

[0096] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0097] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or can be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0099] The computer program instructions for carrying out the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or, alternatively, may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present invention.

[0100] Aspects of the present invention are described herein with reference to the flowchart and / or block diagram of a method, apparatus (system), and computer program product according to embodiments of the present invention. It should be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer - readable program instructions.

[0101] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data - processing apparatus, create a means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which causes a computer, a programmable data - processing apparatus, and / or other devices to operate in a particular manner, so that the computer - readable medium storing the instructions includes a manufacture, which includes instructions for implementing various aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0102] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0103] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that implementation by hardware, implementation by software, and implementation by a combination of software and hardware are equivalent.

[0104] The embodiments of the present invention have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of technologies in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. An over-temperature protection circuit, characterized in that: The invention comprises a first branch module, a second branch module and a comparator, wherein the first branch module comprises N first branches, the second branch module comprises N second branches and a third branch; the first branch comprises a first triode, the second branch comprises a second triode, and the third branch comprises a third triode; wherein N is a positive integer; The first branch module is used to output a first voltage, and the first voltage is the sum of the base-emitter voltages of the first transistors in the N first branches; The second branch module is used to output a second voltage, where the second voltage is the sum of the base-emitter voltage of the second transistors in the N second branches and the base-emitter voltage of the third transistor; The comparator is used to output an over-temperature protection signal according to a comparison result of the first voltage and the second voltage.

2. The over-temperature protection circuit according to claim 1, characterized in that: The over-temperature protection circuit also includes a bias voltage input terminal for inputting a bias voltage. The first branch further includes a first PMOS transistor, the second branch includes a second PMOS transistor, and the third branch further includes a third PMOS transistor; The gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the third PMOS tube are all connected to the bias voltage input terminal; The first PMOS tube and the first transistor are connected in series between the power supply terminal and the ground terminal of the over-temperature protection circuit, the second PMOS tube and the second transistor are connected in series between the power supply terminal and the ground terminal, and the third PMOS tube and the third transistor are connected in series between the power supply terminal and the ground terminal.

3. The over-temperature protection circuit according to claim 2, characterized in that: When N is 1, the collector of the first transistor, the collector of the second transistor, and the collector of the third transistor are all connected to the ground terminal of the over-temperature protection circuit; The collector of the first triode is connected to the base of the first triode, the collector of the second triode is connected to the base of the second triode, and the emitter of the second triode is connected to the base of the third triode; The emitter of the first transistor is connected to the first input terminal of the comparator, and the emitter of the third transistor is connected to the first input terminal of the comparator.

4. The over-temperature protection circuit according to claim 2, characterized in that: When N is greater than 1, the collector of the first transistor, the collector of the second transistor, and the collector of the third transistor are all connected to the ground terminal of the over-temperature protection circuit; The collector of the first triode in the first first branch is connected to the base of the first triode in the first first branch, and the collector of the second triode in the first second branch is connected to the base of the second triode in the first second branch; The emitter of the first transistor in the i-th first branch is connected to the base of the first transistor in the i+1-th first branch, and the emitter of the second transistor in the i-th second branch is connected to the base of the second transistor in the i+1-th second branch, where i is a positive integer less than N; The emitter of the first transistor in the Nth first branch is connected to the first input terminal of the comparator, the emitter of the second transistor in the Nth second branch is connected to the base of the third transistor, and the emitter of the third transistor is connected to the second input terminal of the comparator.

5. The over-temperature protection circuit according to claim 4, characterized in that: The first branch further includes a fourth PMOS tube and a fifth PMOS tube, and the over-temperature protection circuit further includes an inverter; The fourth PMOS tube and the fifth PMOS tube are connected in series between the power supply terminal and the first transistor, and the gate of the fourth PMOS tube is connected to the bias voltage input terminal; The output end of the comparator is connected to the input end of the inverter, and the output end of the inverter is connected to the gate of the fifth PMOS tube.

6. The over-temperature protection circuit according to claim 2, characterized in that: The over-temperature protection circuit further includes a bias voltage generating module, and the bias voltage generating module is used to generate the bias voltage.

7. The over-temperature protection circuit according to claim 6, characterized in that: The bias voltage generating module includes a sixth PMOS tube, a seventh PMOS tube, a first NMOS tube, a second NMOS tube and a first resistor, the sixth PMOS tube and the first NMOS tube are connected in series between the power supply terminal and the ground terminal, the seventh PMOS tube, the second NMOS tube and the first resistor are connected in series between the power supply terminal and the ground terminal, the gate of the first NMOS tube is connected to the drain of the first NMOS tube and the gate of the second NMOS tube, and the gate of the sixth PMOS tube, the gate of the seventh PMOS tube and the drain of the seventh PMOS tube are all connected to the bias voltage input terminal.

8. The over-temperature protection circuit according to claim 2, characterized in that: The size ratio of the first PMOS tube to the second PMOS tube is determined according to the temperature when the over-temperature protection circuit outputs the over-temperature protection signal.

9. The over-temperature protection circuit according to claim 1, characterized in that: The over-temperature protection circuit further includes an alarm module, and the alarm module is used to issue an alarm according to the over-temperature protection signal.

10. A chip, characterized in that: The invention comprises an over-temperature protection circuit according to any one of claims 1 to 9.

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