Electrostatic discharge protection circuit and electrostatic discharge protection method

Abstract

The invention provides an electrostatic discharge protection circuit and an electrostatic discharge protection method. The electrostatic discharge protection circuit comprises a current discharge module; the current discharge module comprises a first NMOS (N-channel Metal Oxide Semiconductor) connected between a power supply and the ground; wherein the first NMOS is used for performing current discharge on an electrostatic discharge pulse in a conducting state; a driving module; the driving module is used for providing a grid voltage required by conduction of the first NMOS under the condition that electrostatic discharge is generated; the driving module comprises a first PMOS (P-channel Metal Oxide Semiconductor) connected with a power supply and a second PMOS connected with the first PMOS in series; the drain electrode of the second PMOS is connected with the grid electrode of the first NMOS; wherein the size of the first NMOS is larger than that of the first PMOS or the second PMOS; a pull-up module; and the pull-up module is connected between the power supply and the grid electrode of the first NMOS so as to pull up the potential of the drain electrode of the second PMOS in the current discharge process of the first NMOS. Therefore, the risk of gate-drain breakdown of the second PMOS can be effectively reduced, and the reliability of the electrostatic discharge protection circuit is improved.

Description

Technical Field

[0001] The embodiments in the present application relate to the field of integrated circuit technology, and particularly to an electrostatic discharge protection circuit and a method for protecting against electrostatic discharge. Background Art

[0002] Electrostatic Discharge (ESD) can generate transient pulses with high voltage and high current, causing permanent damage to sensitive integrated circuits and electronic components, resulting in failures of devices or equipment. Especially during the manufacturing, transportation, installation, and use of semiconductor devices, the risk of electrostatic discharge is particularly prominent.

[0003] Currently, by designing and integrating an effective electrostatic discharge protection circuit (ESD protection circuit), it is possible to quickly respond and discharge electrostatic energy in the event of electrostatic discharge, thereby protecting the core circuit from damage.

[0004] In the related art, the ESD protection circuit usually consists of an RC network, an inverter (INV), and a large-size MOS. When an ESD pulse occurs, the ESD discharge current can be discharged through the current path provided by the turned-on large-size MOS. However, technicians have found that this ESD protection circuit is prone to failure and has insufficient reliability in actual applications. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application are dedicated to providing an electrostatic discharge protection circuit and a method for protecting against electrostatic discharge, which can effectively improve the problem of failure of the electrostatic discharge protection circuit and enhance the reliability of the electrostatic discharge protection circuit.

[0006] An embodiment of the present application provides an electrostatic discharge protection circuit, including: a current discharge module; the current discharge module includes a first NMOS connected between a power supply and a ground; wherein, the first NMOS is used to discharge the electrostatic discharge pulse current in the on state; a driving module; the driving module is used to provide the gate voltage required for the first NMOS to turn on in the event of electrostatic discharge; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein, the size of the first NMOS is larger than the size of the first PMOS or the second PMOS; a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS to raise the potential of the drain of the second PMOS during the process of the first NMOS discharging current.

[0007] Optionally, the pull-up module includes a third PMOS; wherein, the source of the third PMOS is connected to the power supply, and the drain is connected to the gate of the first NMOS.

[0008] Optionally, the pull-up module further includes a first RC network connected to the gate of the third PMOS; the first RC network includes a first resistor and a first capacitor; wherein, the gate of the third PMOS is connected to the power supply through the first resistor and grounded through the first capacitor.

[0009] Optionally, the gate of the third PMOS is connected to the source of the second PMOS.

[0010] Optionally, the pull-up module further includes a protection resistor provided between the gate of the third PMOS and the source of the second PMOS.

[0011] Optionally, the pull-up module includes a second NMOS; wherein, the drain of the second NMOS is connected to the power supply, and the source is connected to the gate of the first NMOS.

[0012] Optionally, the pull-up module further includes a pull-up resistor provided between the gate of the first NMOS and the drain of the second PMOS.

[0013] Optionally, the gate of the second NMOS is at the same potential as the gate of the first PMOS and the gate of the second PMOS.

[0014] Optionally, the electrostatic discharge protection circuit further includes a second RC network; the second RC network includes a second resistor and a second capacitor; the gates of the first PMOS and the second PMOS are commonly connected to the second RC network; wherein, the gates of the first PMOS and the second PMOS are connected to the power supply through the second resistor and grounded through the second capacitor.

[0015] An embodiment of the present application provides a method for protecting electrostatic discharge. The method for protecting electrostatic discharge includes: in the case of generating electrostatic discharge, providing a gate voltage to a first NMOS connected between the power supply and the ground through a driving module, making the first NMOS in an on state, and discharging the current of the electrostatic discharge pulse; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than the size of the first PMOS or the second PMOS; wherein, during the process of the first NMOS discharging current, the potential of the drain of the second PMOS is pulled up by a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS.

[0016] Multiple embodiments provided by the present application have an unexpected effect that by adding a pull-up module in front of the gate of the large-size first NMOS, during the process of the first NMOS discharging current for an electrostatic discharge pulse, the charging speed of the gate capacitance of the first NMOS can be increased, and the drain potential of the second PMOS connected to the gate of the first NMOS can be pulled up, thereby reducing the potential difference between the gate and the drain of the second PMOS and reducing the risk of gate-drain breakdown, and further improving the problem of electrostatic discharge protection circuit failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of an electrostatic discharge protection circuit in the related art.

[0018] Figure 2 It is a schematic diagram of the nano-probe measurement results for the failure analysis of the electrostatic discharge protection circuit.

[0019] Figure 3 and Figure 4 It is a schematic diagram of the transmission electron microscope results for the failure analysis of the electrostatic discharge protection circuit.

[0020] Figure 5 It is a schematic diagram of the simulation results of the electrostatic discharge protection circuit in the related art.

[0021] Figure 6 It is a schematic diagram of the electrostatic discharge protection circuit provided by an embodiment of the present application.

[0022] Figure 7 It is a schematic diagram of the simulation results of the electrostatic discharge protection circuit provided by an embodiment of the present application.

[0023] Figure 8 It is a schematic diagram of the electrostatic discharge protection circuit provided by another embodiment of the present application.

[0024] Figure 9 It is a schematic diagram of the simulation results of the electrostatic discharge protection circuit provided by another embodiment of the present application.

[0025] Figure 10 It is a schematic diagram of the electrostatic discharge protection circuit provided by still another embodiment of the present application.

[0026] Figure 11 It is a schematic diagram of the simulation results of the electrostatic discharge protection circuit provided by still another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0028] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0029] Unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by those skilled in the technical field of this application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned", and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of this application, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0031] In the description of this application, the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of the simplified description of this application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, that is, it cannot be construed as a limitation on this application.

[0032] In the description of this application, unless otherwise clearly defined, terms such as "installation", "connection", "connection", "fixation", "setting", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can also be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] Please refer to Figures 1 to 5 ... Traditional electrostatic discharge (ESD) protection circuits such as Figure 1As shown in [reference], it is composed of an RC network, an inverter INV, and a large-sized MOS transistor NM'. The inverter includes two PMOS transistors connected in series, namely Figure 1 PM1' and PM2' in [reference]. Among them, the source of PM1' is connected to the power supply, the drain is connected to the source of PM2', the drain of PM2' is connected to the gate of NM', and the gates of PM1' and PM2' are connected between the power supply and the ground through the RC network. When an electrostatic discharge pulse occurs across the power supply and the ground, a voltage drop is generated across the resistor R, causing the gate voltages of PM1' and PM2' to be less than the source voltages and turn on. Subsequently, NM' can be turned on to form a low-impedance path between the power supply and the ground to discharge the current I_ESD.

[0034] In the related art, the size of NM' is usually large to meet the withstand voltage requirements during current discharge, so NM' has a large gate capacitance. However, the drain of PM2' is connected to the gate of NM', which is equivalent to the drain of PM2' being connected to the gate capacitance of NM'. Due to the large gate capacitance of NM', its charging speed is relatively slow, resulting in the potential VD2' of the drain of PM2' connected to the gate of NM' being less than the potential VD1' of the drain of PM1' during the process of NM' starting to conduct and discharging current. Furthermore, since the gate potentials of PM1' and PM2' are the same, both being VG', there is a large voltage difference between the gate potential VG' and the drain potential VD2' of PM2'. When the voltage difference is greater than the breakdown voltage of PM2', it will cause gate-drain breakdown of PM2', and the electrostatic discharge protection circuit fails.

[0035] Technicians conducted a failure analysis (FA) on the actual product and found that the nano probe measurement results of PM2' are as Figure 2 shown in [reference], with μA-level leakage between the gate and the drain, and found that the TEM (transmission electron microscope) results are as Figure 3 and Figure 4 shown in [reference], with diffusion of NiSi between the gate and the drain, indicating that gate-drain breakdown of PM2' has occurred.

[0036] In addition, technicians also simulated the turn-on situation of the above electrostatic discharge protection circuit under a 2KV electrostatic discharge pulse. The simulation results are as Figure 5 shown in [reference]. It can be seen from it that at 0.5 μs, an electrostatic discharge pulse is generated at the power supply end, the electrostatic discharge protection circuit turns on, and the current I_ESD is discharged through NM'. By comparing the voltages at each node, it can be found that VD2' is always lower than VD1' and has a large voltage difference from VG'. The voltage difference reaches a maximum value of 4.0V at 1.35 μs, which is likely to cause gate-drain breakdown.

[0037] Therefore, it is necessary to provide an electrostatic discharge protection circuit that can reduce the risk of gate-drain breakdown and thus improve the problem of electrostatic discharge protection circuit failure.

[0038] Please refer to Figure 6 and Figure 7 . An embodiment of the present application provides an electrostatic discharge protection circuit. As Figure 7 shown, the electrostatic discharge protection circuit may include a current discharge module 11, a driving module 12, a pull-up module 13, and a second RC network 14.

[0039] In this embodiment, the current discharge module 11 is used to provide a low-impedance current path from the power supply to the ground in the case of generating an electrostatic discharge, so as to discharge the electrostatic discharge pulse through this path, thereby realizing the function of the protection circuit. Specifically, the current discharge module 11 includes a first NMOS connected between the power supply and the ground, that is, Figure 6 NM in

[0040] . The first NMOS is used to discharge the electrostatic discharge pulse in the conducting state. Among them, the source of NM is grounded, and the drain is connected to the power supply. Figure 6 In this embodiment, the driving module 12 is used to provide the gate voltage required for NM to conduct in the case of generating an electrostatic discharge. Specifically, the driving module 12 includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS, that is,

[0041] PM1 and PM2 in

[0042] . Among them, the source of PM1 is connected to the power supply, the drain is connected to the source of PM2, and the drain of PM2 is connected to the gate of NM, so as to control the conduction or cut-off of NM through the potential VD2 of the drain of PM2. The gates of PM1 and PM2 can be connected to the same potential VG.

[0043] In this embodiment, the driving module 12 may further include two NMOS connected in series between VD2 and the ground, and these two NMOS and PM1, PM2 can form an inverter.

[0044] In this embodiment, the pull-up module 13 may include a third PMOS, namely Figure 6 PM3 in Figure 6 , and a first RC network connected to the gate of PM3. The first RC network includes a first resistor R1 and a first capacitor C1. Wherein, the source of PM3 is connected to the power supply, and the drain is connected to the gate of NM. The gate of PM3 is connected to the power supply through R1 and grounded through C1.

[0045] In this embodiment, when an electrostatic discharge pulse occurs, a voltage drop can be generated across the first resistor R1 of the first RC network to turn on PM3. The current flowing through PM3 can charge the gate of NM, thus improving the charging speed of the gate capacitance of NM. At the same time node, the gate voltage of NM is higher, and the potential of VD2 is pulled up.

[0046] In this embodiment, by setting the first RC network, when an electrostatic discharge pulse occurs, the response of PM3 can have a certain delay, preventing the instantaneous electrostatic discharge energy from causing a large impact on the circuit. It should be noted that in some embodiments, for example, in some application scenarios with low ESD voltage, the first RC network may not be provided in the pull-up module 13.

[0047] In this embodiment, the electrostatic discharge protection circuit may further include a second RC network 14. Specifically, the second RC network 14 may include a second resistor R2 and a second capacitor C2. In this embodiment, the gates of PM1 and PM2 may be commonly connected to the second RC network 14. Wherein, the gates of PM1 and PM2 are connected to the power supply through R2 and grounded through C2. Similarly, the second RC network 14 can provide a delay for the response of the electrostatic discharge protection circuit to protect the circuit.

[0048] In this embodiment, an unexpected effect is that through the pull-up module 13, during the process of the first NMOS discharging the electrostatic discharge pulse current, the charging speed of the gate capacitance of the first NMOS can be improved, and the drain potential of the second PMOS connected to the gate of the first NMOS can be pulled up, thereby reducing the potential difference between the gate and the drain of the second PMOS and reducing the risk of gate-drain breakdown, and further improving the problem of electrostatic discharge protection circuit failure.

[0049] Technicians simulated the turn-on situation of the electrostatic discharge protection circuit provided in this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as Figure 7As shown, it can be seen that an electrostatic discharge pulse is generated at the power supply terminal at 0.5 μs, the electrostatic discharge protection circuit is turned on, and the current is discharged through NM. By comparing the voltages of each node, it can be found that the potential difference between VD2 and VG is significantly reduced, and the potential difference reaches a maximum value of 2.0 V at 1.39 μs, which is 50% lower than that of the ESD protection circuit in the related art, reducing the risk of PM2 being broken down. At the same time, the potential difference between the source and gate of PM3 is basically the same as that of PM1, and the potential difference between the drain and gate is basically the same as that of PM2, and the breakdown risk is also small.

[0050] In addition, please refer to Figure 5 again, from Figure 5 it can also be seen that in the electrostatic discharge protection circuit in the related art, the current flowing through NM' is basically 0 at 1.6 μs, that is, NM' is turned off, but the ESD discharge process lasts until about 2 μs, so there is still a problem of incomplete current discharge in the electrostatic discharge protection circuit in the related art.

[0051] And from Figure 7 it can be seen that in the electrostatic discharge protection circuit provided in this embodiment, the current flowing through NM is basically 0 at 2.0 μs, that is, NM is turned off, which is consistent with the entire ESD discharge process. Therefore, the current discharge of the electrostatic discharge protection circuit provided in this embodiment is more complete.

[0052] Please refer to Figure 8 and Figure 9 . Another embodiment of the present application provides an electrostatic discharge protection circuit. As Figure 8 shown, the electrostatic discharge protection circuit may include a current discharge module 21, a driving module 22, a pull-up module 23, and a second RC network 24. The difference from the previous embodiment is that in this embodiment, the pull-up module 23 is composed of a third PMOS, that is, PM3, and a protection resistor R3 provided between the gate of PM3 and the source of PM2. Among them, PM3 is connected to the source of PM2 through R3.

[0053] In this embodiment, the functions and effects of the same parts as in the previous embodiment can be explained with reference to the previous embodiment, and will not be repeated here.

[0054] In this embodiment, an unexpected effect is that while using the pull-up module 23 to raise the drain potential of the second PMOS to reduce the potential difference between the gate and drain of the second PMOS and achieve the risk of gate-drain breakdown, compared with the previous embodiment, fewer electronic components are used, the connection method is simpler, and the occupied integrated circuit layout area is smaller.

[0055] Technicians simulated the turn-on situation of the electrostatic discharge protection circuit provided in this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as Figure 9 shown. It can be seen from it that at 0.5 μs, an electrostatic discharge pulse is generated at the power supply terminal, the electrostatic discharge protection circuit turns on, and the current is discharged through NM. By comparing the voltages of each node, it can be found that the potential difference between VD2 and VG is significantly reduced, and the potential difference reaches a maximum value of 2.1V at 1.35 μs. Compared with the ESD protection circuit in the related art, it is reduced by 48%, reducing the risk of the second PMOS being broken down. Although the potential difference between the drain and gate of PM3 also reaches 2.7V at 1.35 μs, compared with the 4V potential difference between the gate and drain of PM2' in the ESD protection circuit of the related art, it is also reduced by 33%, reducing the risk of being broken down.

[0056] In addition, it can be seen from Figure 9 that for the electrostatic discharge protection circuit provided in this embodiment, the current flowing through NM is basically 0 at 2.0 μs, that is, NM is turned off, which is consistent with the entire ESD discharge process. Therefore, the current discharge of the electrostatic discharge protection circuit provided in this embodiment is also more complete.

[0057] Please refer to Figure 10 and Figure 11 . Another embodiment of the present application provides an electrostatic discharge protection circuit. As Figure 10 shown, the electrostatic discharge protection circuit may include a current discharge module 31, a driving module 32, a pull-up module 33, and a second RC network 34. The difference from the foregoing embodiment is that in this embodiment, the pull-up module 33 is composed of a second NMOS, that is, Figure 10 NM1 in, and a pull-up resistor R4 provided between the gate of NM and the drain of PM2. Wherein, the drain of NM1 is connected to the power supply, and the source is connected to the gate of NM. The bulk terminal of NM1 can be grounded or connected to the source. The gate of NM1 can be connected to the gates of PM1 and PM2 at the same node, so that the potential of the gate of NM1 is the same as that of the gates of PM1 and PM2, both being VG.

[0058] In this embodiment, the pull-up resistor R4 can further raise the potential VD2 of the drain of PM2 when the current flowing through the second NMOS is insufficient to charge the gate of NM, so as to reduce the potential difference between the gate and drain of the second PMOS. It should be noted that in some embodiments, for example, when the charging effect of the second NMOS on the gate of NM is already sufficient, the pull-up resistor R4 may not be provided, and it can be set flexibly according to needs.

[0059] In this embodiment, the functions and effects of the same parts as those in the foregoing embodiment can be explained with reference to the foregoing embodiment, and will not be elaborated here.

[0060] In this embodiment, an unexpected effect is that when using the pull-up module 33 to raise the drain potential of the second PMOS to reduce the potential difference between the gate and the drain of the second PMOS and achieve the risk of reducing gate-drain breakdown, at the same time, fewer electronic components are also used, the connection method is simpler, and the occupied integrated circuit layout area is smaller.

[0061] Technicians simulated the turn-on situation of the electrostatic discharge protection circuit provided in this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as Figure 11 shown. It can be seen from it that at 0.5 μs, an electrostatic discharge pulse is generated at the power supply terminal, the electrostatic discharge protection circuit is turned on, and the current is discharged through NM. By comparing the voltages of each node, it can be found that the potential difference between VD2 and VG is significantly reduced, and the potential difference reaches a maximum value of 2.04V at 1.51 μs. Compared with the ESD protection circuit in the related art, it is reduced by 49%, reducing the risk of the second PMOS being broken down. At the same time, the potential difference between the source potential VD3 of PM3 and the gate potential VG reaches a maximum value of 2.05V at 1.51 μs, and the breakdown risk is also small.

[0062] In addition, it can be seen from Figure 11 that for the electrostatic discharge protection circuit provided in this embodiment, the current flowing through NM is basically 0 at 2.2 μs, that is, NM is turned off, which is consistent with the entire ESD discharge process. Therefore, the electrostatic discharge protection circuit provided in this embodiment can also discharge the current completely and effectively.

[0063] An embodiment of the present application provides a method for protecting electrostatic discharge. The method for protecting electrostatic discharge includes:

[0064] In the case of generating electrostatic discharge, a gate voltage is provided to a first NMOS connected between a power supply and a ground through a driving module to make the first NMOS in a conducting state, and the electrostatic discharge pulse is current-discharged; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than the size of the first PMOS or the second PMOS; wherein, during the process of current-discharging by the first NMOS, the potential of the drain of the second PMOS is raised by a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS.

[0065] For the functions and effects of the steps in the electrostatic discharge protection method, reference may be made to the foregoing embodiments for explanation and description, which will not be elaborated here.

[0066] It can be understood that the specific examples in this article are only for helping those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the present invention.

[0067] It can be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the various processes do not imply the order of execution, and the order of execution of the various processes should be determined by their functions and internal logics, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0068] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0069] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the related listed items. The singular forms of "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0070] As described above, the above are only specific embodiments of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that: include: Current discharge module; The current discharge module includes a first NMOS connected between a power source and a ground; wherein the first NMOS is used to discharge the current of an electrostatic discharge pulse in a conducting state; A driving module; the driving module is used to provide a gate voltage required for the first NMOS to be turned on when electrostatic discharge occurs; the driving module includes a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein the size of the first NMOS is larger than that of the first PMOS or the second PMOS; A pull-up module; the pull-up module is connected between a power supply and the gate of the first NMOS to pull up the potential of the drain of the second PMOS during the current discharge of the first NMOS.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: The pull-up module includes a third PMOS; wherein a source of the third PMOS is connected to a power source, and a drain is connected to a gate of the first NMOS.

3. The electrostatic discharge protection circuit according to claim 2, characterized in that: The pull-up module also includes a first RC network connected to the gate of the third PMOS; the first RC network includes a first resistor and a first capacitor; wherein the gate of the third PMOS is connected to a power supply through the first resistor and is grounded through the first capacitor.

4. The electrostatic discharge protection circuit according to claim 2, characterized in that: The gate of the third PMOS is connected to the source of the second PMOS.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that: The pull-up module further includes a protection resistor arranged between the gate of the third PMOS and the source of the second PMOS.

6. The electrostatic discharge protection circuit according to claim 1, characterized in that: The pull-up module includes a second NMOS; wherein the drain of the second NMOS is connected to a power source, and the source is connected to the gate of the first NMOS.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that: The pull-up module further includes a pull-up resistor arranged between the gate of the first NMOS and the drain of the second PMOS.

8. The electrostatic discharge protection circuit according to claim 7, characterized in that: The gate of the second NMOS has the same potential as the gate of the first PMOS and the gate of the second PMOS.

9. The electrostatic discharge protection circuit according to any one of claims 1 to 8, characterized in that: The electrostatic discharge protection circuit also includes a second RC network; the second RC network includes a second resistor and a second capacitor; the gate of the first PMOS and the gate of the second PMOS are commonly connected to the second RC network; wherein the gate of the first PMOS and the gate of the second PMOS are connected to a power supply through the second resistor and are grounded through the second capacitor.

10. A method for protecting against electrostatic discharge, characterized in that: The electrostatic discharge protection method comprises: In the case of electrostatic discharge, a gate voltage is provided to a first NMOS connected between a power supply and a ground through a driving module, so that the first NMOS is in a conducting state and current discharges the electrostatic discharge pulse; the driving module comprises a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than that of the first PMOS or the second PMOS; Wherein, during the current discharge of the first NMOS, the potential of the drain of the second PMOS is pulled up by a pull-up module; the pull-up module is connected between a power source and a gate of the first NMOS.

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