Inverter adjustment device and inverter adjustment method

Abstract

The embodiment of the invention relates to an inverter adjusting device and an inverter adjusting method. The present invention suppresses a decrease in life of an inverter having a plurality of switching elements connected in parallel. An inverter adjustment device according to an embodiment is a device for adjusting an inverter configured by connecting a plurality of switching elements in parallel. The inverter adjustment device is provided with a heat generation amount measurement device and an on-time ratio determination unit. The calorific value measuring device measures the calorific value of each switching element. The on-time ratio determination unit determines the ratio between the on-time and the off-time of each of the switching elements such that the difference in the heat generation amount of each of the switching elements measured by the heat generation amount measurement device falls within a predetermined range.

Description

This application claims priority from Japanese Patent Application No. 2023-209355 filed on December 12, 2023. By reference to the Japanese application, this application incorporates the entire contents of the Japanese application. Technical Field

[0001] Embodiments of the present invention relate to an inverter adjustment device and an inverter adjustment method. Background Art

[0002] In a high-output inverter, in order to reduce the load applied to one switching element, multiple switching elements are often connected in parallel. However, since there are deviations in characteristics such as on-resistance and gate capacitance among the switching elements, the loads applied to the respective parallel-connected switching elements are not the same.

[0003] The switching element with a more concentrated load generates more heat, and the degree of aging progresses faster. Therefore, the possibility of early breakage is higher. Switching elements mostly break in the short-circuit mode. Therefore, when one of the multiple parallel-connected switching elements breaks, the inverter breaks. Therefore, when the load is concentrated on one of the multiple parallel-connected switching elements, the life of the inverter is reduced.

[0004] Although there are reports on load dispersion when multiple inverters are connected in parallel, there are no reports on techniques for suppressing the difference in loads applied to multiple switching elements connected in parallel within one inverter. Summary of the Invention

[0005] The present invention has been completed in view of the above circumstances, and its object is to suppress a reduction in the life of an inverter having multiple switching elements connected in parallel.

[0006] An inverter adjustment device according to an embodiment for solving the above problems is a device for adjusting an inverter constituted by connecting multiple switching elements in parallel. The inverter adjustment device includes a heat generation amount measuring device and a conduction time ratio determination unit. The heat generation amount measuring device measures the heat generation amount of each of the switching elements; the conduction time ratio determination unit determines the ratio of the conduction time and the cutoff time of each of the switching elements so that the difference in the heat generation amount of each of the switching elements measured by the heat generation amount measuring device is within a specified range. Thereby, it is possible to reduce the deviation of the load applied to the parallel-connected switching elements and reduce the temperature difference of the parallel-connected switching elements. Therefore, it is possible to suppress a reduction in the life of an inverter having multiple switching elements connected in parallel. Brief Description of the Drawings

[0007] Figure 1 It is a perspective view of an elevator device according to a first embodiment. Figure 2It is a block diagram showing the control system of the elevator device according to the first embodiment of the present invention. Figure 3 It is a block diagram of the drive unit according to the first embodiment of the present invention. Figure 4 It is a configuration diagram of the inverter according to the first embodiment of the present invention. Figure 5 It is a diagram for explaining the inverter according to the first embodiment of the present invention. Figure 6 It is a configuration diagram of the switching element group according to the first embodiment of the present invention. Figure 7 It is a physical block diagram of the control unit according to the first embodiment of the present invention. Figure 8 It is a functional block diagram of the control unit according to the first embodiment of the present invention. Figure 9 It is a flowchart for explaining the gate resistance determination process according to the first embodiment of the present invention. Figure 10 It is a diagram for explaining the surge voltage of the inverter according to the first embodiment of the present invention. Figure 11 It is a diagram for explaining the surge voltage of the inverter according to the first embodiment of the present invention. Figure 12 It is a diagram for explaining the surge voltage of the inverter according to the first embodiment of the present invention. Figure 13 It is a diagram for explaining the surge voltage of the inverter according to the first embodiment of the present invention. Figure 14 It is a diagram for explaining the surge voltage of the inverter according to the first embodiment of the present invention. Figure 15 It is a flowchart for explaining the conduction time ratio determination process according to the first embodiment of the present invention. Figure 16 It is a diagram for explaining the conduction time ratio determination process according to the first embodiment of the present invention. Figure 17 It is a diagram for explaining the conduction time ratio determination process according to the first embodiment of the present invention. Figure 18 It is a diagram for explaining the conduction time ratio determination process according to the first embodiment of the present invention. Figure 19 It is a diagram for explaining the conduction time ratio determination process according to the first embodiment of the present invention. Figure 20 It is a flowchart for explaining the second gate resistance determination process according to the second embodiment of the present invention. Detailed implementation mode

[0008] Hereinafter, this embodiment will be described with reference to the drawings. In the description, an XYZ coordinate system composed of mutually orthogonal X-axis, Y-axis, and Z-axis is appropriately used. The figures and flowcharts used in the description of this embodiment show an example.

[0009] Figure 1 is a perspective view of the elevator device 10 of this embodiment. The elevator device 10 is disposed inside a hoistway 100 provided in a building such as a commercial facility or a residential facility. As Figure 1 shown, the elevator device 10 includes a passenger car 31, a counterweight 50, a hoist motor 40, guide rails 21 to 24, and a control panel 70 (elevator control device).

[0010] The guide rails 21 to 24 are members whose longitudinal direction is the Z-axis direction. The guide rails 21 and 22 are a pair of members for guiding the passenger car 31 to move up and down freely. In addition, the guide rails 23 and 24 are a pair of members for guiding the counterweight 50 to move up and down freely. The guide rails 21 and 22 are arranged at intervals in the Y-axis direction. In addition, the guide rails 23 and 24 are also arranged at intervals from each other in the Y-axis direction. In Figure 1 the guide rails 23 and 24 of the counterweight 50 are arranged at intervals in the X-axis direction with respect to the guide rails 21 and 22 of the passenger car 31. In addition, the arrangement of the guide rails 21 to 24 is not limited to Figure 1 the arrangement shown.

[0011] The passenger car 31 is a unit that accommodates users and moves up and down via the hoistway 100. The passenger car 31 is disposed between the guide rails 21 and 22 and is mounted so as to be movable in the vertical direction with respect to the guide rails 21 and 22.

[0012] On the +X side surface of the passenger car 31, an opening 31a for entering and exiting the interior is formed. The opening 31a is closed or opened by a pair of doors 32 that move along the side surface of the passenger car 31. The doors 32 are opened and closed by an opening and closing motor (not shown in Figure 1 ).

[0013] The counterweight 50 is mounted so as to be movable in the vertical direction with respect to the guide rails 23 and 24. The weight of the counterweight 50 is adjusted to a prescribed ratio with respect to the weight of the passenger car 31.

[0014] The hoist motor 40 is a motor for raising and lowering the passenger car 31. The hoist motor 40 is disposed at the upper part of the hoistway 100 with its rotation axis parallel to the Y-axis. A pulley 42 is fixed to the rotation axis of the hoist motor 40. A wire rope 43 is wound around the pulley 42 of the hoist motor 40. One end of the wire rope 43 is fixed to the passenger car 31, and the other end is fixed to the counterweight 50.

[0015] The control panel 70 is arranged on the hoistway 100. A control device for controlling equipment provided on the hoist motor 40, the passenger car 31, etc. is accommodated in the control panel 70.

[0016] Figure 2 It is a block diagram showing the control system of the elevator device 10. The control system includes a control unit 80 and a drive unit 91 accommodated in the control panel 70 and an operation panel 36 provided in the passenger car 31.

[0017] The operation panel 36 is provided on the inner wall surface of the passenger car 31. The operation panel 36 is an interface for receiving the destination floor, etc. from the user of the passenger car 31. By operating the operation panel 36, the user can register the destination floor, etc. of the passenger car 31 and open and close the door 32. The operation panel 36 is connected to the control unit 80 accommodated in the control panel 70 via Figure 1 the cable 44 shown.

[0018] Figure 2 The drive unit 91 shown drives the hoist motor 40 by supplying electric power to the hoist motor 40. The drive unit 91 drives the hoist motor 40 according to an instruction from the control unit 80. The control unit 80 controls the drive unit 91 according to an input from the operation panel 36 or the call panels on each floor. For example, when the control unit 80 rotates the hoist motor 40 forward via the drive unit 91, the passenger car 31 ascends and the counterweight 50 descends. When the control unit 80 rotates the hoist motor 40 in reverse via the drive unit 91, the passenger car 31 descends and the counterweight 50 ascends.

[0019] Figure 3 It is a block diagram of the drive unit 91. The drive unit 91 has a converter 11 and an inverter 13. The converter 11 is a power supply device that converts the AC voltage supplied from the commercial power supply 1 into a DC voltage. The converter 11 is composed of a switching regulator. In the present embodiment, the converter 11 supplies a voltage that is positive and a voltage that is negative with respect to the ground potential to the inverter 13. The inverter 13 is a power supply device that converts the DC voltage supplied from the converter 11 into an AC voltage of a specified voltage at a specified frequency and supplies electric power to the hoist motor 40. The inverter 13 is composed of a switching regulator.

[0020] Figure 4 It is a circuit example of the inverter 13. The inverter 13 has an oscillation circuit 155, a conduction time setting unit 150, a gate resistor group 140, and a switching element group 130. The oscillation circuit 155 supplies a clock of a specified frequency to the switching element group 130 via the gate resistor group 140 and the conduction time setting unit 150. The gate resistor group 140 and the conduction time setting unit 150 constitute a part of an inverter adjustment device 75 described later.

[0021] Figure 5 This is a diagram for explaining the drive circuit of the FETs that make up the switching element group 130 of the inverter 13. Figure 5 This shows the drive circuit of one FET 134. Specifically, the clock output by the oscillation circuit 155 is supplied to the gate of the FET 134 via the conduction time setting unit 150 and the gate resistor group 140. The conduction time setting unit 150 and the gate resistor group 140 are respectively provided on the switching elements.

[0022] The conduction time setting unit 150 is a circuit that determines the ratio of the conduction time (the time when the clock supplied to the gate is high) and the cutoff time (the time when the clock supplied to the gate is low) of each switching element. The conduction time setting unit 150 includes a plurality of delay elements with different delay times that can be selectively provided and an AND circuit. Here, Figure 5 the delay time of the shown delay element ta151 is smaller than the delay time of the delay element tb152, and the delay time of the delay element tb152 is smaller than the delay time of the delay element tc153. The delay time of the delay element ta151 with the smallest delay time can be 0 seconds. The delay times of the delay element ta151, the delay element tb152, and the delay element tc153 are determined by the deviation of the on-resistance of the FET, etc. When one of the delay element ta151, the delay element tb152, and the delay element tc153 is specified, the conduction time setting unit 150 sets the ratio of the high-level time and the low-level time of the clock supplied to the switching element by taking the "AND" of the clock output by the oscillation circuit 155 and the clock delayed by the specified delay element. The larger the delay time of the delay element, the shorter the high-level time of the clock and the smaller the conduction time ratio of the switching element. The delay times of the delay element ta151, the delay element tb152, and the delay element tc153 are set such that, for example, the high-level times of the clock supplied to the gate of the FET differ by 2% from each other. The method for setting the delay times of the delay element ta151, the delay element tb152, and the delay element tc153 will be described later.

[0023] The gate resistor group 140 selectively includes a plurality of resistors with different resistance values. Here, let Figure 5The resistance value of the gate resistor Ra141 shown is smaller than that of the gate resistor Rb142, and the resistance value of the gate resistor Rb142 is smaller than that of the gate resistor Rc143. The resistance values of the gate resistor Ra141, the gate resistor Rb142, and the gate resistor Rc143 are determined by the gate capacitance of the FET and the impedance of the lifting motor 40, etc. The resistance values of the gate resistor Ra141, the gate resistor Rb142, and the gate resistor Rc143 are set such that, for example, the resistance values differ by 10% from each other. The gate resistor group 140 selects one resistor from the plurality of resistors that make up the gate resistor group 140 and supplies the clock supplied from the oscillation circuit 155 to the gate of the FET134.

[0024] Among the plurality of FETs (FET132 and FET134) that make up the switching element group 130, there are provided a voltage measuring device 161 that measures the voltage Vds (switching voltage) between the drain and source of the FET, a current measuring device 162 that measures the current Ids flowing through the FET, and a temperature measuring device 163 that measures the temperature of the FET.

[0025] Figure 6 This is a circuit example of the switching element group 130. The switching elements that make up the switching element group 130 are composed of transistors or FETs (Field Effect Transistors), insulated gate bipolar transistors (IGBTs: Insulated Gate Bipolar Transistors), etc. Here, the case where an FET is used as the switching element will be described as an example. The switching element group 130 is composed of three parallel-connected FET132s and three parallel-connected FET134s connected in series. A DC voltage output from the converter 11 is applied between the terminal P1 and the terminal P2. The terminal P3 is connected to the lifting motor 40. The clock output from the oscillation circuit 155 is supplied to the gates of the FET132 and the FET134 via the conduction time setting unit 150 and the gate resistor group 140. The FET132 and the FET134 become conductive during the period when the clock supplied to the gate is at a high level and become non-conductive during the period when it is at a low level.

[0026] Figure 7is a physical block diagram of the control unit 80. The control unit 80 is a computer having a CPU (Central Processing Unit) 81, a main storage unit 82, an auxiliary storage unit 83, and an interface unit 84 that are interconnected via a bus 85. The CPU 81 executes the processes described below according to the programs stored in the auxiliary storage unit 83. The main storage unit 82 includes a RAM (Random Access Memory). The main storage unit 82 serves as a working area for the CPU 81. The auxiliary storage unit 83 includes non-volatile memories such as a ROM (Read Only Memory) and a semiconductor memory. The auxiliary storage unit 83 stores the programs executed by the CPU 81 and various parameters, etc.

[0027] The interface unit 84 includes a serial interface, a parallel interface, a wireless LAN interface, etc. The operation panel 36 and the drive unit 91 are connected to the CPU 81 via the interface unit 84. In addition, an input / output device 93 composed of a keyboard, a display, etc. is connected to the interface unit 84.

[0028] Figure 8 is a functional block diagram of the control unit 80. The control unit 80 implements the functions of the inverter adjustment device 75 by executing the programs stored in the auxiliary storage unit 83. The inverter adjustment device 75 includes a measurement data acquisition unit 77, a gate resistance determination unit 78, and a conduction time ratio determination unit 79. The inverter adjustment device 75 includes the above-mentioned conduction time setting unit 150 and the gate resistance group 140.

[0029] The measurement data acquisition unit 77 acquires the data measured by the voltage measurement device 161, the current measurement device 162, and the temperature measurement device 163.

[0030] The gate resistance determination unit 78 controls the selection of one resistor from the multiple resistors that make up the gate resistance group 140. The gate resistance determination unit 78 selects the resistor of the gate resistance group 140 in such a way that the surge voltage of each of the FETs 132 and 134 measured by the voltage measurement device 161 does not exceed the absolute rating of the FET (switching element).

[0031] The conduction time ratio determination unit 79 determines the ratio of the conduction time and the cutoff time of each switching element so that the difference in the heat generation amount of each switching element (FET) measured by the temperature measurement device 163, which is a heat generation amount measurement device, is within a specified range. The conduction time ratio determination unit 79 determines the ratio of the conduction time and the cutoff time of each switching element by selecting the delay elements that make up the conduction time setting unit 150.

[0032] Next, refer to Figure 9The flowchart shown below explains the gate resistance determination process (gate resistance determination operation). The following control is performed based on a program stored in the auxiliary storage unit 83, and the main body of the control is the control unit 80 (CPU 81). In the initial state, the gate resistance group 140 selects the gate resistance Ra141 with the smallest resistance value.

[0033] The voltage measurement device 161 measures the waveform data of the voltage Vds between the drain and source of each of the multiple FETs that make up the switching element group 130, and notifies the inverter adjustment device 75 of the measurement value. The measurement data acquisition unit 77 acquires the waveform data measured by the voltage measurement device 161 (step S11). Figure 10 is an illustrative diagram of the waveform data of the voltage Vds between the drain and source of the FET acquired by the measurement data acquisition unit 77. The voltage Vds between the drain and source usually has a surge voltage (overshoot voltage) surrounded by the dashed line "0" in Figure 10 .

[0034] Next, the gate resistance determination unit 78 determines the resistance of the gate resistance group 140 based on the waveform data of the voltage between the drain and source of the FET acquired by the measurement data acquisition unit 77 (step S12). Specifically, the resistance of the gate resistance group 140 is determined in such a way that Figure 10 the maximum value Vpeak of the surge voltage (overshoot voltage) of the voltage Vds shown does not exceed a reference value with a margin over the absolute rating of the FET.

[0035] Here, with reference to Figures 11 to 14 , the resistance value of the gate resistance group 140 and the waveform data of the voltage Vds between the drain and source of the FET will be described. The signal output from the oscillation circuit 155 is supplied to the gate of the FET via the resistance of the gate resistance group 140. When a high-level signal is applied to the gate of the FET, as charge accumulates in the parasitic capacitance of the gate, the gate voltage gradually rises. The time constant of the rise of the gate voltage is determined by the gate resistance value and the parasitic capacitance of the gate. As the gate voltage rises, the voltage Vds between the drain and source gradually decreases, and the current Ids flowing from the collector to the emitter gradually increases. Due to the characteristics of the coil constituting the inverter 13, the larger the change ratio of this current Ids, the greater the tendency for the maximum value (Vpeak) of the surge voltage of the voltage Vds between the drain and source to increase. That is, there is a correlative relationship between the time constant of the rise of the gate voltage (gate resistance value) and the maximum value Vpeak of the surge voltage.

[0036] Figure 11 Schematically shows the gate voltage of the FET when the resistance value of the gate resistance is small and the rise of the gate voltage is sharp. In this case, as shown in Figure 12 , there is a tendency for the maximum value Vpeak of the surge voltage of Vds of the FET to increase.Figure 13 Schematically represents the gate voltage of an FET when the resistance value of the gate resistor is large and the rise of the gate voltage is not steep. At this time, as Figure 14 shown, the maximum value Vpeak of Vds of the FET is smaller than Figure 12 the maximum value of the surge voltage shown.

[0037] Return Figure 9 , the gate resistor determination unit 78 initially selects the gate resistor Ra141 with the smallest resistance value in the gate resistor group 140. The gate resistor determination unit 78 determines whether the maximum value Vpeak of the surge voltage of the voltage Vds of the FET is above a reference value (step S13). The reference value is set to a value with a margin from the absolute rating of the FET used. When the maximum value Vpeak of the surge voltage of the voltage Vds of the FET is above the reference value (step S13: Yes), the process returns to step S11.

[0038] In the second processing of step S12, the gate resistor determination unit 78 selects the gate resistor Rb142 whose resistance value is only larger than the initial gate resistor Ra141. In the third processing of step S12, the gate resistor determination unit 78 selects the gate resistor Rc143 whose resistance value is only larger than the second gate resistor Rb142. In this way, the gate resistor determination unit 78 selects a gate resistor for which the maximum value Vpeak of the surge voltage of Vds of the FET is less than the reference value. If the gate resistor for which the maximum value Vpeak of the surge voltage is less than the reference value is determined (step S13: No), the process proceeds to step S14.

[0039] Next, the gate resistor determination unit 78 determines whether the gate resistors of all FETs have been determined (step S14). When the determination process of the gate resistors has not been completed for all FETs (step S14: No), the process returns to step S11, and the processes of steps S11 to S13 are performed for the FETs for which the determination process of the gate resistors has not been performed. When the determination process of the gate resistors has been completed for all FETs (step S14: Yes), the gate resistor determination process ends.

[0040] Next, the on-time ratio determination process will be described with reference to the Figure 15 flowchart shown. The following control is performed based on a program stored in the auxiliary storage unit 83, and the main body of the control is the control unit 80 (CPU 81). In the initial state, all on-time setting units 150 connected to the FET via the gate resistor group 140 select the delay element ta151 with the minimum delay time.

[0041] Here, the heat generation of the FET will be described. Figure 16 is the clock supplied to the gate of the FET. Figure 17 The current Ids shown is the current flowing from the drain to the source of the FET.Figure 17 The Vds shown is the voltage between the drain and source of the FET. When the clock is high, the FET is in the on state and the current Ids flows between the drain and source. During Figure 17 the ton period of Figure 17 , the FET is in the on state. Figure 17 The voltage Vds during the ton period of Figure 17 is the on-voltage of the FET, and the current Ids during the ton period is the on-current of the FET. During

[0042] supply Figure 18 the clock supplied to the gate of the FET shown is to Figure 16 only shorten the on-time of the clock shown by the time td. Thus, Figure 19 the on-time ton of the FET shown is shorter than the on-time ton of the FET shown by Figure 17 only the time td. That is, compared with the waveform shown by Figure 17 , the on-time ratio of the FET in the waveform shown by Figure 19 becomes smaller. The smaller the on-time ratio of the FET, the smaller the heat generation amount of the FET. Therefore, Figure 19 the heat generation amount in the case shown by Figure 17 is smaller than the heat generation amount in the case shown by

[0043] The larger the delay time of the delay element selected in the on-time setting unit 150, Figure 18 and Figure 19 the larger the time td shown by

[0044] Return Figure 15 , the measurement data acquisition unit 77 acquires the temperature data measured by the temperature measurement device 163 (step S31). Step S31 is a heat generation amount measurement process for measuring the heat generation amounts of the respective FETs (switching elements). Next, the on-time ratio determination unit 79 determines whether the temperature difference between the parallel-connected switching elements (FETs) is below the threshold value (step S32). In Figure 6 the example shown by

[0045] On the other hand, when the temperature difference between the parallel-connected FETs is not below the threshold (Step S32: No), the conduction time ratio determination unit 79 decreases the conduction time ratio of the clock supplied to the switching element (FET) with the highest supply temperature (Step S33). Step S33 is a conduction time ratio determination step for determining the ratio of the conduction time and the cutoff time of each switching element, so that the difference in the heat generation amount of each switching element measured in the heat generation amount measurement step of Step S31 is within a specified range. Specifically, the conduction time ratio determination unit 79 performs control to switch the delay element of the conduction time setting unit 150 from the delay element ta151 with the minimum delay time to the delay element tb152 with the second-largest delay time. When the delay element of the conduction time setting unit 150 is changed to the delay element tb152, the process returns to Step S31.

[0046] In the process of the second Step S33, control is performed to switch from the delay element tb152 to the delay element tc153 with the second-largest delay time. Here, the case where there are three types of delay elements is taken as an example for explanation, but the type (number) of delay elements is not limited. The process of Steps S31 to S33 is repeated while sequentially switching from the delay element with a small delay time to the delay element with a large delay time. The actually required type of delay element is determined by the degree of deviation of the on-resistance of the FET and the allowable difference in the heat generation amount of the FET, etc.

[0047] For example, the threshold of the temperature difference in Step S32 is set such that the difference in the heat generation amount of the FET is 1% or less. In this case, if the switching frequency of the inverter 13 is set to fs, the difference in the delay time between the delay element ta151 and the delay element tb152 is set to, for example, (1 / (10×fs)). By setting the delay element in this way, the heat generation amount of the FET can be changed by approximately 0.1% each time the delay element is switched.

[0048] When the temperature difference between the parallel-connected FETs is below the threshold (Step S32: Yes), the process ends.

[0049] Figure 9 The gate resistance determination process shown and Figure 15 The conduction time ratio determination process shown are performed during each up and down operation of the car 31.

[0050] As described above, the inverter adjustment device according to the first embodiment includes a conduction time ratio determination unit 79 that determines the ratio of the conduction time and the cutoff time of each switching element so that the difference in the calorific value of each switching element measured by the temperature measurement device 163 (calorific value measurement device) is within a specified range. Thereby, it is possible to reduce the deviation of the load applied to the parallel-connected switching elements and reduce the temperature difference between the parallel-connected switching elements. Therefore, it is possible to suppress a reduction in the lifespan of the inverter having a plurality of parallel-connected switching elements.

[0051] In addition, although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above description, the case where the gate resistance determination process shown in Figure 9 and the conduction time ratio determination process shown in Figure 15 are performed during each ascending and descending operation of the passenger car 31 has been described. However, for example, they may also be performed during each regular inspection.

[0052] In addition, in the above description, the case where the conduction time ratio of the FET is adjusted by controlling the delay time in the conduction time setting unit 150 has been described. However, the method of adjusting the conduction time of the FET is not limited thereto. For example, a plurality of clock generation circuits with different conduction times may be provided, and any clock may be selected.

[0053] In addition, in the above description, the case where the rising speed of the gate voltage is adjusted by changing the gate resistance value has been described. As another method, capacitors with different capacitances may be arranged at the gate of the FET, and a certain capacitor may be selected, or the rising speed of the gate voltage may be adjusted by changing the combination of the parallel-connected capacitors.

[0054] In addition, when the maximum value Vpeak of the surge voltage of the Vds of the FET hardly changes through the conduction time ratio determination process, either one of the above gate resistance determination process and conduction time ratio determination process may be performed first.

[0055] (Modification example) In the description of the first embodiment, the case of adjusting the conduction time ratio of the FET according to the measurement data of the temperature measurement device 163 was described. As another embodiment, the conduction time ratio of the FET may also be adjusted according to the measurement data of the voltage measurement device 161 and the current measurement device 162. In a modified example, the voltage measurement device 161 and the current measurement device 162 constitute a heat generation measurement device. The heat generated by the FET is obtained by multiplying the voltage Vds between the drain and source of the FET measured by the voltage measurement device 161 by the current Ids measured by the current measurement device 162. Therefore, the value obtained by integrating (Vds×Ids) over a specified time corresponds to the temperature measured by the temperature measurement device 163. The specified time is set to about 1 second, for example. By controlling the conduction time setting unit 150 so that the difference in the integrated values of (Vds×Ids) for each switching element is within a specified range, a reduction in the life of an inverter having a plurality of switching elements connected in parallel can be suppressed.

[0056] A specified time is required for the temperature change of the FET. On the one hand, the voltage measurement device 161 and the current measurement device 162 can measure data on the instantaneous changes in the voltage Vds and the current Ids. Therefore, compared with the first embodiment, in some cases, the modified example can adjust the converter 13 in a shorter time. On the other hand, if the heat generation during the transition period of the FET's conduction and cutoff is considered, it should be noted that the integrated value of (Vds×Ids) is not strictly related to the actual temperature of the FET.

[0057] (Second Embodiment) In the first embodiment, a method of extending the life of an inverter having a configuration in which a plurality of switching elements are connected in parallel by equalizing the load applied to the FET by adjusting the delay time of the conduction time setting unit 150 was described. In the second embodiment, a method of equalizing the load applied to the FET by adjusting the gate resistance of the driving switching element to extend the life of an inverter having a configuration in which a plurality of switching elements are connected in parallel will be described.

[0058] In the inverter adjustment device 75 of the second embodiment, Figure 4 and Figure 5 the conduction time setting unit 150 is deleted. In addition, Figure 8 the conduction time ratio determination unit 79 and the conduction time setting unit 150 are deleted.

[0059] Here, the heat generation of the FET will be described. When a high-level signal is applied to the gate of the FET, as charges accumulate in the parasitic capacitance of the base, the base voltage gradually rises. As the base voltage rises, the voltage Vds between the collector and the emitter gradually decreases, and the current Ids flowing from the collector to the emitter gradually increases. When the signal applied to the gate becomes low level, as the charges stored in the parasitic capacitance of the gate discharge, the gate voltage gradually decreases. As the gate voltage decreases, the voltage Vds between the drain and the source gradually rises, and the current Ids flowing from the drain to the source gradually decreases.

[0060] The heat generation of the FET is proportional to the product of the voltage Vds and the current Ids. During the period when the current Ids is completely "0", the FET does not generate heat. Additionally, when the FET is in the conducting state, since the value of the voltage Vds is small (e.g., 0.1V), the heat generation in the FET is small. When the FET is in the transition state from the conducting state to the cutoff state and the transition state from the cutoff state to the conducting state, the value of (Vds × Ids) becomes large, and the heat generation becomes large.

[0061] The smaller the resistance value selected by the gate resistor group 140, the more rapid the rise and fall changes of the gate voltage of the FET, the shorter the period of the transition state of the FET from the conducting state to the cutoff state and the transition state from the cutoff state to the conducting state, and the smaller the heat generation of the FET. On the other hand, the larger the resistance value selected by the gate resistor group 140, the slower the rise and fall changes of the gate voltage of the FET, the longer the period of the transition state of the FET from the conducting state to the cutoff state and the transition state from the cutoff state to the conducting state, and the larger the heat generation of the FET.

[0062] Next, with reference to Figure 20 the flowchart shown, the second gate resistor determination process will be described. Here, the determination process of the minimum value of the gate resistor described using Figure 8 etc. is referred to as the first gate resistor determination process. The description of the first gate resistor determination process is the same as the description in Embodiment 1. The minimum value of the gate resistor is determined by the first gate resistor determination process. Figure 20 The descriptions of step S51 and step S52 shown are the same as the descriptions of step S31 and step S32 in Embodiment 1.

[0063] The gate resistor determination unit 78 increases the resistance value of the gate resistor connected to the FET with the lowest temperature (step S53). For example, when the gate resistor Ra141 with the smallest resistance value is selected in the first gate resistor determination process, the gate resistor Rb142 with the second largest resistance value is selected. Then, the process returns to step S51.

[0064] In the process of step S53 in the second time, control is performed to switch from the gate resistor Rb142 to the gate resistor Rc143 with the second largest resistance value. Here, the case where there are three types of gate resistance values has been described as an example, but the types of gate resistors are not limited. While sequentially switching to gate resistors with larger resistance values, the processes of step S51 to step S53 are repeated. By repeating the processes of step S51 to step S53, the temperature difference of the FETs connected in parallel becomes below the threshold value.

[0065] Although some embodiments of the present invention have been described, these embodiments are given as examples and are not intended to limit the scope of the present invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Claims

1. An inverter adjustment device, characterized in that: In an inverter formed by connecting a plurality of switching elements in parallel, the inverter adjustment device includes: a heat generation measuring device for measuring the heat generation of each of the switching elements; and The on-time ratio determination unit determines the ratio of the on-time to the off-time of each of the switching elements so that the difference in the amount of heat of each of the switching elements measured by the heat generation measurement device is within a predetermined range.

2. The inverter adjustment device according to claim 1, characterized in that: have: a voltage measuring device for measuring a switching voltage of each of the switching elements; A gate resistor group, which is respectively arranged on the switch elements and can selectively include a plurality of resistors with different resistance values; as well as A gate resistance determination unit selects the resistance of the gate resistance group so that the maximum value of the surge voltage of each of the switching elements measured by the voltage measurement device does not exceed a preset reference value.

3. An inverter adjustment device, characterized in that: In an inverter formed by connecting a plurality of switching elements in parallel, the inverter adjustment device includes: A gate resistor group, which is respectively arranged on the switch elements and can selectively include a plurality of resistors with different resistance values; a heat generation measuring device for measuring the heat generation of each of the switching elements; as well as A gate resistance determination unit selects resistances of the gate resistance group so that a difference in the amount of heat generated by each of the switching elements measured by the heat generation measurement device falls within a predetermined range.

4. The inverter adjustment device according to claim 3, characterized in that: A voltage measuring device is provided for measuring the switching voltage of each of the switching elements, The gate resistance determination unit selects the resistance of the gate resistance group so that the maximum value of the surge voltage of each of the switching elements measured by the voltage measurement device does not exceed a preset reference value.

5. The inverter adjustment device according to any one of claims 1 to 4, characterized in that: The calorific value measuring device is composed of a voltage measuring device and a current measuring device or a temperature measuring device.

6. An inverter adjustment method, characterized in that: In an inverter formed by connecting a plurality of switching elements in parallel, the inverter adjustment method comprises: a heating value measuring step of measuring the heating value of each of the switching elements; and The on-time ratio determining step determines the ratio of the on-time to the off-time of each of the switching elements so that the difference in the amount of heat of each of the switching elements measured in the calorific value measuring step is within a predetermined range.

7. An inverter adjustment method, characterized in that: In an inverter formed by connecting a plurality of switching elements in parallel, the inverter adjustment method comprises: a heating value measuring step of measuring the heating value of each of the switching elements; and The gate resistance determination step selects one resistor from a gate resistance group consisting of a plurality of resistors having different resistance values ​​provided on the switching element so that the difference in the heat generation of each of the switching elements measured in the heat generation measurement step is within a predetermined range.

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