Semiconductor memory device

Abstract

A semiconductor memory device includes a dummy stack structure, an insulating chip protection pattern penetrating a lower portion of the dummy stack structure, and a conductive chip protection pattern penetrating a lower portion of the dummy stack structure. And the conductive chip protection pattern is aligned with the insulating chip protection pattern over the insulating chip protection pattern and penetrates an upper portion of the dummy stack structure.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices. Background Art

[0002] Semiconductor memory devices are applied to electronic systems in various fields (including automobiles, medical devices, data centers, etc.) in addition to small electronic devices. Therefore, the demand for semiconductor memory devices is increasing day by day.

[0003] A semiconductor memory device may include memory cells for data storage. A three-dimensional semiconductor memory device includes memory cells arranged three-dimensionally, which is advantageous for large-capacity storage compared to a two-dimensional semiconductor memory device.

[0004] The integration degree of a three-dimensional semiconductor device can be improved by increasing the number of stacked layers of memory cells (i.e., the number of memory cells in each memory cell string). As the number of stacked layers of memory cells increases, the stability of the manufacturing process may deteriorate. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a semiconductor memory device includes: a lower structure including a circuit region and a chip protection region surrounding the circuit region; a memory cell array structure overlapping a first region of the circuit region of the lower structure; a conductive vertical contact structure overlapping a second region of the circuit region of the lower structure; a dummy stack structure stacked above the chip protection region of the lower structure; an insulating chip protection pattern penetrating a lower portion of the dummy stack structure; and a conductive chip protection pattern aligned with the insulating chip protection pattern above the insulating chip protection pattern and penetrating an upper portion of the dummy stack structure.

[0006] According to an embodiment of the present disclosure, a semiconductor memory device includes: a lower structure including a circuit region and a chip protection region surrounding the circuit region; a memory cell array structure overlapping a first region of the circuit region of the lower structure; a conductive vertical contact structure overlapping a second region of the circuit region of the lower structure; a dummy stack structure stacked above the chip protection region of the lower structure; an insulating chip protection pattern penetrating a part of the dummy stack structure; and a conductive chip protection pattern penetrating a different part of the dummy stack structure to contact the insulating chip protection pattern. Brief Description of the Drawings

[0007] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0008] In the drawings, for clarity of illustration, the dimensions may be exaggerated. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or there can be one or more intervening elements. Like reference numerals always refer to like elements.

[0009] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 3 is a plan view illustrating a circuit region and a chip protection region of a first structure according to an embodiment of the present disclosure.

[0012] Figure 4 is a circuit diagram of a memory cell array structure according to an embodiment of the present disclosure.

[0013] Figure 5A 、 Figure 5B and Figure 5C are diagrams illustrating a memory cell array structure according to an embodiment of the present disclosure.

[0014] Figure 6A and Figure 6B are diagrams illustrating a peripheral contact structure and a chip protection structure according to an embodiment of the present disclosure.

[0015] Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10 、 Figure 11A 、 Figure 12 、 Figure 13A 、 Figure 14 、 Figure 15 and Figure 16 are cross-sectional views illustrating a process of forming a memory cell array structure according to an embodiment of the present disclosure.

[0016] Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 11B 、 Figure 13B 、 Figure 17 、Figure 18 and Figure 19 is a cross-sectional view illustrating a process of forming a peripheral contact structure and a chip protection structure according to an embodiment of the present disclosure.

[0017] Figure 20 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Embodiments

[0018] The specific structures and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be modified in various forms and replaced by other equivalent embodiments. Therefore, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0019] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and the order or number of components is not limited by these terms.

[0020] Embodiments provide a semiconductor memory device capable of improving the stability of a manufacturing process.

[0021] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Referring to Figure 1 , the semiconductor memory device 50 may include a peripheral circuit 40 and a memory cell array 10.

[0023] The peripheral circuit 40 may be configured to perform a programming operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. In an embodiment, the peripheral circuit 40 may include an input / output circuit 21, a control circuit 23, a voltage generation circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0024] The memory cell array 10 may include a plurality of memory cells in which data is stored. The memory cells may be three-dimensionally arranged. The memory cell array 10 may be connected to a drain select group DSL, a word line group WL, a source select group SSL, a plurality of bit lines BL, and a common source line CSL.

[0025] The input / output circuit 21 can transfer the command CMD and the address ADD to the control circuit 23. The command CMD and the address ADD can be transferred from an external device (e.g., a memory controller) of the semiconductor memory device 50. The input / output circuit 21 can exchange data DATA with the external device and the column decoder 35.

[0026] The control circuit 23 can output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

[0027] The voltage generation circuit 31 can generate various operation voltages Vop for programming operations, read operations, and erase operations in response to the operation signal OP_S.

[0028] The row decoder 33 can transfer the operation voltage Vop to the drain select group DSL, the word line group WL, and the source select group SSL in response to the row address RADD.

[0029] The column decoder 35 can send the data DATA input from the input / output circuit 21 to the page buffer 37 in response to the column address CADD. The column decoder 35 can send the data DATA stored in the page buffer 37 to the input / output circuit 21 in response to the column address CADD. The column decoder 35 can exchange data DATA with the input / output circuit 21 through the column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 through the data line DL.

[0030] The page buffer 37 can store the data DATA received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 can sense the voltage or current of the bit line BL in a read operation.

[0031] The source line driver 39 can control the voltage applied to the common source line CSL in response to the source line control signal SL_S.

[0032] Figure 2 is an illustration of a perspective view of a semiconductor memory device according to an embodiment of the present disclosure.

[0033] Referring to Figure 2 , the semiconductor memory device can include a first structure ST1 and a second structure ST2. The first structure ST1 can overlap with the second structure ST2.

[0034] Each of the first structure ST1 and the second structure ST2 can include a circuit structure and a chip protection structure surrounding the circuit structure, and the circuit structure includes the circuits of the semiconductor memory device.

[0035] The circuit structure of the first structure ST1 may include a memory cell array structure, a doped semiconductor structure connected to the memory cell array structure, a plurality of bit lines connected to the memory cell array structure, an interconnect connected to the memory cell array structure, and a peripheral contact structure separated from the memory cell array structure. The memory cell array structure includes Figure 1 the memory cell array 10 shown. The circuit structure of the second structure ST2 may include a peripheral circuit structure and an interconnect connected to the peripheral circuit structure. The peripheral circuit structure includes Figure 1 the peripheral circuit 40 shown. The peripheral contact structure of the first structure ST1 may be connected to a part of the interconnect of the second structure ST2. The interconnect in each of the first structure ST1 and the second structure ST2 may include various conductive structures such as conductive contact plugs, conductive wires, conductive bonding pads, etc.

[0036] The chip protection structure in each of the first structure ST1 and the second structure ST2 may reduce the chance of contaminants infiltrating into the circuit structure and / or the amount of contaminants infiltrating into the circuit structure. The chip protection structure of the first structure ST1 may overlap with the chip protection structure of the second structure ST2.

[0037] Figure 3 is a plan view illustrating a circuit region and a chip protection region of a first structure according to an embodiment of the present disclosure.

[0038] Referring to Figure 3 , the circuit region CIR of the first structure ST1 may include a first region CER and a second region PCR. The first region CER may be a region where the memory cell array structure is provided. The second region PCR may be a region where the peripheral contact structure is provided.

[0039] The chip protection region CGR may surround the circuit region CIR. The chip protection structure may be formed along the chip protection region CGR.

[0040] Figure 4 is a circuit diagram of a memory cell array structure according to an embodiment of the present disclosure.

[0041] Referring to Figure 4 , the memory cell array structure may include a storage block BLK. Each storage block BLK may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may each be connected to a common source layer CSR, a bit line BL, a plurality of word lines WL1 to WLn (n is a natural number of 2 or greater), and a plurality of selection lines SSL1A, SSL2A, SSL1B, SSL2B, DSL1, and DSL2.

[0042] A voltage for precharging the channel layer of the corresponding memory cell string CS can be applied to the bit line BL. A voltage for discharging the potential of the channel layer of the memory cell string CS can be applied to the common source layer CSR. Each memory cell string CS can be connected to the Figure 1 common source line CSL shown.

[0043] A plurality of memory cell strings CS can be connected in parallel to the common source layer CSR. The plurality of memory cell strings CS can be divided into a plurality of columns and a plurality of rows. The memory cell strings of the column corresponding to the bit line BL can be connected in parallel to the bit line BL. The memory cell strings of the row corresponding to each of the plurality of word lines WL1 to WLn can be connected in parallel to each of the plurality of word lines WL1 to WLn. Figure 4 Illustrated are memory cell strings of any column connected to the same bit line BL.

[0044] Each memory cell string CS can include a plurality of memory cells MC1 to MCn connected in series through a channel layer. Each memory cell string CS can further include at least one drain select transistor connected to the bit line BL and at least one source select transistor connected to the common source layer CSR. In an embodiment, each memory cell string CS can include a first source select transistor SST1 connected to the common source layer CSR, a second source select transistor SST2 connected in series to the first source select transistor SST1, a first drain select transistor DST1 connected in series to the plurality of memory cells MC1 to MCn, and a second drain select transistor DST2 connected between the first drain select transistor DST1 and the bit line BL. Although the following description is based on an embodiment in which each memory cell string CS includes the first source select transistor SST1, the second source select transistor SST2, the plurality of memory cells MC1 to MCn, the first drain select transistor DST1, and the second drain select transistor DST2 connected in series, the embodiments of the present disclosure are not limited thereto.

[0045] A plurality of selection lines SSL1A, SSL2A, SSL1B, SSL2B, DSL1, and DSL2 may be divided into source selection groups SSL1A, SSL2A, SSL1B, and SSL2B, and drain selection groups DSL1 and DSL2. A plurality of word lines WL1 to WLn may be provided between the source selection groups SSL1A, SSL2A, SSL1B, and SSL2B and the drain selection groups DSL1 and DSL2. The source selection groups SSL1A, SSL2A, SSL1B, and SSL2B may include a first source selection line SSL1A or SSL1B connected to a gate of a first source selection transistor SST1, and a second source selection line SSL2A or SSL2B connected to a gate of a second source selection transistor SST2. The drain selection groups DSL1 and DSL2 may include a first drain selection line DSL1 connected to a gate of a first drain selection transistor DST1, and a second drain selection line DSL2 connected to a gate of a second drain selection transistor DST2. The plurality of word lines WL1 to WLn may be connected to the plurality of gates of the plurality of memory cells MC1 to MCn, respectively.

[0046] The memory cell strings CS connected to the same bit line BL may be part of the same column group. Each of the plurality of word lines WL1 to WLn may be designed to jointly control the memory cell strings CS of the same column group. At least one of the source selection groups SSL1A, SSL2A, SSL1B, and SSL2B and the drain selection groups DSL1 and DSL2 may be designed to individually control the memory cell strings CS of the same column group.

[0047] In an embodiment, the memory block BLK may include a first memory cell string CS1 and a second memory cell string CS2 connected to the same bit line BL. In order to control the first memory cell string CS1 and the second memory cell string CS2, each of the plurality of word lines WL1 to WLn may be commonly connected to the first memory cell string CS1 and the second memory cell string CS2. In order to individually control the first memory cell string CS1 and the second memory cell string CS2, the source selection group may be isolated into a first group and a second group, the first group including a first source selection line SSL1A and a second source selection line SSL2A connected to the first memory cell string CS1, and the second group including a first source selection line SSL1B and a second source selection line SSL2B connected to the second memory cell string CS2. In order to control the first memory cell string CS1 and the second memory cell string CS2, each of the first drain selection line DSL1 and the second drain selection line DSL2 may be commonly connected to the first memory cell string CS1 and the second memory cell string CS2.

[0048] Figure 5A , Figure 5B andFigure 5C FIG. is a diagram illustrating a memory cell array structure according to an embodiment of the present disclosure. Figure 5A FIG. is a plan view illustrating the memory cell array structure, Figure 5B which is Figure 5A a cross-sectional view of the memory cell array structure taken along the line I-I’ shown, and Figure 5C FIG. is Figure 5B an enlarged cross-sectional view of the region “AR1” shown.

[0049] Referring to Figure 5A , the memory cell array structure CAS may include a plurality of gate stack structures GST, and the plurality of gate stack structures GST are separated by slits SI. In an embodiment, a slit SI may be formed between consecutive gate stack structures. Specifically, a slit SI may be formed between a first gate stack structure GST1 and a second gate stack structure GST2, and between the second gate stack structure GST2 and a third gate stack structure GST3.

[0050] Each gate stack structure GST may include a word line group WL, a drain select group DSL, a first group SSL_A of source select lines, and a second group SSL_B of source select lines. The first group SSL_A of source select lines and the second group SSL_B of source select lines may be isolated from each other by a select line isolation insulating layer SLI.

[0051] Each gate stack structure GST may be penetrated by a plurality of pillar structures PS1 and PS2. The plurality of pillar structures PS1 and PS2 may be arranged in a zigzag form. The plurality of pillar structures PS1 and PS2 may include a first pillar structure PS1 disposed on both sides of the select line isolation insulating layer SLI and a second pillar structure PS2 overlapping the select line isolation insulating layer SLI. The first pillar structure PS1 may be used as a cell pillar defining a memory cell string. The second pillar structure PS2 may be used as a cell pillar defining a memory cell string, or may be used as a dummy pillar that does not participate in the operation of the memory cell string.

[0052] Referring to Figure 5B , each gate stack structure GST may overlap a lower structure LS. The lower structure LS may include a doped semiconductor structure 100.

[0053] Referring to Figure 3 and Figure 5B, a doped semiconductor structure 100 may be disposed in a first region CER of a circuit region CIR of a lower structure LS. The doped semiconductor structure 100 may include at least one doped semiconductor layer. The doped semiconductor structure 100 may include at least one of an n-type impurity and a p-type impurity. The doped semiconductor structure 100 may include at least one of the following: a first conductivity type doped region including an n-type impurity as majority carriers and a second conductivity type doped region including a p-type impurity as majority carriers. The first conductivity type doped region may be disposed with reference to Figure 4 the common source layer CSR described, and the second conductivity type doped region may be disposed as a well region.

[0054] In an embodiment, the doped semiconductor structure 100 may include a first semiconductor layer 101, a second semiconductor layer 109, and a channel contact semiconductor layer 151. The channel contact semiconductor layer 151 may be disposed between the first semiconductor layer 101 and the second semiconductor layer 109. The first semiconductor layer 101, the second semiconductor layer 109, and the channel contact semiconductor layer 151 may be used as a reference Figure 4 the common source layer CSR described. Each of the first semiconductor layer 101, the second semiconductor layer 109, and the channel contact semiconductor layer 151 disposed as the common source layer CSR may include an n-type impurity as majority carriers.

[0055] The doped semiconductor structure 100 may be covered with a first interlayer insulating layer 115. A gate stack structure GST may be disposed above the doped semiconductor structure 100, and the first interlayer insulating layer 115 is interposed between the gate stack structure GST and the doped semiconductor structure 100. The gate stack structure GST may include a plurality of conductive layers 117A, 117B, and 117C, and a plurality of second interlayer insulating layers 119CA, 119CB, and 119CC. The conductive layers 117A, 117B, and 117C and the second interlayer insulating layers 119CA, 119CB, and 119CC may be alternately stacked above the first interlayer insulating layer 115. Each of the conductive layers 117A, 117B, and 117C may include various conductive materials such as a doped semiconductor layer and a metal layer. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the conductive layers 117A, 117B, and 117C may further include a conductive metal nitride layer. The conductive metal nitride layer may include titanium nitride, tantalum nitride, etc. Each of the first interlayer insulating layer 115 and the second interlayer insulating layers 119CA, 119CB, and 119CC may include an oxide, such as a silicon oxide layer and a silicon oxynitride layer.

[0056] At least one lower conductive layer (e.g., 117A) among the plurality of conductive layers 117A, 117B, and 117C that is closest to the lower structure LS can be penetrated by the select line isolation insulating layer SLI. Accordingly, the lower conductive layer 117A can be isolated into select lines. In an embodiment, two lower conductive layers 117A adjacent to the doped semiconductor structure 100 can be isolated into a first group SSL_A and a second group SSL_B. The first group SSL_A includes a first source select line SSL1A and a second source select line SSL2A, and the second group SSL_B includes a first source select line SSL1B and a second source select line SSL2B. Other conductive layers 117B and 117C other than the two lower conductive layers 117A can be used as a word line group and a drain select group DSL. The word line group includes a plurality of word lines WL1 to WLn, and the drain select group DSL includes a first drain select line DSL1 and a second drain select line DSL2.

[0057] The gate stack structure GST can be covered with a third interlayer insulating layer 131. The slit SI can penetrate the third interlayer insulating layer 131 and can be disposed between the continuous gate stack structures GST. The slit SI can extend to penetrate the first interlayer insulating layer 115 and the second semiconductor layer 109. The filler disposed in the slit SI can be diverse. In an embodiment, the filler can include an insulating layer. In another embodiment, the filler can include at least one of a conductive layer and a semiconductor layer in addition to the insulating layer.

[0058] Each pillar structure PS can include a multilayer 121 and a channel layer 123.

[0059] The channel layer 123 can penetrate the gate stack structure GST. The channel layer 123 can extend to penetrate the first interlayer insulating layer 115 and the third interlayer insulating layer 131. The channel layer 123 can extend into the doped semiconductor structure 100 and can contact the doped semiconductor structure 100. The contact surface between the channel layer 123 and the doped semiconductor structure 100 can be differently defined at the sidewall portion, the end portion, etc. of the channel layer 123. In an embodiment, the channel layer 123 can include sidewalls surrounded by a channel contact semiconductor layer 151, and the sidewalls of the channel layer 123 can contact the channel contact semiconductor layer 151. To this end, the channel layer 123 can penetrate the second semiconductor layer 109 and can extend into the first semiconductor layer 101. The channel layer 123 can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof that can be used as a channel region of a memory cell string.

[0060] The multi-layer 121 can extend along the outer wall of the channel layer 123. The multi-layer 121 can be isolated by the channel contact semiconductor layer 151 into a memory layer 121M and a dummy memory layer 121D. The memory layer 121M can be the part of the multi-layer 121 inserted between the gate stack structure GST and the channel layer 123, and the dummy memory layer 121D can be the part of the multi-layer 121 inserted between the first semiconductor layer 101 and the channel layer 123.

[0061] The memory layer 121M can extend along the side wall of the channel layer 123 to be inserted between each of the plurality of conductive layers 117A, 117B, and 117C and the channel layer 123. The memory layer 121M can extend to between the second semiconductor layer 109 and the channel layer 123.

[0062] Referring to Figure 5B and Figure 5C , the multi-layer 121 can include a tunnel insulating layer 121TI, a data storage layer 121DS, and a blocking insulating layer 121BI. The data storage layer 121DS can be formed of a material layer capable of storing data changed by Fowler-Nordheim tunneling. In an embodiment, the data storage layer 121DS can be formed of a charge trapping insulating layer, a floating gate layer, or an insulating layer including conductive nanodots. The charge trapping insulating layer can include a silicon nitride layer. The tunnel insulating layer 121TI can be disposed between the data storage layer 121DS and the channel layer 123. The tunnel insulating layer 121TI can include an insulating material, such as a silicon oxide layer. The blocking insulating layer 121BI can extend along the outer wall of the data storage layer 121DS. The blocking insulating layer 121BI can include at least one of a silicon oxide layer and a high-k layer. The high-k layer can include an aluminum oxide layer, etc., each of which has a dielectric constant higher than that of the silicon oxide layer.

[0063] The column structure PS can further include a core insulating layer 125 and a covering pattern 127. The core insulating layer 125 and the covering pattern 127 can be disposed in the central region of the column structure PS. The covering pattern 127 can be disposed on the core insulating layer 125. The channel layer 123 can extend along the outer wall of the core insulating layer 125 and the side wall of the covering pattern 127. The covering pattern 127 can be formed of a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. In an embodiment, the covering pattern 127 can include doped silicon, and the doped silicon includes an n-type impurity as the majority carrier.

[0064] Figure 6A and Figure 6B are diagrams illustrating a peripheral contact structure and a chip protection structure according to an embodiment of the present disclosure. Figure 6A is a plan view illustrating the peripheral contact structure and the chip protection structure, andFigure 6B is a cross-sectional view of a peripheral contact structure and a chip protection structure taken along line II-II’ shown in Figure 6A .

[0065] Referring to Figure 6A , the peripheral contact structure PCT can be disposed in a second region PCR of a circuit region CIR of a first structure ST1 shown in Figure 3 . The chip protection structure CG can be disposed in a chip protection region CGR of the first structure ST1.

[0066] The chip protection structure CG can include an insulating chip protection pattern GP1 and a conductive chip protection pattern GP2. The insulating chip protection pattern GP1 and the conductive chip protection pattern GP2 can be disposed inside a dummy stacked structure DMST. The dummy stacked structure DMST can extend to surround the peripheral contact structure PCT.

[0067] Referring to Figure 3 and Figure 6B , the lower structure LS can further include an insulating structure 110. The insulating structure 110 can be disposed in the second region PCR in the circuit region CIR and can extend to the chip protection region CGR. The lower structure LS can include a lower conductive contact structure LCT and a lower conductive chip protection pattern LGP, and the lower conductive contact structure LCT and the lower conductive chip protection pattern LGP each penetrate the insulating structure 110. The lower conductive contact structure LCT can be a part of the peripheral contact structure PCT. The lower conductive contact structure LCT can be disposed in the second region PCR of the circuit region CIR. The lower conductive chip protection pattern LGP can be a part of the chip protection structure CG. The lower conductive chip protection pattern LGP can be disposed in the chip protection region CGR.

[0068] Referring to Figure 5B and Figure 6B , the insulating structure 110 can be disposed at substantially the same height as the doped semiconductor structure 100. The first interlayer insulating layer 115 can extend to cover the insulating structure 110.

[0069] Referring to Figure 6A and Figure 6B , the dummy stacked structure DMST can overlap with the chip protection region CGR of the lower structure LS and can extend to overlap with the second region PCR of the lower structure LS. The dummy stacked structure DMST can be disposed above the lower structure LS, and the first interlayer insulating layer 115 is interposed between the dummy stacked structure DMST and the lower structure LS. The dummy stacked structure DMST can include a plurality of dummy layers 116A, 116B, and 116C and a plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC, which are alternately stacked above the first interlayer insulating layer 115.

[0070] Referring to Figure 5B and Figure 6B Figure 6B , the dummy stack structure DMST can be disposed at substantially the same height as the gate stack structure GST. The plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC can be disposed at substantially the same height as the plurality of second interlayer insulating layers 119CA, 119CB, and 119CC, and can be formed of substantially the same insulating material as the plurality of second interlayer insulating layers 119CA, 119CB, and 119CC. In an embodiment, the plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC can include an oxide, such as a silicon oxide layer or a silicon oxynitride layer. The plurality of dummy layers 116A, 116B, and 116C can be disposed at substantially the same height as the plurality of conductive layers 117A, 117B, and 117C. The plurality of dummy layers 116A, 116B, and 116C can be formed of an insulating material having an etching selectivity with respect to the plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC. In an embodiment, the plurality of dummy layers 116A, 116B, and 116C can include a nitride, such as a silicon nitride layer. The third interlayer insulating layer 131 can extend to cover the dummy stack structure DMST.

[0071] Referring to Figure 6A and Figure 6B Figure 6B , the lower conductive chip protection pattern LGP, the insulating chip protection pattern GP1, and the conductive chip protection pattern GP2 of the chip protection structure CG can be aligned in a straight line in the vertical direction. The vertical direction can be defined as the stacking direction of the plurality of dummy layers 116A, 116B, and 116C and the plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC. The insulating chip protection pattern GP1 can penetrate the lower part of the dummy stack structure DMST and the first interlayer insulating layer 115, and the conductive chip protection pattern GP2 can penetrate the upper part of the dummy stack structure DMST and the third interlayer insulating layer 131.

[0072] Referring to Figure 5B and Figure 6B, the lower part of the dummy stack structure DMST may include the lower dummy layer 116A among the plurality of dummy layers 116A, 116B, and 116C and the lower dummy interlayer insulating layer 119DA among the plurality of dummy interlayer insulating layers 119DA, 119DB, and 119DC. The lower dummy layer 116A and the lower dummy interlayer insulating layer 119DA may be associated with the lower conductive layer 117A and the lower second interlayer insulating layer 119CA, and the lower conductive layer 117A and the lower second interlayer insulating layer 119CA are penetrated by the selection line isolation insulating layer SLI. The lower dummy layer 116A may be disposed at substantially the same height as the lower conductive layer 117A, and the lower dummy interlayer insulating layer 119DA may be disposed at substantially the same height as the lower second interlayer insulating layer 119CA.

[0073] The insulating chip protection pattern GP1 may be associated with the selection line isolation insulating layer SLI. The insulating chip protection pattern GP1 may be formed using the process for forming the selection line isolation insulating layer SLI. The insulating chip protection pattern GP1 may have sidewalls overlapping with the selection line isolation insulating layer SLI and may be disposed at substantially the same height as the selection line isolation insulating layer SLI. In addition, the insulating chip protection pattern GP1 and the selection line isolation insulating layer SLI may include substantially the same material. The insulating chip protection pattern GP1 may include a first end in contact with the lower conductive chip protection pattern LGP and a second end in contact with the conductive chip protection pattern GP2.

[0074] Referring to Figure 5B and Figure 6B , the upper part of the dummy stack structure DMST may include the other dummy layers 116B and 116C except for the lower dummy layer 116A and the other dummy interlayer insulating layers 119DB and 119DC except for the lower dummy interlayer insulating layer 119DA. The conductive chip protection pattern GP2 may be aligned with the insulating chip protection pattern GP1 above the insulating chip protection pattern GP1 and may penetrate the upper part of the dummy stack structure DMST by penetrating the dummy layers 116B and 116C and the dummy interlayer insulating layers 119DB and 119DC.

[0075] Referring to Figure 6B , the peripheral contact structure PCT may further include a conductive vertical contact structure VCT. The conductive vertical contact structure VCT may be aligned with the lower conductive contact structure LCT above the lower conductive contact structure LCT. The conductive vertical contact structure VCT may extend away from the lower conductive contact structure LCT in the vertical direction to penetrate the third interlayer insulating layer 131. The conductive vertical contact structure VCT may have sidewalls overlapping with the insulating chip protection pattern GP1 and the conductive chip protection pattern GP2. The dummy stack structure DMST may extend to surround the conductive vertical contact structure VCT.

[0076] The insulating layer IL1 can be inserted between the conductive vertical contact structure VCT and the dummy stacked structure DMST, and the insulating layer IL2 can be inserted between the conductive chip protection pattern GP2 and the dummy stacked structure DMST.

[0077] Referring to Figure 6A and Figure 6B , each of the insulating chip protection pattern GP1 and the conductive chip protection pattern GP2 of the chip protection structure GP can be formed in a linear shape in a plane. When forming the linear chip protection structure GP, after performing the process of forming the lower part of the dummy stacked structure DMST and the process of forming the insulating chip protection pattern GP1 that penetrates the lower part of the dummy stacked structure DMST, the process of forming the upper part of the dummy stacked structure DMST and the process of forming the conductive chip protection pattern GP2 that penetrates the upper part of the dummy stacked structure DMST can be performed. Therefore, although the height of the dummy stacked structure DMST increases, process failures where the chip protection structure CG is not provided in the lower part of the dummy stacked structure DMST can be reduced.

[0078] Figure 7A , Figure 8A , Figure 9A , Figure 10 , Figure 11A , Figure 12 , Figure 13A , Figure 14 , Figure 15 and Figure 16 are cross-sectional views illustrating a process of forming a memory cell array structure according to an embodiment of the present disclosure.

[0079] Figure 7B , Figure 8B , Figure 9B , Figure 11B , Figure 13B , Figure 17 , Figure 18 and Figure 19 are cross-sectional views illustrating a process of forming a peripheral contact structure and a chip protection structure according to an embodiment of the present disclosure.

[0080] Although not shown in the figures, the following processes can be performed above a sacrificial substrate such as a silicon wafer, or can be performed above a semiconductor substrate including the second structure ST2 described with reference to Figure 2 .

[0081] Referring to Figure 7A and Figure 7B, the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 may be sequentially stacked on a sacrificial substrate (not shown) or a semiconductor substrate including a second structure (not shown). The first protective layer 203 and the second protective layer 207 may include a material having an etching selectivity with respect to the first semiconductor layer 201, the second semiconductor layer 209, and the source sacrificial layer 205. The source sacrificial layer 205 may include a material having an etching selectivity with respect to the first semiconductor layer 201 and the second semiconductor layer 209. In an embodiment, the first semiconductor layer 201 and the second semiconductor layer 209 may include a doped silicon layer including at least one of an n-type impurity and a p-type impurity. The first protective layer 203 and the second protective layer 207 may include an oxide layer, and the source sacrificial layer 205 may include an undoped silicon layer or a nitride layer.

[0082] Subsequently, a portion of each of the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 may be etched. Accordingly, the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 may remain as a preliminary doped semiconductor structure in a first region of the circuit region, as Figure 7A shown. In addition, the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 may be removed in a second region of the circuit region and the chip protection region.

[0083] Subsequently, an insulating structure 210 is formed in the region where the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 are removed, and then, a lower conductive contact structure 211A and a lower conductive chip protection pattern 211B penetrating the insulating structure 210 may be formed.

[0084] The first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 of the preliminary doped semiconductor structure, the insulating structure 210, the lower conductive contact structure 211A, and the lower conductive chip protection pattern 211B may form a preliminary lower structure. A first interlayer insulating layer 215 may be formed above the preliminary lower structure.

[0085] Thereafter, a first material layer 216A and a second material layer 219A may be alternately stacked over the first interlayer insulating layer 215. The first material layer 216A may include a material having an etching selectivity relative to the second material layer 219A, and the second material layer 219A may include an insulating material. In an embodiment, the first material layer 216A may include a nitride, such as a silicon nitride layer, and the second material layer 219A may include an oxide, such as a silicon oxide layer.

[0086] Referring to Figure 8A and Figure 8B , a process for forming the select line isolation insulating layer 220A may be used to form the insulating chip protection pattern 220B. The select line isolation insulating layer 220A may penetrate the first material layer 216A and the second material layer 219A that overlap with the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 of the preliminary doped semiconductor structure, and may extend to penetrate the first interlayer insulating layer 215. The insulating chip protection pattern 220B may penetrate the first material layer 216A and the second material layer 219A that overlap with the lower conductive chip protection pattern 211B, and may extend to penetrate the first interlayer insulating layer 215.

[0087] Referring to Figure 9A and Figure 9B , after forming the select line isolation insulating layer 220A and the insulating chip protection pattern 220B, a plurality of third material layers 219B and a plurality of fourth material layers 216B may be alternately stacked over the stacked structure of the first material layer 216A and the second material layer 219A. Subsequently, a fifth material layer 216C and a sixth material layer 219C may be alternately stacked over the stacked structure of the plurality of third material layers 219B and the plurality of fourth material layers 216B. The plurality of fourth material layers 216B and the fifth material layer 216C may include the same material as the first material layer 216A, and the plurality of third material layers 219B and the sixth material layer 219C may include the same material as the second material layer 219A. A part of each of the second material layer 219A, the plurality of third material layers 219B, and the sixth material layer 219C may correspond to the second interlayer insulating layer described with reference to Figure 5B , and another part of each of the second material layer 219A, the plurality of third material layers 219B, and the sixth material layer 219C may correspond to the dummy interlayer insulating layer described with reference to Figure 6B .

[0088] Subsequently, a mask layer 301 may be formed over the stacked structure of the fifth material layer 216C and the sixth material layer 219C.

[0089] Referring to Figure 10, after forming a plurality of openings in the mask layer 301, the first material layer 216A, the second material layer 219A, the plurality of third material layers 219B, the plurality of fourth material layers 216B, the fifth material layer 216C, and the sixth material layer 219C can be etched through the plurality of openings. Additionally, the first interlayer insulating layer 215, the second semiconductor layer 209, the second protective layer 207, the source sacrificial layer 205, the first protective layer 203, and the first semiconductor layer 201 can be etched through the plurality of openings in sequence. Accordingly, a plurality of channel holes can be formed. Each channel hole can penetrate the mask layer 301, the first material layer 216A, the second material layer 219A, the plurality of third material layers 219B, the plurality of fourth material layers 216B, the fifth material layer 216C, the sixth material layer 219C, the first interlayer insulating layer 215, the second semiconductor layer 209, the second protective layer 207, the source sacrificial layer 205, and the first protective layer 203, and can extend into the first semiconductor layer 201.

[0090] Subsequently, a multilayer 221 can be formed on the surface of the channel holes. The multilayer 221 can include a barrier insulating layer, a data storage layer, and a tunneling insulating layer as described with reference to Figure 5C . Then, a channel layer 223 can be formed on the inner wall of the multilayer 221. The channel layer 223 can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The central region of the channel hole opened by the channel layer 223 can be filled with a core insulating layer 225 and a covering pattern 227. The covering pattern 227 can include a doped semiconductor layer.

[0091] With reference to Figure 11A and Figure 11B , the mask layer 301 shown in Figure 10 can be removed. Subsequently, an insulating layer 231 can be formed in the region where the mask layer 301 has been removed. The insulating layer 231 can correspond to the third interlayer insulating layer described with reference to Figure 5B and Figure 6B .

[0092] With reference to Figure 12 , the first interlayer insulating layer 215, the first material layer 216A, the second material layer 219A, the plurality of third material layers 219B, the plurality of fourth material layers 216B, the fifth material layer 216C, the sixth material layer 219C, and the insulating layer 231 that overlap with the first semiconductor layer 201, the first protective layer 203, the source sacrificial layer 205, the second protective layer 207, and the second semiconductor layer 209 of the preliminary doped semiconductor structure can be etched. Accordingly, a slit 241A can be formed. During the etching process of forming the slit 241A, the second semiconductor layer 209 can be used as an etch stop layer. The second semiconductor layer 209 can be exposed through the slit 241A.

[0093] With reference to Figure 13A andFigure 13B , Figure 12 The first material layer 216A, the plurality of fourth material layers 216B, and the fifth material layer 216C shown in Figure 12 can be replaced by the plurality of conductive layers 217A, 217B, and 217C through the slit 241A. The portions of each of the first material layer 216A, the plurality of fourth material layers 216B, and the fifth material layer 216C adjacent to the slit 241A can be replaced by the corresponding conductive layers. The partial regions of each of the first material layer 216A, the plurality of fourth material layers 216B, and the fifth material layer 216C that overlap with the regions where the insulating structure 210, the lower conductive contact structure 211A, and the lower conductive chip protection pattern 211B are provided are not replaced by the conductive layers but can be retained as dummy layers, thereby constituting the dummy layer stack structure 210D.

[0094] The second material layer, the plurality of third material layers, and the sixth material layer can be divided into a plurality of second interlayer insulating layers 219CA, 219CB, and 219CC and a plurality of dummy interlayer insulating layers 219DA, 219DB, and 219DC. In order to form the gate stack structure 210G, the plurality of second interlayer insulating layers 219CA, 219CB, and 219CC and the plurality of conductive layers 217A, 217B, and 217C can be alternately provided between the first interlayer insulating layer 215 and the insulating layer 231. In order to form the dummy layer stack structure 210D, the plurality of dummy interlayer insulating layers 219DA, 219DB, and 219DC can be alternately provided with the plurality of dummy layers that are the remaining portions of the first material layer 216A, the plurality of fourth material layers 216B, and the fifth material layer 216C between the first interlayer insulating layer 215 and the insulating layer 231.

[0095] Referring to Figure 14 , after forming the gate stack structure 210G, the second semiconductor layer 209 and the second protective layer 207 can be etched through the slit 241A shown in Figure 13A . Accordingly, an extended slit 241B can be formed. The source sacrificial layer 205 can be exposed through the extended slit 241B. Although not shown in the figure, a spacer layer can be formed on the sidewalls of the gate stack structure 210G before etching the second semiconductor layer 209. The extended slit 241B can be formed in a state where the gate stack structure 210G is protected by the spacer layer.

[0096] Referring to Figure 15 , the Figure 14 ​​The source sacrificial layer 205 shown. A part of the multilayer 221 can be exposed through the area where the source sacrificial layer 205 is removed. Subsequently, the channel layer 223 can be exposed by etching the exposed area of the multilayer 221. The multilayer 221 can be isolated into a memory layer 221M and a dummy memory layer 221D. When etching the exposed area of the multilayer 221, Figure 14 the first protective layer 203 and the second protective layer 207 shown can be removed. Referring to Figure 14 the spacer layer described, it can be retained, or can be removed when etching the exposed area of the multilayer 221.

[0097] Subsequently, a channel contact semiconductor layer 251 can be formed between the first semiconductor layer 201 and the second semiconductor layer 209. The channel contact semiconductor layer 251 can be in contact with each of the first semiconductor layer 201, the second semiconductor layer 209, and the channel layer 223. The channel contact semiconductor layer 251 can include at least one of an n-type impurity and a p-type impurity. In an embodiment, the channel contact semiconductor layer 251 can include an n-type doped silicon layer, and the n-type doped silicon layer includes an n-type impurity as a majority carrier.

[0098] Referring to Figure 16 , Figure 15 the extended slit 241B shown can be filled with various fillers 243.

[0099] Referring to Figure 17 , a first opening 250A and a second opening 250B can be formed, and the first opening 250A and the second opening 250B penetrate at least a part of the insulating layer 231 and the dummy stacked structure 210D.

[0100] The first opening 250A can penetrate the insulating layer 231, the dummy stacked structure 210D, and the first interlayer insulating layer 215 to expose the lower conductive contact structure 211A. The second opening 250B can penetrate a part of the insulating layer 231 and the dummy stacked structure 210D to expose the insulating chip protection pattern 220B. The second opening 250B can extend in a line shape on a plane in a manner similar to the Figure 5C conductive chip protection pattern GP2 shown. When the second opening 250B is formed in a line shape, the depth of the second opening 250B can be formed to be shallower than the depth of the first opening 250A. Although the depth of the second opening 250B is formed to be shallower than the depth of the first opening 250A, the second opening 250B can be formed to have a depth that still exposes the pre-formed insulating chip protection pattern 220B.

[0101] Referring to Figure 18 , an insulating layer 251A and 251B can be respectively formed in the Figure 17 first opening 250A and the second opening 250B shown.

[0102] Referring to Figure 19 , a conductive vertical contact structure 255A and a conductive chip protection pattern 255B can be formed. The conductive vertical contact structure 255A can penetrate Figure 17 the insulating layer 251A in the first opening 250A shown, and can be connected to the lower conductive contact structure 211A. The conductive chip protection pattern 255B can penetrate Figure 17 the insulating layer 251B in the second opening 250B shown, and can be connected to the insulating chip protection pattern 220B.

[0103] Figure 20 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0104] Referring to Figure 20 , the electronic system 1000 can be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 can include a host 1100 and a storage device 1200.

[0105] Based on the interface, the host 1100 can store data in the storage device 1200 or read the data stored in the storage device 1200. The interface can include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a rapid PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash storage (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0106] The storage device 1200 can include a memory controller 1210 and a semiconductor memory device 1220. In an embodiment, the storage device 1200 can be a storage medium such as a solid state drive (SSD) or a universal serial bus (USB) memory.

[0107] The memory controller 1210 can store data in the semiconductor memory device 1220 or read the data stored in the semiconductor memory device 1220 under the control of the host 1100.

[0108] The semiconductor memory device 1220 can include one memory chip or multiple memory chips. The semiconductor memory device 1220 can store data or output the stored data under the control of the memory controller 1210.

[0109] The semiconductor memory device 1220 may be a non-volatile memory device. As referred to Figure 6A and Figure 6B above, the semiconductor memory device 1220 may include a dummy stack structure, an insulating chip protection pattern penetrating the lower part of the dummy stack structure, and a conductive chip protection pattern aligned with the insulating chip protection pattern above the insulating chip protection pattern and penetrating the upper part of the dummy stack structure.

[0110] According to an embodiment of the present disclosure, by a structure in which the insulating chip protection pattern and the conductive chip protection pattern overlap each other, process failures in the chip protection region can be reduced. Accordingly, the stability of the semiconductor memory device manufacturing process can be improved.

[0111] Cross-reference to related applications

[0112] This application claims the priority of Korean Patent Application No. 10-2023-0179864, filed on December 12, 2023, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A lower structure, the lower structure comprising a circuit area and a chip protection area, the chip protection area surrounding the circuit area; a memory cell array structure, the memory cell array structure overlapping a first region of the circuit region of the lower structure; a conductive vertical contact structure overlapping a second region of the circuit region of the lower structure; a dummy stacked structure, the dummy stacked structure being stacked above the chip protection region of the lower structure; an insulating chip protection pattern, the insulating chip protection pattern penetrating a lower portion of the dummy stacked structure; as well as A conductive chip protection pattern is aligned with the insulating chip protection pattern above the insulating chip protection pattern, and the conductive chip protection pattern penetrates an upper portion of the dummy stack structure.

2. The semiconductor memory device according to claim 1, wherein The memory cell array structure comprises: a plurality of conductive layers and a plurality of interlayer insulating layers, the plurality of conductive layers and the plurality of interlayer insulating layers being alternately stacked above the lower structure; a selection line isolation insulating layer, wherein the selection line isolation insulating layer penetrates a lower conductive layer closest to the lower structure among the plurality of conductive layers, so that the lower conductive layer is isolated into a selection line; a channel layer penetrating the plurality of conductive layers and the plurality of interlayer insulating layers on both sides of the selection line isolation insulating layer; and A memory layer is interposed between each of the plurality of conductive layers and the channel layer.

3. The semiconductor memory device according to claim 2, wherein: The insulating chip protection pattern has a sidewall overlapping the selection line isolation insulating layer.

4. The semiconductor memory device according to claim 2, wherein: The insulating chip protection pattern and the selection line isolation insulating layer include the same material.

5. The semiconductor memory device according to claim 2, wherein: The insulating chip protection pattern and the selection line isolation insulating layer are disposed at substantially the same height.

6. The semiconductor memory device according to claim 1, wherein: The dummy stack structure includes a plurality of nitride layers and a plurality of oxide layers alternately stacked over the lower structure.

7. The semiconductor memory device according to claim 1, wherein: The dummy stack structure extends to surround the conductive vertical contact structure.

8. The semiconductor memory device according to claim 1, wherein The lower structure comprises: a doped semiconductor structure, the doped semiconductor structure being disposed in the first region of the circuit region; an insulating structure, the insulating structure being disposed in the second region of the circuit region, the insulating structure extending to the chip protection region; and A lower conductive contact structure and a lower conductive chip protection pattern penetrate the insulating structure.

9. The semiconductor memory device according to claim 8, wherein: The conductive vertical contact structure: extending in a direction away from the lower conductive contact structure; and A sidewall overlaps the insulating chip protection pattern and the conductive chip protection pattern.

10. The semiconductor memory device according to claim 8, wherein: The insulating chip protection pattern includes a first end portion contacting the lower conductive chip protection pattern and a second end portion contacting the conductive chip protection pattern.

11. A semiconductor memory device, comprising: A lower structure, the lower structure comprising a circuit area and a chip protection area, the chip protection area surrounding the circuit area; a memory cell array structure, the memory cell array structure overlapping a first region of the circuit region of the lower structure; a conductive vertical contact structure overlapping a second region of the circuit region of the lower structure; a dummy stacked structure, the dummy stacked structure being stacked above the chip protection region of the lower structure; an insulating chip protection pattern, wherein the insulating chip protection pattern penetrates a portion of the dummy stacked structure; as well as A conductive chip protection pattern penetrates different portions of the dummy stack structure to contact the insulating chip protection pattern.

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