Semiconductor memory device and manufacturing method thereof

Abstract

The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes: a first stack including a first hole; a second stack disposed on the first stack and including a second hole connected to the first hole; a first memory film formed along an inner sidewall of the first hole; a second memory film formed along an inner side wall of the second hole; and a channel film formed along an inner sidewall of the first memory film and an inner sidewall of the second memory film. The channel film is a single, continuous element.

Description

[0001] This patent application is a divisional application of a Chinese patent application with an application date of April 17, 2020, an application number of 2020103039507, and an invention title of "Semiconductor Memory Device and Method of Manufacturing the Same".

[0002] Cross - reference to related applications

[0003] This application claims the priority of a Korean patent application No. 10 - 2019 - 0109139, filed on September 3, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0004] The present disclosure relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three - dimensional semiconductor memory device and a method of manufacturing the same. Background art

[0005] A semiconductor memory device includes memory cells capable of storing data.

[0006] According to the method used to store and maintain data, semiconductor memory devices can be classified as volatile semiconductor memory devices or non - volatile semiconductor memory devices. A volatile semiconductor memory device is a memory device in which data stored therein is lost when the power supply is interrupted, while a non - volatile semiconductor memory device is a memory device that retains the stored data even when the power supply is interrupted.

[0007] Recently, with the increasing use of portable electronic devices, the demand for non - volatile semiconductor memory devices with higher integration, larger capacity, improved portability, and improved performance has also increased. To achieve these goals, various three - dimensional semiconductor memory devices have been proposed and are being developed. Summary of the invention

[0008] Embodiments of the present disclosure provide a semiconductor memory device and a method of manufacturing the same that can improve operational reliability.

[0009] A semiconductor memory device according to an embodiment of the present disclosure may include: a first stack including a first hole; a second stack disposed on the first stack and including a second hole connected to the first hole; a first storage film formed along an inner sidewall of the first hole; a second storage film formed along an inner sidewall of the second hole; and a channel film formed along inner sidewalls of the first storage film and the second storage film. The channel film may have an integrated structure.

[0010] A semiconductor memory device according to an embodiment of the present disclosure may include: a first stack; a second stack disposed on the first stack; a first hole that vertically penetrates the first stack; a first barrier film and a first storage film that are sequentially formed along an inner wall of the first hole; a second hole that vertically penetrates the second stack; a second barrier film and a second storage film that are sequentially formed along an inner wall of the second hole; a tunnel film that is formed along the inner walls of the first storage film and the second storage film; and a channel film formed in the tunnel film.

[0011] A method of manufacturing a semiconductor memory according to an embodiment of the present disclosure may include: forming a first stack including a first hole; forming a first storage film and a channel sacrificial pattern in the first hole; forming a second stack including a second hole on the first stack; forming a first initial storage film along an inner wall of the second hole; removing the channel sacrificial pattern exposed through the second hole; and forming a channel film in the first hole and the second hole from which the channel sacrificial pattern has been removed.

[0012] A semiconductor memory device according to an embodiment of the present technology may provide a channel film that penetrates a plurality of cell stacks. Accordingly, the operation reliability of the semiconductor memory device according to an embodiment of the present technology may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 2A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 2B is Figure 2A an enlarged view of region A of

[0016] Figures 3A to 3G is a cross-sectional view describing a method of manufacturing a semiconductor memory device according to Figure 2A and Figure 2B of the present disclosure.

[0017] Figure 4A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 4B is Figure 4A an enlarged view of region B of

[0019] Figures 5A to 5G is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to Figure 4A and Figure 4B of the present disclosure.

[0020] Figure 6AIt is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Figure 6B is Figure 6A an enlarged view of region C of

[0022] Figure 7 It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Figure 8 It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Figure 9 It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0025] Figure 10 It is a block diagram showing the configuration of a storage system according to an embodiment of the present disclosure.

[0026] Figure 11 It is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Detailed Description

[0027] The technical spirit of the present disclosure can be variously changed by configuring embodiments having various aspects. Hereinafter, some embodiments of the present disclosure will be described so that those skilled in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0028] Figure 1 It is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0029] Referring to Figure 1 , the semiconductor memory device may include a substrate SUB, a peripheral circuit structure PC on the substrate SUB, and a memory cell array on the peripheral circuit structure PC.

[0030] The substrate SUB may be a single crystal semiconductor film. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, or a germanium-silicon substrate. The single crystal semiconductor film may be an epitaxial thin film formed on a semiconductor substrate by a selective epitaxial growth method.

[0031] The peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the memory cell array. The NMOS transistors, PMOS transistors, resistors, and capacitors may be used as elements for configuring a row decoder, a column decoder, a page buffer circuit, and an input / output circuit.

[0032] The peripheral circuit structure PC can be disposed between the memory cell array and the substrate SUB. For example, the memory cell array can overlap with the peripheral circuit structure PC vertically (i.e., in the third direction D3). The third direction D3 can be a direction perpendicular to the upper surface of the substrate SUB. When the memory cell array is disposed on the peripheral circuit structure PC, the area of the substrate SUB occupied by the memory cell array and the peripheral circuit structure PC can be reduced. Different from the illustrated embodiment, the peripheral circuit structure PC may not overlap with the memory cell array. In other words, the peripheral circuit structure PC and the memory cell array can be spaced apart in a plane (i.e., in the first direction D1 or the second direction D2). The first direction D1 can be a direction parallel to the upper surface of the substrate SUB. The second direction D2 can be a direction parallel to the upper surface of the substrate SUB and perpendicular to the first direction D1.

[0033] The memory cell array can include a source electrode film SL, a bit line BL, a stack CE, a channel structure CST, and a bit line contact BCT.

[0034] The source electrode film SL can serve as a source line and can be disposed on the peripheral circuit structure PC. The source electrode film SL can be a doped semiconductor film containing a source dopant. For example, the source dopant can be an n-type dopant. For example, the source electrode film SL can be formed by depositing a doped semiconductor film on the peripheral circuit structure PC. In one embodiment, a semiconductor film such as a silicon film can be deposited on the peripheral circuit structure using any suitable deposition method, and then an n-type dopant can be implanted into the film to form the doped semiconductor film SL. For example, the doped semiconductor film can include doped silicon.

[0035] The stack CE can be disposed on the source electrode film SL. The stack CE can include a conductive pattern CP and an insulating pattern (not shown). The conductive pattern CP and the insulating pattern can be alternately arranged along the third direction D3. In other words, the conductive pattern CP and the insulating pattern can be alternately stacked along the third direction D3. For example, the conductive pattern CP can be formed of a gate conductive film. For example, the gate conductive film can include at least one of a doped silicon film, a metal silicide film, tungsten, nickel, and cobalt, and can serve as a word line connected to the memory cell or a selection line connected to the selection transistor. The conductive pattern CP can also include a barrier film surrounding the gate conductive film. For example, the barrier film can include at least one of titanium nitride and tantalum nitride. For example, the insulating pattern can include silicon oxide.

[0036] The conductive pattern CP closest to the source electrode film SL can be defined as the first conductive pattern CP1. The conductive pattern CP adjacent to the first conductive pattern CP1 can be defined as the second conductive pattern CP2.

[0037] The conductive pattern CP set farthest from the source electrode film SL can be defined as the third conductive pattern CP3. The third conductive patterns CP3 can be spaced apart from each other in the second direction D2 through the upper slit USI. The conductive pattern CP adjacent to the third conductive pattern CP3 can be defined as the fourth conductive pattern CP4. The fourth conductive patterns CP4 can be spaced apart from each other in the second direction D2 through the upper slit USI. The upper slit USI can vertically overlap the conductive pattern CP other than the third conductive pattern CP3 and the fourth conductive pattern CP4.

[0038] For example, the first conductive pattern CP1 and the second conductive pattern CP2 can be used as source selection lines, while the third conductive pattern CP3 and the fourth conductive pattern CP4 can be used as drain selection lines. However, the present disclosure is not limited thereto. The conductive pattern disposed between the source selection line and the drain selection line can be used as a word line.

[0039] The channel structure CST can extend in the third direction D3 and pass through the stack CE. The plurality of channel structures CST passing through one third conductive pattern CP3 can be arranged in the first direction D1. The plurality of channel structures CST electrically connected to one bit line BL can be arranged in the second direction D2. The channel structure CST can be in direct contact with the source electrode film SL. The channel structure CST can be electrically connected to the source electrode film SL.

[0040] The bit line BL can be disposed on the stack CE. The bit line BL can extend in the second direction D2. The bit lines BL can be arranged to be spaced apart from each other in the first direction D1. The bit line BL can be electrically connected to the channel structure CST via the bit line contact BCT. The bit line BL can include a conductive material. For example, the bit line BL can include tungsten, aluminum, or copper.

[0041] The bit line contact BCT can be disposed between the bit line BL and the channel structure CST. Each bit line contact BCT can electrically connect one bit line BL to one channel structure CST. The bit line contact BCT can include a conductive material. For example, the bit line contact BCT can include tungsten, aluminum, or copper.

[0042] Figure 2A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 2B is Figure 2A an enlarged view of region A of

[0043] Except as described below, the semiconductor memory device according to the present embodiment can be similar to the semiconductor memory device according to Figure 1 of

[0044] Refer to Figure 2A and Figure 2B, the semiconductor memory device according to the present embodiment may include a first stack CE1 and a second stack CE2. The first stack CE1 may be disposed on the source electrode film SL (refer to Figure 1 ), and the second stack CE2 may be disposed on the first stack CE1. The first stack CE1 may include alternately stacked conductive patterns CP and insulating patterns IP. The second stack CE2 may include an upper insulating pattern UIP and alternately stacked conductive patterns CP and insulating patterns IP. For example, the upper insulating pattern UIP may include silicon oxide.

[0045] The first stack CE1 may include a first hole HO1. The first hole HO1 may penetrate the first stack CE1. The second stack CE2 may include a second hole HO2. The second hole HO2 may penetrate the second stack CE2. The first hole HO1 may penetrate the conductive pattern CP and the insulating pattern IP of the first stack CE1, and the second hole HO2 may penetrate the conductive pattern CP, the insulating pattern IP, and the upper insulating pattern UIP of the second stack CE2. The second hole HO2 may overlap perpendicularly with the corresponding first hole HO1. The corresponding first hole HO1 and the second hole HO2 may be connected to each other.

[0046] The channel structures CST may each completely fill the corresponding connected first hole HO1 and second hole HO2. Each channel structure CST may include a first storage film ML1 formed along the inner sidewall of the first hole HO1, and a second storage film ML2 formed along the inner sidewall of the second hole HO2. Each channel structure CST may further include a channel film CL formed along the inner sidewalls of the first storage film ML1 and the second storage film ML2. The channel film CL may be formed in a columnar or cylindrical shape. When the channel film CL is formed in a columnar shape, the channel film CL may be filled in the first storage film ML1 and the second storage film ML2 formed in a cylindrical shape. When the channel film CL is formed in a cylindrical shape, the channel structure CST may further include a filling film FI in the channel film CL. In the present embodiment, the following structure will be described as an example, in which the first storage film ML1, the second storage film ML2, the channel film CL, and the filling film FI are included in the channel structure CST.

[0047] The filling film FI may include: a lower portion FI1 in the first stack CE1, an upper portion FI2 in the second stack CE2, and a filling connection portion FI3 connecting the lower portion FI1 and the upper portion FI2 to each other. The lower portion FI1 may be formed in the first hole HO1. The upper portion FI2 may be formed in the second hole HO2. The filling connection portion FI3 may be disposed at the same level as the boundary between the first stack CE1 and the second stack CE2. In other words, the filling connection portion FI3 may be disposed at the same level as the boundary between the first hole HO1 and the second hole HO2.

[0048] Ideally, the upper part of the first hole HO1 and the upper part of the second hole HO2, as well as the lower part of the first hole HO1 and the lower part of the second hole HO2, need to have the same width. However, the upper and lower parts of the same hole can have different widths. For example, the width of the lower part of each of the first hole HO1 and the second hole HO2 can be less than the width of the upper part. As described above, when the widths of the upper and lower parts of each of the first hole HO1 and the second hole HO2 are different from each other, the minimum width of the upper part FI2 of the filling film FI in the second direction D2 can be defined as the first width W1, and the maximum width of the filling connection part FI3 in the second direction D2 can be defined as the second width W2. The second width W2 can be less than the first width W1.

[0049] The filling film FI can have an integrated structure. In other words, the lower part FI1, the upper part FI2, and the filling connection part FI3 of the filling film FI can be formed simultaneously in one deposition process. Therefore, the lower part FI1, the upper part FI2, and the filling connection part FI3 of the filling film FI can be integrally connected to each other without a boundary. The filling film FI can pass through the first stack CE1 and the second stack CE2. In other words, the filling film FI can pass through the first hole HO1 and the second hole HO2. The length of the filling film FI in the third direction D3 can be the same as the sum of the lengths of the first stack CE1 and the second stack CE2 in the third direction D3. For example, the filling film FI can include silicon oxide.

[0050] A channel film CL can be provided to cover the outer sidewalls of the filling film FI. In other words, the filling film FI can be disposed in the channel film CL. The channel film CL can include: a first channel sidewall part CL1 that covers the outer sidewall of the lower part FI1 of the filling film FI; a second channel sidewall part CL2 that covers the outer sidewall of the upper part FI2 of the filling film FI; and a channel interpolation part CL3 that connects the first channel sidewall part CL1 and the second channel sidewall part CL2 to each other. The first channel sidewall part CL1 can be formed along the inner sidewall of the first storage film ML1. The second channel sidewall part CL2 can be formed along the inner sidewall of the second storage film ML2. The channel interpolation part CL3 can cover the outer sidewall of the filling connection part FI3 of the filling film FI.

[0051] The channel interpolation part CL3 may include a first channel connection part CL3_R1, a second channel connection part CL3_R2, and a third channel connection part CL3_R3. The first channel connection part CL3_R1 may be connected to the first channel sidewall part CL1, the second channel connection part CL3_R2 may be connected to the second channel sidewall part CL2, and the third channel connection part CL3_R3 may connect the first channel connection part CL3_R1 and the second channel connection part CL3_R2 to each other. Each of the first to third channel connection parts CL3_R1, CL3_R2, and CL3_R3 may have an annular shape.

[0052] The width between the outer wall and the inner wall of the first channel connection part CL3_R1 in the second direction D2 may be defined as a third width W3. The width between the outer wall and the inner wall of the second channel connection part CL3_R2 in the second direction D2 may be defined as a fourth width W4. The width between the outer wall and the inner wall of the third channel connection part CL3_R3 in the second direction D2 may be defined as a fifth width W5.

[0053] The third width W3 may be greater than the fourth width W4. The fourth width W4 may be greater than the fifth width W5. The fifth width W5 may be substantially the same as the width of the first channel sidewall part CL1. The width of the first channel sidewall part CL1 may be the same as the width of the second channel sidewall part CL2. To avoid confusion, the width of the elements in the present disclosure is measured in the second direction D2. Both the third width W3 and the fourth width W4 may be greater than the width of the first channel sidewall part CL1 (or the second channel sidewall part CL2).

[0054] The lower surface of the first channel connection part CL3_R1 may be in direct contact with the upper surface of the lower part FI1 of the filling film FI. The inner wall of the first channel connection part CL3_R1 may be in direct contact with the outer wall of the filling connection part FI3 of the filling film FI. The upper surface of the first channel connection part CL3_R1 may be at the same level as the boundary between the first stack CE1 and the second stack CE2. In other words, the upper surface of the first channel connection part CL3_R1 may be at the same level as the boundary between the first hole HO1 and the second hole HO2.

[0055] The upper surface of the second channel connection part CL3_R2 may be in direct contact with the lower surface of the upper part FI2 of the filling film FI. The inner wall of the second channel connection part CL3_R2 may be in direct contact with the outer wall of the filling connection part FI3 of the filling film FI.

[0056] The channel membrane CL may have an integrated structure. In other words, the first channel sidewall portion CL1, the second channel sidewall portion CL2, and the channel interpolation portion CL3 of the channel membrane CL may be integrally connected to each other without boundaries. The channel membrane CL may pass through the first stack CE1 and the second stack CE2. In other words, the channel membrane CL may pass through the first hole HO1 and the second hole HO2. The length of the channel membrane CL in the third direction D3 may be the same as the sum of the lengths of the first stack CE1 and the second stack CE2 in the third direction D3. The channel membrane CL may be formed of a semiconductor membrane. For example, the channel membrane CL may be formed of a doped polysilicon membrane or an undoped polysilicon membrane.

[0057] A first storage membrane ML1 and a second storage membrane ML2 that cover the outer sidewalls of the channel membrane CL may be provided. The first storage membrane ML1 may be disposed in the first stack CE1. The first storage membrane ML1 may pass through the first stack CE1. The second storage membrane ML2 may be disposed in the second stack CE2. The second storage membrane ML2 may pass through the second stack CE2.

[0058] The first storage membrane ML1 may include: a first tunnel membrane TI1 that surrounds the outer sidewall of the first channel sidewall portion CL1 of the channel membrane CL; a first storage membrane DS1 that surrounds the outer sidewall of the first tunnel membrane TI1; and a first blocking membrane BI1 that surrounds the outer sidewall of the first storage membrane DS1.

[0059] The second storage membrane ML2 may include: a second tunnel membrane TI2 that surrounds the outer sidewall of the second channel sidewall portion CL2 of the channel membrane CL; a second storage membrane DS2 that surrounds the outer sidewall of the second tunnel membrane TI2; and a second blocking membrane BI2 that surrounds the outer sidewall of the second storage membrane DS2.

[0060] The first tunnel membrane TI1 and the second tunnel membrane TI2 may be spaced apart from each other. The first tunnel membrane TI1 and the second tunnel membrane TI2 may include an oxide capable of charge tunneling. For example, the first tunnel membrane TI1 and the second tunnel membrane TI2 may include silicon oxide.

[0061] The first storage membrane DS1 and the second storage membrane DS2 may be spaced apart from each other. The first storage membrane DS1 and the second storage membrane DS2 may include a material in which charges can be trapped. For example, the first storage membrane DS1 and the second storage membrane DS2 may include at least one of a nitride, silicon, a phase change material, and a nanodot.

[0062] The first blocking membrane BI1 and the second blocking membrane BI2 may be spaced apart from each other. The first blocking membrane BI1 and the second blocking membrane BI2 may include an oxide capable of blocking the movement of charges. For example, the first blocking membrane BI1 and the second blocking membrane BI2 may include silicon oxide.

[0063] The second tunnel film TI2 may include a tunnel sidewall portion TI2_S and a tunnel pattern portion TI2_R. The lowermost portion of the second tunnel film TI2 may be defined as the tunnel pattern portion TI2_R. The tunnel pattern portion TI2_R may have an annular shape. The tunnel pattern portion TI2_R may be a horizontal layer extending in a first direction D1 and a second direction D2. The upper surface of the tunnel pattern portion TI2_R may be in direct contact with the lower surface of the second channel connection portion CL3_R2 of the channel interpolation portion CL3 of the channel film CL. The inner sidewall of the tunnel pattern portion TI2_R may be in direct contact with the outer sidewall of the third channel connection portion CL3_R3 of the channel interpolation portion CL3 of the channel film CL. The width between the outer sidewall and the inner sidewall of the tunnel pattern portion TI2_R in the second direction D2 may be defined as a sixth width W6. The sixth width W6 may be greater than the width of the first tunnel film TI1. The sixth width W6 may be greater than the width of the tunnel sidewall portion TI2_S of the second tunnel film TI2.

[0064] The second storage film DS2 may include a storage sidewall portion DS2_S and a storage pattern portion DS2_R. The lowermost portion of the second storage film DS2 may be defined as the storage pattern portion DS2_R. The storage pattern portion DS2_R may have an annular shape. The storage pattern portion DS2_R may be a horizontal layer extending in a first direction D1 and a second direction D2. The upper surface of the storage pattern portion DS2_R may be in direct contact with the lower surface of the tunnel pattern portion TI2_R of the second tunnel film TI2. The inner sidewall of the storage pattern portion DS2_R may be in direct contact with the outer sidewall of the third channel connection portion CL3_R3 of the channel interpolation portion CL3 of the channel film CL. The width between the outer sidewall and the inner sidewall of the storage pattern portion DS2_R in the second direction D2 may be defined as a seventh width W7. The seventh width W7 may be greater than the width of the first storage film DS1. The seventh width W7 may be greater than the width of the storage sidewall portion DS2_S of the second storage film DS2. The seventh width W7 may be greater than the sixth width W6.

[0065] The second barrier film BI2 may include a barrier sidewall portion BI2_S and a barrier pattern portion BI2_R. The lowermost portion of the second barrier film BI2 may be defined as the barrier pattern portion BI2_R. The barrier pattern portion BI2_R may have an annular shape. The barrier pattern portion BI2_R may be a horizontal layer extending in a first direction D1 and a second direction D2. The upper surface of the barrier pattern portion BI2_R may be in direct contact with the lower surface of the storage pattern portion DS2_R of the second storage film DS2. The inner sidewall of the barrier pattern portion BI2_R may be in direct contact with the outer sidewall of the third channel connection portion CL3_R3 of the channel interpolation portion CL3 of the channel film CL. The lower surface of the barrier pattern portion BI2_R may be in direct contact with the upper surface of the first channel connection portion CL3_R1 of the channel interpolation portion CL3 of the channel film CL. The width between the outer sidewall and the inner sidewall of the barrier pattern portion BI2_R in the second direction D2 may be defined as an eighth width W8. The eighth width W8 may be greater than the width of the first barrier film BI1. The eighth width W8 may be greater than the width of the barrier sidewall portion BI2_S of the second barrier film BI2. The eighth width W8 may be greater than the seventh width W7.

[0066] The length of the first storage film ML1 in a third direction D3 may be substantially the same as the length of the first stack CE1 in the third direction D3. The length of the second storage film ML2 in the third direction D3 may be substantially the same as the length of the second stack CE2 in the third direction D3. The sum of the length of the first storage film ML1 in the third direction D3 and the length of the second storage film ML2 in the third direction D3 may be substantially the same as the length of the channel film CL in the third direction D3 and the length of the filling film FI in the third direction D3.

[0067] Figures 3A to 3G is a cross-sectional view of a method of manufacturing a semiconductor memory device according to Figure 2A and Figure 2B of.

[0068] Referring to Figure 3A , a first stack CE1 may be formed on a substrate. The first stack CE1 may include an insulating film and a gate sacrificial film stacked alternately. Each of the insulating film and the gate sacrificial film may be stacked alternately by a deposition process. For example, the insulating film may include silicon oxide. For example, the gate sacrificial film may include silicon nitride.

[0069] A first hole HO1 can be formed through the first stack CE1. Forming the first hole HO1 may include: forming a mask pattern (not shown) on the first stack CE1, patterning the first stack CE1 using the mask pattern as an etching mask, and removing the mask pattern. Along with the formation of the first hole HO1, the insulating film and the gate sacrificial film may be patterned, for example, by etching, to form an insulating pattern IP and a gate sacrificial pattern SP of the first stack CE1.

[0070] A first initial storage film pML1 can be formed along the surface of the first stack CE1. The first initial storage film pML1 may include a first initial barrier film pBI1, a first initial storage film pDS1, and a first initial tunnel film pTI1. Forming the first initial storage film pML1 may include: conformally forming the first initial barrier film pBI1 along the surface of the first stack CE1, conformally forming the first initial storage film pDS1 on the first initial barrier film pBI1, and conformally forming the first initial tunnel film pTI1 on the first initial storage film pDS1. The first initial storage film pML1 may partially fill the first hole HO1. In other words, the first initial storage film pML1 may not completely fill the first hole HO1.

[0071] Reference Figure 3B , a channel sacrificial film ME can be formed in the first hole HO1 in which the first initial storage film pML1 is formed. The first hole HO1 may be completely filled with the channel sacrificial film ME. The channel sacrificial film ME may have an etching selectivity with respect to the first initial storage film pML1. The channel sacrificial film ME may include a metal material having an etching rate higher than that of the first initial storage film pML1. For example, the channel sacrificial film ME may be formed of a material having an etching selectivity with respect to the first initial tunnel film pTI1. For example, the channel sacrificial film ME may be formed of a metal material having an etching rate higher than that of the first initial tunnel film pTI1.

[0072] Reference Figure 3C , a planarization process can be performed to expose the upper surface CE1_T of the first stack CE1. The planarization process may be a chemical mechanical polishing (CMP) process. Through the planarization process, a part of the first initial storage film pML1 and a part of the channel sacrificial film ME located at a level higher than the upper surface CE1_T of the first stack CE1 can be removed, and the upper surface CE1_T of the first stack CE1 can be exposed. In other words, the planarization process removes all parts of the first initial storage film pML1 above the first stack CE1.

[0073] Through a planarization process, a part of the first initial storage film pML1 can be removed, and the first initial storage film pML1 remaining in the first hole HO1 can be defined as the first storage film ML1. In other words, the first storage film ML1 can be formed. The first storage film ML1 can include a first tunnel film TI1, a first storage film DS1, and a first barrier film BI1.

[0074] Through a planarization process, a part of the channel sacrificial film ME can be removed to form a channel sacrificial pattern MP.

[0075] Reference Figure 3D , and then a second stack CE2 can be formed on the first stack CE1. Forming the second stack CE2 can include alternately stacking an insulating film and a gate sacrificial film on the first stack CE1, and forming an upper insulating film UIP. For example, the upper insulating film UIP can include silicon oxide.

[0076] A hard mask film can be formed on the upper insulating film. For example, the hard mask film HP can include silicon nitride.

[0077] A second hole HO2 can be formed through the second stack CE2 and the hard mask film. Forming the second hole HO2 can include: forming a mask pattern on the hard mask film including an opening exposing a part of the hard mask film, using the mask pattern as an etching mask to pattern the hard mask film and the second stack CE2, and removing the mask pattern. When forming the second hole HO2, the hard mask film can be patterned, for example by etching, to form a hard mask pattern HP, the upper insulating film can be patterned, for example by etching, to form an upper insulating pattern UIP, the insulating film and the gate sacrificial film can be patterned, for example by etching, to form an insulating pattern IP and a gate sacrificial pattern SP. The upper surface MP_T of the channel sacrificial pattern MP in the first stack CE1 can be exposed by the second hole HO2.

[0078] A second initial storage film pML2 can be formed along the surfaces of the second stack CE2 and the hard mask pattern HP. The second initial storage film pML2 can include a second initial barrier film pBI2, a second initial storage film pDS2, and a second initial tunnel film pTI2. Forming the second initial storage film pML2 can include: conformally forming the second initial barrier film pBI2 along the surfaces of the second stack CE2 and the hard mask pattern HP, conformally forming the second initial storage film pDS2 on the second initial barrier film pBI2, and conformally forming the second initial tunnel film pTI2 on the second initial storage film pDS2. The second initial storage film pML2 can partially fill the second hole HO2. In other words, the second initial storage film pML2 may not completely fill the second hole HO2. The second initial storage film pML2 can cover the upper surface MP_T of the channel sacrificial pattern MP.

[0079] ReferenceFigure 3E , a part of the second initial storage film pML2 located on the upper surface MP_T of the channel sacrificial pattern MP of the first stack CE1 can be patterned, for example, by etching. As the second initial storage film pML2 is patterned, a part of the upper surface MP_T of the channel sacrificial pattern MP can be exposed again. As the second initial storage film pML2 is patterned, a barrier pattern portion BI2_R can be formed in the second initial barrier film pBI2 (refer to Figure 2B ), a storage pattern portion DS2_R can be formed in the second initial storage film pDS2 (refer to Figure 2B ), and a tunnel pattern portion TI2_R can be formed in the second initial tunnel film pTI2 (refer to Figure 2B ).

[0080] Refer to Figure 3F , the channel sacrificial pattern MP of the first stack CE1 can be selectively removed. The selective removal of the channel sacrificial pattern MP can be performed by a wet etching method using an etchant capable of selectively removing the channel sacrificial pattern MP. As the channel sacrificial pattern MP is removed, the inner sidewall of the first storage film ML1 can be exposed. As the channel sacrificial pattern MP is removed, the central portion of the first hole HO1 can be exposed again.

[0081] Refer to Figure 3G , a channel film CL covering the first storage film ML1 and the second initial storage film pML2 can be formed. The channel film CL can be formed on the inner sidewalls of the first storage film ML1 and the second initial storage film pML2. The channel film CL can include: a first channel sidewall portion CL1 in the first stack CE1 (refer to Figure 2B ), a second channel sidewall portion CL2 in the second stack CE2 (refer to Figure 2B ), and a channel interpolation portion CL3 (refer to Figure 2B ) that connects the first channel sidewall portion CL1 and the second channel sidewall portion CL2 to each other.

[0082] The channel film CL can be formed as a single, continuous element without any interfaces in one step. In other words, the channel film CL can be formed in the first hole HO1 and the second hole HO2 simultaneously. The channel film CL formed as a single, continuous element can pass through the first stack CE1 and the second stack CE2.

[0083] When the channel film CL is formed, then a filling film FI that completely fills the first hole HO1 and the second hole HO2 can be formed (refer to Figure 2A)。The filling film FI can be formed into a single, continuous element without any interfaces in a single step. The filling film FI formed into a single, continuous element can pass through the first stack CE1 and the second stack CE2.

[0084] When the filling film FI is formed, a planarization process can be performed to remove the hard mask pattern HP. The upper portion of the second initial storage film pML2, the upper portion of the channel film CL, and the upper portion of the filling film FI can be removed together with the hard mask pattern HP. As the upper portion of the second initial storage film pML2 is removed, the second storage film ML2 can be formed. Through the planarization process, a channel structure CST including the first storage film ML1, the second storage film ML2, the channel film CL, and the filling film FI can be formed (refer to Figure 2A ).

[0085] When the channel structure CST is formed, the gate sacrifice pattern SP can be selectively removed. As the gate sacrifice pattern SP is selectively removed, an empty space can be formed between the insulating pattern IP and the upper insulating pattern UIP. A conductive pattern CP filling the empty space can be formed (refer to Figure 2A ).

[0086] In the semiconductor memory device according to the present embodiment, after the first storage film ML1 is formed in the first hole HO1 of the first stack CE1, the second storage film ML2 is formed in the second hole HO2 of the second stack CE2 using the same process, thereby ensuring that the widths and electrical characteristics of the first storage film ML1 and the second storage film ML2 are uniform. In addition, the channel film CL covering both the first storage film ML1 and the second storage film ML2 is formed in a single step to ensure that the channel film CL is a single component. Similarly, the filling film FI is formed as an integral component in a single step. In other words, the widths and electrical characteristics of the upper and lower portions of the channel structure CST can be uniform.

[0087] In the semiconductor memory device according to the present embodiment, the channel film CL is formed simultaneously in the first hole HO1 of the first stack CE1 and the second hole HO2 of the second stack CE2. Therefore, the channel film CL can be formed by one process, and time and cost can be reduced.

[0088] Figure 4A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 4B is Figure 4A an enlarged view of region B of

[0089] Except as described below, the semiconductor memory device according to the present embodiment is similar to the semiconductor memory devices according to Figure 2A and Figure 2B .

[0090] Refer toFigure 4A and Figure 4B According to the present embodiment, the channel structure CST of the semiconductor memory device may include: a first blocking film BI1 and a first storage film DS1, which are sequentially formed along the inner sidewall of the first hole HO1; a second blocking film BI2 and a second storage film DS2, which are sequentially formed along the inner sidewall of the second hole HO2; a tunnel film TI, which is formed along the inner sidewalls of the first storage film DS1 and the second storage film DS2; a channel film CL in the tunnel film TI; and a filling film FI in the channel film CL.

[0091] The channel film CL may include a first channel sidewall portion CL1, a second channel sidewall portion CL2, and a channel interpolation portion CL3, and the channel interpolation portion CL3 may include a first channel connection portion to a third channel connection portion CL3_R1, CL3_R2, and CL3_R3 (refer to Figure 2B ). The filling film FI may include a lower portion FI1, an upper portion FI2, and a filling connection portion FI3. The second blocking film BI2 may include a blocking sidewall portion BI2_S and a blocking pattern portion BI2_R. The second storage film DS2 may include a storage sidewall portion DS2_S and a storage pattern portion DS2_R. The first blocking film BI1 and the second blocking film BI2 may be spaced apart from each other. The first storage film DS1 and the second storage film DS2 may be spaced apart from each other.

[0092] The tunnel film TI may include: a first tunnel sidewall portion TI1, which is formed along the inner sidewall of the first storage film DS1; a second tunnel sidewall portion TI2, which is formed along the inner sidewall of the second storage film DS2; and a tunnel interpolation portion TI3, which connects the first tunnel sidewall portion TI1 and the second tunnel sidewall portion TI2.

[0093] The tunnel interpolation portion TI3 may include: a first tunnel connection portion TI3_R1, which is connected to the first tunnel sidewall portion TI1; a second tunnel connection portion TI3_R2, which is connected to the second tunnel sidewall portion TI2; and a third tunnel connection portion TI3_R3, which connects the first tunnel connection portion TI3_R1 and the second tunnel connection portion TI3_R2 to each other.

[0094] The width between the outer sidewall and the inner sidewall of the first tunnel connection portion TI3_R1 in the second direction D2 may be defined as a ninth width W9. The width between the outer sidewall and the inner sidewall of the second tunnel connection portion TI3_R2 in the second direction D2 may be defined as a tenth width W10. The width between the outer sidewall and the inner sidewall of the third tunnel connection portion TI3_R3 in the second direction D2 may be defined as an eleventh width W11.

[0095] The tenth width W10 can be less than the ninth width W9. The eleventh width W11 can be less than the tenth width W10. The eleventh width W11 can be substantially the same as the widths of the first sidewall portion TI1 and the second tunnel sidewall portion TI2. The ninth width W9 and the tenth width W10 can be greater than the widths of the first tunnel sidewall portion TI1 and the second tunnel sidewall portion TI2.

[0096] The upper surface of the first tunnel connection portion TI3_R1 can be in direct contact with the lower surface of the blocking pattern portion BI2_R of the second blocking film BI2. The lower surface of the second tunnel connection portion TI3_R2 can be in direct contact with the upper surface of the storage pattern portion DS2_R of the second storage film DS2. The outer sidewall of the third tunnel connection portion TI3_R3 can be in direct contact with the inner sidewall of the storage pattern portion DS2_R of the second storage film DS2 and the inner sidewall of the blocking pattern portion BI2_R of the second blocking film BI2.

[0097] In the semiconductor memory device according to the present embodiment, the tunnel film TI, the channel film CL, and the filling film FI can each be a single, continuous element without any interfaces therein. Each of the tunnel film TI, the channel film CL, and the filling film FI can pass through the first stack CE1 and the second stack CE2. In other words, each of the tunnel film TI, the channel film CL, and the filling film FI can be formed along the inner sidewall of the first hole HO1 and the inner sidewall of the second hole HO2.

[0098] Figures 5A to 5G is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to Figure 4A and Figure 4B of the semiconductor memory device.

[0099] Except as described below, the method of manufacturing a semiconductor memory device according to the present embodiment is similar to the method of manufacturing a semiconductor memory device described in reference Figures 3A to 3G described.

[0100] Reference Figure 5A , a first stack CE1 can be formed on a substrate, and a first hole HO1 passing through the first stack CE1 can be formed.

[0101] A first initial blocking film pBI1 and a first initial storage film pDS1 can be formed on the first stack CE1. Forming the first initial blocking film pBI1 and the first initial storage film pDS1 can include: conformally forming the first initial blocking film pBI1 along the surface of the first stack CE1, and conformally forming the first initial storage film pDS1 on the first initial blocking film pBI1.

[0102] Reference Figure 5B, a channel sacrificial film ME can be formed in a first hole HO1 in which a first initial barrier film pBI1 and a first initial storage film pDS1 are formed. The first hole HO1 can be completely filled with the channel sacrificial film ME.

[0103] Referring to 5C, a planarization process can be performed to expose the upper surface CE1_T of the first stack CE1. By the planarization process, a part of the first initial barrier film pBI1, a part of the first initial storage film pDS1, and a part of the channel sacrificial film ME located at a level higher than the upper surface CE1_T of the first stack CE1 can be removed, and the upper surface CE1_T of the first stack CE1 can be exposed.

[0104] By the planarization process, a part of the first initial barrier film pBI1 can be removed, and the first initial barrier film pBI1 remaining in the first hole HO1 can be defined as the first barrier film BI1. In other words, the first barrier film BI1 can be formed. By the planarization process, a part of the first initial storage film pDS1 can be removed, and the first initial storage film pDS1 remaining in the first hole HO1 can be defined as the first storage film DS1. In other words, the first storage film DS1 can be formed.

[0105] By the planarization process, a part of the channel sacrificial film ME can be removed to form a channel sacrificial pattern MP.

[0106] Referring to Figure 5D , a second stack CE2 and a hard mask pattern HP in which a second hole HO2 is formed can be formed on the first stack CE1. For example, after the second stack CE2 is formed on the first stack CE1, a hard mask pattern HP in which an opening exposing a part of the upper surface of the second stack CE2 is formed can be formed on the second stack CE2. Subsequently, the second stack CE2 exposed through the opening of the hard mask pattern HP can be etched to form the second hole HO2. An etching process for forming the second hole HO2 can be performed until the channel sacrificial pattern MP in the first stack CE1 is exposed.

[0107] When the second hole HO2 is formed, a second initial barrier film pBI2 and a second initial storage film pDS2 can be sequentially formed along the surfaces of the second stack CE2 and the hard mask pattern HP.

[0108] Referring to Figure 5E , a part of the second initial barrier film pBI2 and a part of the second initial storage film pDS2 located on the upper surface MP_T of the channel sacrificial pattern MP can be patterned, for example, by etching. Thus, the upper surface MP_T of the channel sacrificial pattern MP can be exposed again.

[0109] Referring to Figure 5F, the channel sacrificial pattern MP can be selectively removed (e.g., by etching) to reopen a portion of the first hole HO1.

[0110] Reference Figure 5G , a tunnel film TI can be formed to cover the first storage film DS1 and the second initial storage film pDS2. The tunnel film TI can be conformally formed on the first storage film DS1 and the second initial storage film pDS2.

[0111] The tunnel film TI can be formed as a single, continuous element without any interfaces through a process. The tunnel film TI formed as a single, continuous element can pass through the first stack CE1 and the second stack CE2.

[0112] The channel film CL can be formed along the surface of the tunnel film TI. The channel film CL can be conformally formed on the tunnel film TI. The channel film CL can be formed as a single, continuous element without any interfaces through a process. The channel film CL formed as a single, continuous element can pass through the first stack CE1 and the second stack CE2.

[0113] When the channel film CL is formed, a filling film FI that completely fills the first hole HO1 and the second hole HO2 can be formed (Reference Figure 4A ). The filling film FI can be formed as a single, continuous element without any interfaces through a process. The filling film FI formed as a single, continuous element can pass through the first stack CE1 and the second stack CE2.

[0114] When the filling film FI is formed, a planarization process can be performed to form the channel structure CST (Reference Figure 4A ). Each channel structure CST can include a first blocking film BI1 and a second blocking film BI2, a first storage film DS1 and a second storage film DS2, a tunnel film TI, a channel film CL, and a filling film FI.

[0115] When the channel structure CST is formed, the gate sacrificial pattern SP can be removed, and a conductive pattern CP can be formed (Reference Figure 4A ).

[0116] Figure 6A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 6B is Figure 6A an enlarged view of the C region in

[0117] Except as described below, the semiconductor memory device according to the present embodiment can be similar to the semiconductor memory device according to Figure 2A and Figure 2B . Reference Figure 6A and Figure 6B, the width of the second tunnel film TI2 of the memory device according to the present embodiment may be constant in the second direction D2. In other words, the second tunnel film TI2 of the memory device according to the present embodiment may not include the tunnel pattern portion TI2_R of the second tunnel film TI2 of the memory device according to Figure 2A and Figure 2B .

[0118] The channel film CL may include: a first channel sidewall portion CL1 formed along the inner sidewall of the first memory film ML1; a second channel sidewall portion CL2 formed along the inner sidewall of the second memory film ML2; and a channel boundary portion CL_B connecting the first channel sidewall portion CL1 and the second channel sidewall portion CL2 to each other.

[0119] The outer sidewall of the second channel sidewall portion CL2 may be in direct contact with the inner sidewall of the storage pattern portion DS2_R of the second storage film DS2, the inner sidewall of the barrier pattern portion BI2_R of the second barrier film BI2, and the inner sidewall of the second tunnel film TI2.

[0120] The channel boundary portion CL_B may have an annular shape. The upper surface of the channel boundary portion CL_B may be at the same level as the boundary between the first stack CE1 and the second stack CE2. The upper surface of the channel boundary portion CL_B may be in direct contact with the lower surface of the barrier pattern portion BI2_R of the second barrier film BI2. The outer sidewall of the channel boundary portion CL_B may be in direct contact with the inner sidewall of the first tunnel film TI1.

[0121] The filling film FI may include a lower portion FI1 passing through the first stack CE1 and an upper portion FI2 passing through the second stack CE2. The lower portion FI1 and the upper portion FI2 may be directly connected to each other. The boundary between the lower portion FI1 and the upper portion FI2 of the filling film FI may be at the same level as the lower surface of the channel boundary portion CL_B.

[0122] Figure 7 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0123] Except as described below, the semiconductor memory device according to the present embodiment is similar to the reference Figure 2A and Figure 2B described semiconductor memory device.

[0124] Reference Figure 7 , the semiconductor memory device according to the present embodiment may include first to fourth stacks CE1, CE2, CE3, and CE4 stacked in sequence along a third direction D3. The fourth stack CE4 may include an upper insulating pattern UIP.

[0125] The channel structure CST may include: a first storage film ML1 in the first stack CE1, a second storage film ML2 in the second stack CE2, a third storage film ML3 in the third stack CE3, and a fourth storage film ML4 in the fourth stack CE4. The first to fourth storage films ML1, ML2, ML3, and ML4 may be separated from each other and may be respectively formed in the first to fourth stacks CE1, CE2, CE3, and CE4.

[0126] The first storage film ML1 may include a first barrier film BI1, a first storage film DS1, and a first tunnel film TI1. The second storage film ML2 may include a second barrier film BI2, a second storage film DS2, and a second tunnel film TI2. The third storage film ML3 may include a third barrier film BI3, a third storage film DS3, and a third tunnel film TI3. And the fourth storage film ML4 may include a fourth barrier film BI4, a fourth storage film DS4, and a fourth tunnel film TI4.

[0127] Each of the first to fourth barrier films BI1, BI2, BI3, and BI4 may include a barrier pattern portion. Each of the first to fourth storage films DS1, DS2, DS3, and DS4 may include a storage pattern portion. And the first to fourth tunnel films TI1, TI2, TI3, and TI4 may include a tunnel pattern portion.

[0128] The channel structure CST may include a single, continuous channel film CL passing through the first to fourth stacks CE1, CE2, CE3, and CE4. The channel film CL may include an in-channel interpolation portion connecting the channel sidewall portions to each other. Each in-channel interpolation portion may include a portion having a width greater than the width of the channel sidewall portion.

[0129] The channel structure CST may include a filling film FI of an integrated structure passing through the first to fourth stacks CE1, CE2, CE3, and CE4.

[0130] A method of manufacturing a semiconductor memory device according to the present embodiment will be described. The first stack CE1, the first hole HO1, and the first storage film ML1 may be formed. The second stack CE2, the second hole HO2, and the second storage film ML2 may be formed. The third stack CE3, the third hole HO3, and the third storage film ML3 may be formed. And the fourth stack CE4, the fourth hole HO4, and the fourth storage film ML4 may be formed. Then, the channel film CL and the filling film FI may be formed. Accordingly, the channel film CL and the filling film FI may each be formed as a single, continuous element passing through the first to fourth stacks CE1, CE2, CE3, and CE4.

[0131] Figure 8 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0132] Except as described below, the semiconductor memory device according to this embodiment is similar to the semiconductor memory device according to Figure 7 .

[0133] The channel structure CST of the semiconductor memory device according to this embodiment may include a first storage film ML1 passing through the first stack CE1 and the second stack CE2, and a second storage film ML2 passing through the third stack CE3 and the fourth stack CE4.

[0134] The first storage film ML1 may include a first storage film connection portion ML1_R located at the boundary between the first stack CE1 and the second stack CE2. The width between the outer wall and the inner wall of the first storage film connection portion ML1_R in the second direction D2 may be greater than the width of the first storage film ML1. The second storage film ML2 may include a second storage film connection portion ML2_R located at the boundary between the third stack CE3 and the fourth stack CE4. The width between the outer wall and the inner wall of the second storage film connection portion ML2_R in the second direction D2 may be greater than the width of the second storage film ML2.

[0135] The channel film CL may include: a first channel connection portion adjacent to the first storage film connection portion ML1_R, a second channel connection portion adjacent to the second storage film connection portion ML2_R, and a channel interpolation portion located at the boundary between the first storage film ML1 and the second storage film ML2.

[0136] A method of manufacturing a semiconductor memory device according to this embodiment will be described. The first stack CE1 and the first hole HO1 may be formed, the second stack CE2 and the second hole HO2 may be formed, and then the first storage film ML1 may be formed.

[0137] The third stack CE3 and the third hole HO3 may be formed, the fourth stack CE4 and the fourth hole HO4 may be formed, and then the second storage film ML2 may be formed.

[0138] Subsequently, the channel film CL and the filling film FI passing through the first to fourth stacks CE1, CE2, CE3, and CE4 may be formed.

[0139] Figure 9 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0140] Except as described below, the semiconductor memory device according to this embodiment is similar to the semiconductor memory device according to Figure 7 .

[0141] Refer to Figure 9, the channel structure CST of the semiconductor memory device according to the present embodiment may include: a first barrier film BI1 in the first stack CE1, a second barrier film BI2 in the second stack CE2, a third barrier film BI3 in the third stack CE3, and a fourth barrier film BI4 in the fourth stack CE4. Each of the first to fourth barrier films BI1, BI2, BI3, and BI4 may include a barrier pattern portion.

[0142] The channel structure CST may have a first storage film DS1 passing through the first stack CE1 and the second stack CE2, and a second storage film DS2 passing through the third stack CE3 and the fourth stack CE4. Each of the first storage film DS1 and the second storage film DS2 may include a storage sidewall and a storage interpolation portion connecting the storage sidewalls to each other. The storage interpolation portion may include a portion having a width greater than the width of the storage sidewall portion.

[0143] The channel structure CST may include a tunnel film TI, which is formed as a single, continuous element passing through the first to fourth stacks CE1, CE2, CE3, and CE4. The tunnel film TI may include a tunnel interpolation portion connecting the tunnel sidewall portions to each other. Each tunnel interpolation portion may include a portion having a width greater than the width of the tunnel sidewall portion.

[0144] A method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described. The first stack CE1, the first hole HO1, and the first barrier film BI1 may be formed, the second stack CE2, the second hole HO2, and the second barrier film BI2 may be formed, and then the first storage film DS1 may be formed.

[0145] The third stack CE3, the third hole HO3, and the third barrier film BI3 may be formed, the fourth stack CE4, the fourth hole HO4, and the fourth barrier film BI4 may be formed, and then the second storage film DS2 may be formed.

[0146] Subsequently, a tunnel film TI, a channel film CL, and a filling film FI passing through the first to fourth stacks CE1, CE2, CE3, and CE4 may be formed.

[0147] Figure 10 is a block diagram showing the configuration of a storage system according to an embodiment of the present disclosure.

[0148] Reference Figure 10 , a storage system 1100 according to an embodiment of the present disclosure includes a storage device 1120 and a memory controller 1110.

[0149] The storage device 1120 may include reference Figure 1 , Figure 2A and Figure 2B , Figure 4A andFigure 4B , Figure 6A and Figure 6B , Figure 7 , Figure 8 or Figure 9 the structures described. The storage device 1120 may be a multi-chip package configured by a plurality of flash memory chips.

[0150] The memory controller 1110 is configured to control the storage device 1120 and may include a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an error correction code circuit (ECC) 1114, and a memory interface 1115. The SRAM 1111 serves as the working memory of the CPU 1112. The CPU 1112 performs all control operations for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of the host connected to the storage system 1100. In addition, the ECC circuit 1114 detects and corrects errors included in the data read from the storage device 1120, and the memory interface 1115 performs interaction with the storage device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) that stores code data for interaction with the host.

[0151] The above storage system 1100 may be a memory card or a solid state drive (SSD) that combines the storage device 1120 and the memory controller 1110. For example, when the storage system 1100 is an SSD, the memory controller 1110 may communicate with an external (e.g., host) through at least one of the following various interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0152] Figure 11 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0153] Refer to Figure 11 , a computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a storage system 1210, which are electrically connected to a system bus 1260. In addition, when the computing system 1200 is a mobile device, it may further include a battery for supplying operating voltage to the computing system 1200, and may further include an application chipset, a camera image signal processor (CIS), and mobile DRAM, etc.

[0154] As described in the reference Figure 10 The storage system 1210 may be composed of a storage device 1212 and a memory controller 1211. The storage device 1212 may include the reference Figure 1 , Figure 2A and Figure 2B , Figure 4A and Figure 4B , Figure 6A and Figure 6B , Figure 7 , Figure 8 or Figure 9 the described structure.

[0155] Although the present invention has been described with reference to specific embodiments, after reading this disclosure, the present invention may be implemented according to other embodiments or their variations that are readily conceivable by those skilled in the art of the present invention without departing from the scope and spirit of the present invention defined by the appended claims.

Claims

1. A semiconductor memory device, comprising: a first stack including a first hole; a second stack disposed on the first stack and including a second hole connected to the first hole; a first storage film formed along an inner sidewall of the first hole; a second storage film formed along an inner sidewall of the second hole; and a channel film formed along inner sidewalls of the first storage film and the second storage film, wherein the channel film is a single, continuous element, and wherein at least a part of an upper surface of the first storage film contacts a lowermost conductive pattern among conductive patterns included in the second stack.

2. The semiconductor memory device according to claim 1, wherein the channel film includes: a first channel sidewall portion formed along the inner sidewall of the first storage film; a second channel sidewall portion formed along the inner sidewall of the second storage film; and a channel interpolation portion connecting the first channel sidewall portion and the second channel sidewall portion to each other.

3. The semiconductor memory device according to claim 2, wherein the channel interpolation portion includes a first channel connection portion connected to the second channel sidewall portion, and a width between an outer sidewall and an inner sidewall of the first channel connection portion is greater than each of widths of the first channel sidewall portion and the second channel sidewall portion.

4. The semiconductor memory device according to claim 3, wherein the channel interpolation portion further includes a second channel connection portion connected to the first channel sidewall portion, and a width between an outer sidewall and an inner sidewall of the second channel connection portion is greater than each of widths of the first channel sidewall portion and the second channel sidewall portion.

5. The semiconductor memory device according to claim 4, wherein the channel interpolation portion further includes a third channel connection portion connecting the first channel connection portion and the second channel connection portion, and a width between an outer sidewall and an inner sidewall of the third channel connection portion is the same as each of widths of the first channel sidewall portion and the second channel sidewall portion.

6. The semiconductor memory device according to claim 1, further comprising: a filling film formed in the channel film, wherein the filling film is a single, continuous element.

7. The semiconductor memory device according to claim 6, wherein the filling film includes: a lower portion formed in the first hole; an upper portion formed in the second hole; and a filling connection portion connecting the lower portion and the upper portion, wherein a maximum width of the filling connection portion is less than a minimum width of the upper portion.

8. The semiconductor memory device according to claim 1, wherein the second storage film includes: a tunnel film surrounding the channel film; a storage film surrounding the tunnel film; and a blocking film surrounding the storage film.

9. The semiconductor memory device according to claim 8, wherein the tunnel film includes a tunnel sidewall portion and a tunnel pattern portion, and a width between an outer sidewall and an inner sidewall of the tunnel pattern portion is greater than a width of the tunnel sidewall portion.

10. The semiconductor memory device according to claim 8, wherein, the storage film includes a storage sidewall portion and a storage pattern portion, and the width between the outer sidewall and the inner sidewall of the storage pattern portion is greater than the width of the storage sidewall portion.

11. A semiconductor memory device, comprising: a first stack; a second stack disposed on the first stack; a first hole passing through the first stack in a vertical direction; a first barrier film and a first storage film formed sequentially along the inner sidewall of the first hole; a second hole passing through the second stack in the vertical direction; a second barrier film and a second storage film formed sequentially along the inner sidewall of the second hole; a tunnel film formed along the inner sidewall of the first storage film and the inner sidewall of the second storage film; and a channel film formed in the tunnel film, wherein the first storage film and the second storage film are spaced apart from each other, and the second barrier film is interposed therebetween.

12. The semiconductor memory device according to claim 11, wherein, the first barrier film and the second barrier film are spaced apart from each other.

13. The semiconductor memory device according to claim 11, wherein, the tunnel film includes: a first tunnel sidewall portion formed along the inner sidewall of the first storage film; a second tunnel sidewall portion formed along the inner sidewall of the second storage film; and a tunnel interpolation portion connecting the first tunnel sidewall portion and the second tunnel sidewall portion to each other.

14. The semiconductor memory device according to claim 13, wherein, the tunnel interpolation portion includes a first tunnel connection portion connected to the second tunnel sidewall portion, and the width between the outer surface and the inner surface of the first tunnel connection portion is greater than the width of each of the first tunnel sidewall portion and the second tunnel sidewall portion.

15. A method of manufacturing a semiconductor memory device, the method comprising: forming a first stack including a first hole; forming a first storage film and a channel sacrifice pattern in the first hole; forming a second stack including a second hole on the first stack; forming a first initial storage film along the inner sidewall of the second hole; removing the channel sacrifice pattern exposed through the second hole; and forming a channel film in the first hole and the second hole from which the channel sacrifice pattern has been removed, wherein the channel film protrudes toward the center of the second hole at a level corresponding to the lowermost conductive pattern among the conductive patterns included in the second stack.

16. The method according to claim 15, wherein, forming the first storage film and the channel sacrifice pattern includes: forming a second initial storage film along the surface of the first stack; filling a channel sacrifice film in the first hole in which the second initial storage film is formed; and forming the first storage film and the channel sacrifice pattern by performing a planarization process to expose the upper surface of the first stack.

17. The method according to claim 16, wherein, the channel sacrifice film has an etching selectivity with respect to the second initial storage film.

18. The method according to claim 17, Among them, the channel sacrificial film includes a metal material with an etching rate higher than that of the second initial storage film.

19. The method according to claim 15, wherein, the channel film is formed simultaneously in the first hole and the second hole.

Images