2T2R unit-based area efficient resistive random access memory array reinforcement layout structure and manufacturing method
By adopting the design of common source stacked 2T2R units and well contact in the resistive variable memory array, the bottleneck and process volatility problems of 1T1R resistive variable memory cell integration are solved, and efficient storage density and reliability are achieved.
Patent Information
- Application Number
- CN202510337525.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-13
AI Technical Summary
The existing 1T1R resistive variable memory units have bottlenecks to improve the integration degree, and memory manufacturing has process volatility problems, resulting in read and write errors.
The layout structure is reinforced by an area-efficient resistive variable memory array based on 2T2R units. The common source stacking 2T2R units and well contact design is used to realize structural multiplexing and spatial compression, and process deviation is reduced through complementary structural design.
It significantly improves storage density and area efficiency, reduces read and write errors, and improves memory integration and reliability.
Smart Images
Figure CN120152297A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to an area-efficient resistive random access memory (RRAM) array reinforced layout structure based on 2T2R cells and a manufacturing method therefor. Background Art
[0002] The most common RRAM cell structure is a 1T1R RRAM cell structure composed of a memory resistor and a select transistor, as Figure 1 shown: One end of the memory resistor 101 is connected to the drain of the select transistor 102, and the other end leads out the bit line BL of the RRAM cell; the gate of the select transistor 102 leads out the word line WL of the RRAM cell, and the source leads out the source line SL of the RRAM cell. Figure 1 also shows the layout structure of the 1T1R RRAM cell. The drain leads out the bit line BL after passing through the resistive device layer 200, the gate leads out the word line WL, and the source leads out the source line SL.
[0003] In the 1T1R RRAM cell, the word line WL is used to provide a select control signal, and the bit line BL and the source line SL are used to provide read / write operation signals. Since the word line WL is connected to the gate of the select transistor, and the gate of the select transistor is isolated from the source and the drain, the select control signal and the read / write control signal are independent of each other, making the 1T1R RRAM cell applicable to most memories. Usually, the area of the select transistor determines the area of the 1T1R RRAM cell, and the size of the select transistor must meet the requirement of passing the current for the write operation of the resistive random access memory, thereby restricting the scale of the RRAM array and becoming a bottleneck for improving the integration degree of the resistive random access memory.
[0004] In addition, there are process fluctuation problems during the manufacturing of memories, that is, there are process deviations for different chips on the same wafer or even different memory cells in the same chip, resulting in deviations in the characteristics of the memories and causing read / write errors.
[0005] Based on this, the present invention proposes an area-efficient RRAM array reinforced layout structure based on 2T2R cells and a manufacturing method therefor. Summary of the Invention
[0006] In order to solve the above problems in the prior art, that is, the 1T1R RRAM cell has a bottleneck in improving the integration degree, and there are process fluctuation problems in the manufacturing of memories, resulting in read / write error problems, the present invention provides an area-efficient RRAM array reinforced layout structure based on 2T2R cells and a manufacturing method therefor.
[0007] The first aspect of the present invention proposes an area - efficient resistive - random - access - memory (RRAM) array reinforcement layout structure based on 2T2R cells, including n common - source - stacked 2T2R cells connected along the word - line WL direction and well contacts.
[0008] The common - source - stacked 2T2R cell is composed of two complementary common - gate 2T2R cells stacked vertically with a common source, and the 2T2R cell is composed of two 1T1R resistive - random - access - memory cells with common gates arranged horizontally.
[0009] The well contacts are arranged on both sides of the outermost common - source - stacked 2T2R cells.
[0010] Furthermore, the 2T2R cell includes:
[0011] Two select transistors arranged horizontally;
[0012] The word - line WL led out from the common gate of the two select transistors; the bit - line BL and the bit - line BLB led out from the drains of the two resistive - random - access - memory devices respectively; the source - line SL and the source - line SLB led out from the sources respectively.
[0013] Furthermore, the common - source - stacked 2T2R cell includes: two 2T2R cells stacked with a common source and symmetrically arranged vertically. After stacking, two rows of word - lines WL are controlled by two gates respectively;
[0014] The two bit - lines BL in the same column of the two 2T2R cells are connected, and the two bit - lines BLB in the same column are connected;
[0015] The sources in the same column of the two 2T2R cells are shared and lead out the corresponding source - line SL and source - line SLB.
[0016] Furthermore, the spacing of the well contacts does not exceed the maximum spacing specified by the process, and the layout of the well contacts meets the minimum width requirement of the substrate source region.
[0017] Furthermore, n satisfies: n×d≤2S;
[0018] where d is the width of a single common - source - stacked 2T2R cell, and S is the maximum well - contact spacing allowed by the process.
[0019] Furthermore, n is an integer multiple of 2.
[0020] Furthermore, the minimum RRAM array cell is 2 rows×2n columns, where:
[0021] Two word - lines WL control two rows of the array respectively; n bit - lines BL and n bit - lines BLB are staggered and complementary, and each pair of bit - lines corresponds to 2n columns of the array cells;
[0022] The source line SL and the source line SLB form a pair of interleaved source lines, which are led out through a common source structure.
[0023] The second aspect of the present invention proposes a manufacturing method for a layout-optimized area-efficient resistive random access memory (RRAM) array based on 2T2R cells, based on a layout-optimized area-efficient RRAM array structure based on 2T2R cells. The manufacturing method includes:
[0024] Step S1: Prepare a select transistor and a resistive device layer of a complementary common-gate 2T2R cell on a substrate.
[0025] Step S2: Stack two upper and lower complementary common-gate 2T2R cells through a metal interconnect layer to form a common-source stacked 2T2R cell.
[0026] Step S3: Multiplex a plurality of common-source stacked 2T2R cells along the word line direction to form a minimum memory array unit.
[0027] Step S4: Add well contacts on both sides of the minimum memory array unit, and verify whether the well contact pitch and the metal layer design meet the minimum design rules of the process.
[0028] Further, the minimum design rules of the process include: gate density, metal pitch, and minimum width of the substrate source region.
[0029] Advantages of the present invention:
[0030] Breakthrough in area efficiency and integration
[0031] Common-source stacked 2T2R cell stacking design: By stacking two upper and lower complementary common-gate 2T2R cells with a common source, structure reuse and space compression are achieved. In a traditional 1T1R cell, each memory cell requires an independent select transistor, while in this design, by sharing the gate and source connections, redundant area is effectively reduced, and the storage density per unit area is significantly increased.
[0032] Self-optimized process rule: Through the symmetry and compactness design of the layout (such as external well contacts and lateral arrangement of common gates), the process design rules are utilized to the maximum extent, reducing the overall area of the cell and providing a basis for the large-scale production of high-density memory arrays.
[0033] Process variation suppression and reliability improvement
[0034] Complementary structure deviation compensation: In the 1T1R cells with left and right common gates, by sharing the same gate signal, the influence of gate process deviation on the selection consistency is reduced; the upper and lower stacked 2T2R cells adopt a complementary design, so that the resistance / transistor parameter differences caused by process variations cancel each other out, significantly reducing read / write errors.
[0035] Well Contact Optimization and Radiation Hardening Enhancement: The well contacts are distributed on the outermost sides of the array, forming a stable substrate potential barrier. This not only reduces crosstalk between adjacent cells but also quickly discharges parasitic charges caused by radiation, enhancing the radiation resistance ability. It is applicable to high-reliability scenarios such as aerospace. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:
[0037] Figure 1 is a schematic structural diagram of a 1T1R cell in the prior art;
[0038] Figure 2 is a schematic structural diagram of a 2T2R cell in an area-efficient resistive random access memory (RRAM) array reinforcement layout structure based on 2T2R cells according to the present invention;
[0039] Figure 3 is a schematic structural diagram of a common-source stacked 2T2R cell in an area-efficient resistive random access memory (RRAM) array reinforcement layout structure based on 2T2R cells according to the present invention;
[0040] Figure 4 is the minimum resistive random access memory (RRAM) array cell composed of 8 multiplexed common-source stacked 2T2R cells in an area-efficient resistive random access memory (RRAM) array reinforcement layout structure based on 2T2R cells according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the related invention and not for limiting the invention. Additionally, it should be noted that for the sake of description, only parts related to the relevant invention are shown in the drawings.
[0042] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.
[0043] The present invention provides an area-efficient resistive random access memory (RRAM) array reinforcement layout structure based on 2T2R cells, including n common-source stacked 2T2R cells connected in the word line WL direction and well contacts 100;
[0044] The common-source stacked 2T2R cell is formed by stacking two complementary common-gate 2T2R cells with a common source, and the 2T2R cell is composed of two 1T1R resistive random access memory cells with common gates arranged left and right;
[0045] The well contacts are arranged on both sides of the outermost common-source stacked 2T2R cells.
[0046] Among them, the 2T2R unit includes: two gating transistors arranged left and right;
[0047] A word line WL led out from the common gate of the two gating transistors; a bit line BL and a bit line BLB respectively led out from the drain electrodes of the two to the resistive switching device layer 200; a source line SL and a source line SLB respectively led out from the two source electrodes.
[0048] The common-source stacked 2T2R unit includes:
[0049] Two 2T2R units that are common-source stacked and symmetrically arranged up and down. After stacking, two rows of word lines WL are controlled by two gates respectively;
[0050] Two bit lines BL in the same column of the two 2T2R units are connected, and two bit lines BLB in the same column are connected;
[0051] The source electrodes in the same column of the two 2T2R units are shared and lead out the corresponding source lines SL and source lines SLB.
[0052] Among them, the pitch of the well contacts does not exceed the maximum pitch specified by the process, and the layout of the well contacts meets the minimum width requirement of the substrate source region. The n satisfies:
[0053] n×d≤2S;
[0054] Among them, d is the width of a single common-source stacked 2T2R unit, S is the maximum well contact pitch allowed by the process. Considering binary storage units, n should also be set to an integer multiple of 2.
[0055] The minimum resistive switching memory array unit is 2 rows × 2n columns, where:
[0056] Two word lines WL respectively control two rows of the array; n bit lines BL and n bit lines BLB are staggered and complementary, and each pair of bit lines respectively corresponds to 2n columns of the array unit;
[0057] The source lines SL and source lines SLB form a pair of staggered source lines and are led out through a common-source structure.
[0058] In this embodiment, the maximum well contact pitch S of the selected process is 30um, and the width d of a single common-source stacked 2T2R unit is 6.5um. According to nd≤2S, the maximum value of n can be calculated as 9; in order to meet the integer multiple of 2, n should be taken as 8. Therefore, in this example, the common-source stacked 2T2R unit is multiplexed 8 times in the word line WL direction to form a custom minimum resistive switching memory array unit of 2 rows × 16 columns.
[0059] Therefore, the common-source stacked 2T2R cells are multiplexed 8 times in the word line WL direction, thus forming a resistive memory array layout structure of 2 rows and 16 columns, which includes word lines WL(0:1), interleaved bit lines BL(0:7) and BLB(0:7), and interleaved source lines SL and SLB. As Figure 4 shown, two gates respectively control the two rows of word lines WL; the interleaved independent bit lines BL-0, BLB-0, BL-7, BLB-7; the interleaved source lines SL, SLB; the intermediate multiplexed part is also omitted in the figure;
[0060] Then, appropriate well contacts are added to both sides of the 2-row and 16-column resistive memory array, and the minimum design rules of the process are satisfied, such as gate density, metal pitch, and minimum width of the substrate source region. Finally, a 2-row × 16-column custom minimum resistive memory array cell is completed.
[0061] The second aspect of the present invention proposes a manufacturing method for an area-efficient resistive memory array reinforced layout based on 2T2R cells. Based on an area-efficient resistive memory array reinforced layout structure based on 2T2R cells, the manufacturing method includes:
[0062] Step S1, preparing a gated transistor and a resistive device layer of a complementary common-gate 2T2R cell on a substrate;
[0063] Step S2, stacking the upper and lower complementary common-gate 2T2R cells into a common-source stacked 2T2R cell through a metal interconnection layer;
[0064] Step S3, multiplexing multiple common-source stacked 2T2R cells along the word line direction to form a minimum memory array cell;
[0065] Step S4, adding well contacts on both sides of the minimum memory array cell, and verifying whether the well contact pitch and the metal layer design meet the minimum design rules of the process.
[0066] Furthermore, the minimum design rules of the process include: gate density, metal pitch, and minimum width of the substrate source region.
[0067] In the description of the present invention, terms indicating directions or positional relationships such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings. This is only for convenience of description and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present invention. In addition, terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0068] In addition, it should be noted that in the description of the present invention, unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0069] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device comprising a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to these process, method, article, or apparatus / device.
[0070] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.
Claims
1. An area efficient resistive switching memory array reinforcement layout structure based on 2T2R cells, characterized in that: It includes n common source stacked 2T2R units and well contacts arranged and connected along the word line WL direction; The common source stacked 2T2R unit is composed of two complementary common gate 2T2R units stacked with a common source, and the 2T2R unit is composed of two common gate 1T1R resistive memory units placed on the left and right. The well contacts are arranged on two sides of the common source stacked 2T2R units on the two sides.
2. According to claim 1, an area efficient resistive switching memory array reinforcement layout structure based on 2T2R units is characterized in that: The 2T2R unit includes: Two gate transistors placed left and right; The two gate transistors have a word line WL led out from the common gate; the two drains have a bit line BL and a bit line BLB led out from the resistive device layer respectively; the two sources have a source line SL and a source line SLB led out respectively.
3. According to claim 2, an area efficient resistive switching memory array reinforcement layout structure based on 2T2R units is characterized in that: The common source stacked 2T2R unit comprises: Two 2T2R cells with a common source stacked and symmetrically arranged up and down, after stacking, two gates are used to control two rows of word lines WL respectively; The two bit lines BL in the same column of the two 2T2R cells are connected, and the two bit lines BLB in the same column are connected; The sources in the same column of the two 2T2R cells are shared and lead to corresponding source lines SL and SLB.
4. According to claim 1, an area efficient resistive switching memory array reinforcement layout structure based on 2T2R units is characterized in that: The spacing of the well contacts does not exceed the maximum spacing specified by the process, and the layout of the well contacts meets the minimum width requirement of the substrate source region.
5. According to claim 1, an area efficient resistive switching memory array reinforcement layout structure based on 2T2R units is characterized in that: The n satisfies: n×d≤2S; Wherein, d is the width of a single common-source stacked 2T2R unit, and S is the maximum well contact spacing allowed by the process.
6. The area efficient resistive switching memory array reinforcement layout structure based on 2T2R unit according to claim 5, characterized in that: n is an integer multiple of 2.
7. The area efficient resistive switching memory array reinforcement layout structure based on 2T2R unit according to claim 6, characterized in that: The minimum resistive memory array unit is 2 rows × 2n columns, where: Two word lines WL control two rows of the array respectively; n bit lines BL and n bit lines BLB are interlaced and complementary, and each pair of bit lines corresponds to 2n columns of the array unit; The source line SL and the source line SLB form a pair of staggered source lines and are led out through a common source structure.
8. A method for manufacturing an area efficient resistive switching memory array reinforcement layout based on 2T2R units, based on an area efficient resistive switching memory array reinforcement layout structure based on 2T2R units according to any one of claims 1 to 7, characterized in that: The manufacturing method comprises: Step S1, preparing a gate transistor and a resistive switching device layer of a complementary common-gate 2T2R unit on a substrate; Step S2, stacking the upper and lower complementary common-gate 2T2R units into a common-source stacked 2T2R unit through a metal interconnection layer; Step S3, multiplexing a plurality of common source stacked 2T2R units along the word line direction to form a minimum memory array unit; Step S4, adding well contacts on both sides of the minimum memory array unit, and verifying whether the well contact spacing and metal layer design meet the minimum design rules of the process.
9. The method for manufacturing an area efficient resistive switching memory array reinforcement layout based on 2T2R units according to claim 8, characterized in that: The minimum design rules of the process include: gate density, metal spacing and minimum width of substrate source region.