P type-Si and N-Ga2O3 heterojunction diode

Abstract

The invention provides a P-type-Si and N-Ga2O3 heterojunction diode. The P-type-Si and N-Ga2O3 heterojunction diode comprises a cathode ohmic electrode, a substrate, a drift layer, a P region, oxide dielectric layers and an anode ohmic electrode, wherein the cathode ohmic electrode, the substrate and the drift layer are arranged from bottom to top; the P region is positioned above the drift layer; the two ends of the P region are of a stepped structure extending towards the two sides from bottom to top. The lower surface of the oxide dielectric layer is located on the drift layer, and the upper surface of the oxide dielectric layer is as high as the P region; the anode ohmic electrode covers the upper surface of the P region, and the two sides of the anode ohmic electrode extend outwards to cover part of the oxide dielectric layer to form a metal field plate layer; the material of the substrate is N-type heavily doped Ga2O3; the drift layer is made of N-type lightly doped Ga2O3; and the material of the P region is P-type heavily doped Si. The P type-Si and N-Ga2O3 heterojunction diode disclosed by the invention can be used as a base material of a p-n-p Ga2O3-based bipolar diode, can be applied to a gate drive circuit, and has excellent performance of high voltage resistance and low on-resistance at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of heterojunction diodes, and particularly relates to a P-type-Si and N-type-Ga 2 O 3 heterojunction diode. Background Art

[0002] Gallium oxide (Ga 2 O 3 ) has a bandgap of 4.9 eV and a breakdown field with a predicted value of up to 8 MV / cm, making it one of the most promising materials among wide-bandgap semiconductors. Its electron mobility is 300 cm² / V·s, resulting in excellent performance in high-power electronic devices. The power Baliga figure of merit of gallium oxide is 3444, which is 10 times that of silicon carbide (SiC) and 4 times that of gallium nitride (GaN), showing its great application prospects in high-temperature, high-voltage, and high-frequency electronic devices.

[0003] Currently, the research on Ga 2 O 3 power devices mainly focuses on the structural design and device fabrication technology of Schottky barrier diodes (SBDs), field-effect transistors (FETs), and heterojunction diodes. However, gallium oxide faces many challenges in practical applications. Due to the local self-limiting phenomenon of holes in gallium oxide, the realization of p-type gallium oxide is difficult, which has become the main bottleneck hindering its wide application. To solve this problem, researchers are exploring the introduction of appropriate heterojunction p-type materials and the combination of heterojunction structures to achieve efficient gallium oxide-based power devices. This idea not only helps to overcome the limitations of p-type doping but also improves the thermal performance and overall working efficiency of the devices.

[0004] Currently, in the methods of hetero-integrating Ga 2 O 3 with other p-type materials, heterojunction PN junction diodes based on nickel oxide (NiO) / gallium oxide (Ga 2 O 3 ), cuprous oxide (Cu 2 O) / gallium oxide, P-GaN / N-Ga 2 O 3 and tin oxide (SnO) / gallium oxide have been widely reported and shown excellent electrical characteristics. Among them, p-NiO / Ga 2 O 3 and p-Cu 2 O / Ga 2 O 3The diode achieves a high breakdown voltage, demonstrating its great potential in high-voltage applications. However, using oxide semiconductor materials as the P region has significant technical limitations: First, due to the polycrystalline nature of oxide materials, the carrier mobility decreases, and its high defect density limits device performance, making it difficult to serve as the core material of n-p-n Ga 2 O 3 bipolar transistors and difficult to integrate; Second, forming a heterojunction with oxide semiconductor materials and gallium oxide is difficult to apply in gate drive circuits.

[0005] In contrast, hetero-integrating Ga 2 O 3 with P-type -Si has significant advantages. Silicon materials have high-quality single-crystal growth technology and low defect density, which can significantly improve carrier mobility and device stability. At the same time, the mature processing technology of silicon and its extensive industrial foundation support its flexible integration in gate drive circuits. Through the hetero-bonding of silicon and gallium oxide, not only can device performance be further optimized, but seamless compatibility with silicon-based processes can also be achieved. However, such devices face problems of large on-resistance and low breakdown voltage, limiting their further application in high-voltage and high-frequency fields. J. Gong et al. first used the grafting technique to prepare Si / β-Ga 2 O 3 p-n junction heterojunction diodes in 2023 (arXiv:2305.19138 [physics.app-ph]). Compared with techniques such as wafer bonding, glass, and nano-film transfer, it has good diode characteristics, and the breakdown voltage is in the range of 20 - 25V. Currently, the highest figure of merit for experimentally prepared devices comes from the heterojunction device of the University of Wisconsin-Madison in March 2024 (IEEE Electron Device Letters (Volume: 45, Issue: 3, March 2024)), with a figure of merit of approximately 96.7 MW·cm -2 , and the breakdown voltage is 0.86KV. Summary of the Invention

[0006] In view of this, to solve the above technical problems, the present invention proposes a P-type -Si and N-type -Ga 2 O 3 heterojunction diode. By making full use of the high-quality single-crystal growth technology and low defect density of silicon materials, the carrier mobility and device stability are significantly improved, providing a basis for the subsequent development of gallium oxide-based triodes and the circuit integration of gallium oxide devices. At the same time, through reasonable structural design, the problems of large on-resistance and low breakdown voltage faced by such devices are overcome.

[0007] To achieve the above object, the technical solution of the present invention is implemented as follows:

[0008] A P-type - Si and N-type - Ga 2 O 3 heterojunction diode, comprising a cathode ohmic electrode, a substrate, and a drift layer sequentially arranged from bottom to top; further comprising a P region above the drift layer, oxide dielectric layers on both sides of the P region, and an anode ohmic electrode above the P region; both ends of the P region are in a stepped structure that expands laterally from bottom to top; the oxide dielectric layers are in stepped contact and fit with both sides of the P region, the lower surface of the oxide dielectric layer is located on the drift layer, and the upper surface is at the same height as the P region; the anode ohmic electrode covers the upper surface of the P region, and both sides extend outward to cover part of the oxide dielectric layer, forming a metal field plate layer; the material of the substrate is N-type heavily doped Ga 2 O 3 ; the material of the drift layer is N-type lightly doped Ga 2 O 3 ; the material of the P region is P-type heavily doped Si.

[0009] Both ends of the P region adopt a stepped structure that expands laterally from bottom to top. At the same time, the structure of the oxide dielectric layer is adaptively processed so that the oxide dielectric layer is in stepped contact and fit with both sides of the P region. Then, both sides of the anode ohmic electrode covering the upper surface of the P region extend outward to cover part of the oxide dielectric layer, forming a metal field plate layer. Such a structural design reduces the electric field strength below the P region, alleviates the electric field concentration, and improves the reverse breakdown voltage of the heterojunction diode.

[0010] Silicon, as the P-type semiconductor material of the Ga 2 O 3 heterojunction diode, combines with N-type gallium oxide. Through heavy doping, a low conduction voltage is achieved, thereby significantly reducing the power loss of the device. At the same time, P-type silicon and Ga 2 O 3 have good stability and low contact resistance at the interface, avoiding the high barrier problem of oxide materials, and can significantly improve the electrical performance of the device.

[0011] In some preferred embodiments of the P-type - Si and N-type - Ga 2 O 3 heterojunction diode of the present invention, the material of the cathode ohmic electrode is one of a mixture of Ni, Pt, Ti, and Au, Au, Ag, Cu, W; the material of the oxide dielectric layer is SiO 2 , Al 2 O 3 , HfO 2 , Cu 2O, ZnO, TiO 2 , Si 3 N 4 One of them; the material of the anode ohmic electrode is one of Ni, Pt, Ti and Au mixed material, Au, Ag, Cu, W.

[0012] The materials of the cathode ohmic electrode and the anode ohmic electrode are both preferably Ni, and the material of the oxide dielectric layer is preferably SiO 2 , nickel can form an ohmic contact with the P region, significantly reducing the contact resistance, optimizing the forward conduction characteristics, and improving the device efficiency. At the same time, nickel has excellent thermal stability and mechanical properties, and can maintain stable interface characteristics in a high-temperature environment, which is suitable for high-power devices. In addition, nickel can form low-resistance nickel silicide (NiSi) with silicon during the high-temperature annealing process, further improving the interface electrical properties.

[0013] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the thickness of the cathode ohmic electrode is 0.2 - 0.8 μm; the thickness of the anode ohmic electrode is 0.4 - 1.0 μm.

[0014] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, in the material of the substrate, the doping concentration N 2 O 3 of the N-type heavily doped Ga d is 1.8×10 19 cm -3 ; in the material of the drift layer, the doping concentration N 2 O 3 of the N-type lightly doped Ga d is 3.0×10 15 cm -3 to 7.4×10 15 cm -3 ; in the material of the P region, the doping concentration N a of the P-type heavily doped Si is 2.0×10 20 cm -3 .

[0015] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, in the material of the drift layer, the doping concentration N 2 O 3 of the N-type lightly doped Ga d is 6.6×10 15 cm-3 。

[0016] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the thickness T of the substrate is s 2 - 6 μm; the thickness T of the drift layer is d 8 - 12 μm.

[0017] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the number N of steps at both ends of the P region is 2 - 8, the height of each step is 0.5 - 1.0 μm, and the width is 0.2 - 0.8 μm.

[0018] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the number N of steps at both ends of the P region is 6 - 8.

[0019] By optimizing the number of step layers and the height and width, the superimposed electric field strength at the step corners is reduced, the electric field concentration is further alleviated, and the reverse breakdown voltage of the heterojunction diode is greatly improved.

[0020] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the length L of the metal field plate layer is 2 - 5 μm.

[0021] In some preferred embodiments of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode, the length L of the metal field plate layer is 4 μm.

[0022] Design a metal field plate layer on the oxide dielectric layer. By optimizing the length of the metal field plate layer, the electric field distribution under the steps is made more uniform, and premature breakdown of the dielectric layer is avoided.

[0023] Compared with the prior art, the P-type -Si and N-type -Ga 2 O 3 heterojunction diode of the present invention has the following advantages:

[0024] (1) The P-type -Si and N-type -Ga 2 O 3The heterojunction diode uses silicon material as the P region to form a heterojunction diode with gallium oxide. Due to the single-crystal characteristics of silicon material, silicon has high-quality single-crystal growth technology and low defect density. When forming a heterojunction with gallium oxide, the carrier mobility and device stability can be significantly improved. At the same time, the mature processing technology of silicon and its extensive industrial foundation support its flexible integration in the gate drive circuit. Through the heterojunction of silicon and gallium oxide, not only can the device performance be further optimized, but also the seamless compatibility with silicon-based processes can be achieved.

[0025] (2)The P-type -Si and N-type -Ga described in the present invention 2 O 3 The heterojunction diode overcomes the problems of large on-resistance and low breakdown voltage faced by such devices through reasonable structural design. The breakdown voltage can be as high as 1.72 KV, and the figure of merit is 468 MW·cm -2 , and this figure of merit is about five times that of the highest figure of merit of currently experimentally prepared devices, showing superior characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 is the structural schematic diagram of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode of the present invention;

[0028] Figure 2 is the change of the breakdown voltage of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode of the present invention with the doping concentration of the drift layer;

[0029] Figure 3 is the change of the figure of merit (P-FOM) of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode of the present invention with the doping concentration of the drift layer;

[0030] Figure 4 is the change of the peak electric field intensity inside the dielectric layer with the applied reverse voltage under different metal field plate layer lengths of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode of the present invention;

[0031] Figure 5 is the P-type -Si and N-type -Ga described in the present invention 2 O 3Partial enlarged view at the steps of different numbers of steps N of the heterojunction diode; wherein, Figure 5 a is when N = 8, Figure 5 b is when N = 6, Figure 5 c is when N = 4, Figure 5 d is when N = 2, Figure 5 e is when N = 1;

[0032] Figure 6 For the P-type - Si and N-type - Ga of the present invention 2 O 3 Breakdown voltage at different numbers of steps N of the heterojunction diode;

[0033] Figure 7 For the P-type - Si and N-type - Ga of the present invention 2 O 3 Forward I-V characteristic curve and forward conduction resistance (R on ) of the heterojunction diode;

[0034] Figure 8 For the P-type - Si and N-type - Ga of the present invention 2 O 3 Schematic diagram of the preparation steps of the heterojunction diode.

[0035] Explanation of reference numerals:

[0036] 1 - Cathode ohmic electrode; 2 - Substrate; 3 - Drift layer; 4 - P region; 5 - Oxide dielectric layer; 6 - Anode ohmic electrode; 7 - Metal field plate layer. Detailed implementation manners

[0037] It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0038] The embodiments of the present application are described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation to the present application. On the contrary, the embodiments of the present application include all variations, modifications, and equivalents that fall within the spirit and scope of the appended claims.

[0039] The present invention will be described in detail below with reference to the drawings and in combination with embodiments.

[0040] Embodiment 1

[0041] As Figure 1 shown, a P-type - Si and N-type - Ga 2 O 3The heterojunction diode includes a cathode ohmic electrode 1, a substrate 2, and a drift layer 3 arranged in sequence from bottom to top. It also includes a P region 4 above the drift layer 3, oxide dielectric layers 5 on both sides of the P region 4, and an anode ohmic electrode 6 above the P region 4;

[0042] The material of the cathode ohmic electrode 1 is Ni; the thickness of the cathode ohmic electrode 1 is 0.2 μm;

[0043] The material of the substrate 2 is N-type heavily doped Ga 2 O 3 , with a doping concentration N d of 1.8×10 19 cm -3 ; the thickness T s of the substrate 2 is 2 μm;

[0044] The material of the drift layer 3 is N-type lightly doped Ga 2 O 3 , with a doping concentration N d of 3.0×10 15 cm -3 to 7.4×10 15 cm -3 ; the thickness T d of the drift layer 3 is 8 μm;

[0045] The material of the P region 4 is P-type heavily doped Si, with a doping concentration N a of 2.0×10 20 cm -3 ; both ends of the P region 4 are stepped structures that expand laterally from bottom to top. The number N of steps at both ends of the P region 4 is 8. Among them, the height of the first and second steps from bottom to top is 0.5 μm, the height of the remaining six steps is 1.0 μm, the width of the first and second steps is 0.5 μm, the width of the third step is 0.8 μm, the width of the fourth step is 0.4 μm, the width of the fifth step is 0.6 μm, the width of the sixth step is 0.2 μm, and the width of the seventh and eighth steps is 0.5 μm;

[0046] The material of the oxide dielectric layer 5 is SiO 2 ; the oxide dielectric layer 5 is in stepped contact fit with both sides of the P region 4. The lower surface of the oxide dielectric layer 5 is located on the drift layer 3, and the upper surface is at the same height as the P region 4;

[0047] The material of the anode ohmic electrode 6 is Ni; the anode ohmic electrode 6 covers the upper surface of the P region 4, and both sides extend outward to cover part of the oxide dielectric layer 5, forming a metal field plate layer 7. The length L of the metal field plate layer 7 is 4 μm; the thickness of the anode ohmic electrode 6 is 0.4 μm.

[0048] For P-type - Si and N-type - Ga 2 O 3 For the heterojunction diode, the doping concentration N of the drift layer 3 d will affect the forward conduction resistance and reverse breakdown voltage of the heterojunction diode. In Example 1, the doping concentration N of the drift layer 3 d The selection range is 3×10 15 cm -3 to 7.4×10 15 cm -3 ; A comparative study was conducted on the breakdown voltage and conduction resistance of the Ga d O 2 O 3 heterojunction diode at different doping concentrations N of the drift layer 3 Figure 2 , As shown in d , when the doping concentration N 2 is relatively low, the corresponding breakdown voltage is as high as 1.92 KV, but the corresponding conduction resistance is relatively high at 13.62 mΩ·cm d . As the doping concentration N d increases, the breakdown voltage shows a downward trend, and the conduction resistance also gradually decreases. Since the drift layer 3 is lightly doped, the electric field strength is concentrated at the junction of the oxide dielectric layer 5 and the drift layer 3. Therefore, the concentration N

[0049] As shown in Figure 3 , in order to obtain the optimal doping concentration, a parameter power figure of merit (P-FOM) that characterizes the performance of the power device is introduced. The power figure of merit of the device is calculated using formula (1), where R on in formula (1) is the conduction resistance and BV is the breakdown voltage. The doping concentration corresponding to the FOM turning point is defined as the optimal doping concentration of the device structure, and the optimal doping concentration of the drift layer 3 is obtained as 6.6×10 15 cm -3 .

[0050] FOM = BV 2 / R on (1).

[0051] Example 2

[0052] On the basis of Example 1, the difference from Example 1 is that: the doping concentration of the drift layer 3 in the P-type - Si and N-type - Ga 2 O 3 heterojunction diode is determined to be 6.6×10 15 cm -3 ; The doping concentration N a of the P region 4 is 2.0×10 20 cm -3 , The thickness T of the oxide dielectric layer 50x Take 0.8 μm; among them, the variables are the number of steps N and the length L of the metal field plate layer 7.

[0053] Use TCAD tools to study P-type -Si and N-type -Ga 2 O 3 The influence of different numbers of steps N and the length L of the metal field plate layer 7 on the breakdown voltage and the forward characteristics of the heterojunction diode. Ga 2 O 3 The bandgap and electron affinity of the material are set to 4.8 eV and 4.0 eV respectively, and the ionization calculation uses α(E) = 0.79×10 6 cm -1 exp[-(2.92×10 7 v / cm) / E]. In addition, considering the additional scattering caused by etching damage and SiO 2 / Ga 2 O 3 The mobility of the drift layer 3 at the contact surface of the drift layer 3 and the oxide dielectric layer 5 is set to the experimental value of 50 cm 2 / V·s due to the interface charge, and the mobility of the remaining drift layer 3 is 118 cm 2 / V·s. The work function of the electrode is 5.01 eV. The relative dielectric constant of the oxide dielectric layer 5 material is 3.99, and the critical breakdown field strength is taken as 8.5 MV·cm -1 .

[0054] By changing the length L of the metal field plate layer 7 and the number of steps N, calculate the electric field distribution and breakdown performance of the heterojunction diode device. The range of L change is 0 μm to 5 μm, and N takes 1, 2, 4, 6, 8. Observe the electric field distribution of different lengths L of the metal field plate layer 7 and find the optimal length L of the metal field plate layer 7. Then select the appropriate number of steps N and optimize the steps.

[0055] The first step: study the influence of the length L of the metal field plate layer 7 on the peak electric field strength at the lower part of the P region 4. Let the number of steps N be a fixed value of 8, and the peak electric field at the lower part of the P region 4 when the length of the metal field plate layer 7 is in the range of L = 0 μm to 5 μm. Figure 4 The electric field strength under different lengths L of the metal field plate layer 7 is shown. We take the critical breakdown field strength of SiO 2 as 8.5 MV·cm -2 , and when the critical breakdown field strength is reached, it is considered that the device breaks down. It can be seen from the figure that as the reverse voltage increases, the electric field strength at the lower part of the P region 4 gradually increases. In the case of no metal field plate layer 7, the device breaks down in advance, and the breakdown voltage is 1.50 KV. When the length of the metal field plate layer 7 is greater than 4 μm, the peak electric field tends to be stable, and the breakdown voltage of the device reaches 1.74 KV.

[0056] Step 2: Study the influence of the number of steps N on the breakdown voltage. The breakdown voltages with the number of steps N being 1, 2, 4, 6, and 8 are considered respectively. Figure 5 The step magnification diagrams for different numbers of steps N are shown. Figure 6 The breakdown voltages at different numbers of steps under different metal field plate layer lengths are shown. It can be seen from the figure that as the number of steps increases, the breakdown voltage gradually increases. When the number of steps is greater than 6, the breakdown voltage basically stabilizes. As the length L of the metal field plate layer 7 increases, the breakdown voltage of the device also increases. When N is 8, the breakdown voltages corresponding to the metal field plate layer 7 lengths of 0μm, 1μm, 2μm, 3μm, 4μm, and 5μm are 1.50 KV, 1.62 KV, 1.65 KV, 1.68 KV, 1.72 KV, and 1.74 KV respectively.

[0057] With the metal field plate layer length L being 4μm and the number of steps being 8, the forward I-V characteristic curve and the forward on-resistance (R on ) of the device are extracted, and the data and results are shown in Figure 7 .

[0058] In summary, the doping concentration N of the drift layer 3 d is from 3×10 15 cm -3 to 7.4×10 15 cm -3 In the range, the length L of the metal field plate layer 7 is from 2 to 5μm, and the number of steps N is from 2 to 8. The relevant performance parameters of the P-type -Si and N-type -Ga 2 O 3 heterojunction diodes are superior to the prior art (a heterojunction device from the University of Wisconsin - Madison in March 2024, with a figure of merit of about 96.7 MW·cm -2 , and a breakdown voltage of 0.86 KV). Among them, when the doping concentration N of the drift layer 3 d is 6.6×10 15 cm -3 , the length L of the metal field plate layer 7 is 4μm, and the number of steps N is 8, it is the optimal parameter design. Under this parameter, the reverse breakdown voltage V of the P-type -Si and N-type -Ga 2 O 3 heterojunction diode can reach 1.72 KV, the on-resistance R BR is 6.308 mΩ·cm on , and the figure of merit FOM is 468 MW·cm 2 . -2 .

[0059] In addition, as shown in Figure 8 , the P-type -Si and N-type -Ga in Example 1 and Example 22 O 3 The heterojunction diode is prepared as follows:

[0060] S1. Epitaxially grow a lightly doped Ga 2 O 3 drift layer 3 on the substrate 2 by metalorganic chemical vapor deposition (MOCVD);

[0061] S2. Deposit a SiO 2 thin film on the surface of the drift layer 3 by plasma-enhanced chemical vapor deposition (PECVD), and define a stepped structure region by photolithography;

[0062] S3. Etch the initial stepped structure layer by layer through a reactive ion etching (RIE) process. The etching depth and horizontal length are controlled by a multi-level photomask. Further, wet etching is used to optimize the transition region at the edge of each step to form a smoothly transitioning stepped profile. Finally, the photoresist is removed, and the sample is subjected to a thermal annealing treatment in the range of 400°C to 600°C to obtain the constructed oxide dielectric layer 5;

[0063] S4. Deposit a silicon thin film on the stepped structure by chemical vapor deposition (CVD). By adjusting the growth parameters, a relatively thin transition layer is formed on both sides of the step in the silicon thin film, while a relatively thick silicon layer is formed in the central region, thereby constructing a heterojunction structure. After deposition, the device is annealed at a high temperature again. The annealing temperature is preferably 800°C to 1000°C. After annealing is completed, a cleaning treatment is performed to remove by-products during the CVD process and surface impurities during the annealing process to obtain the constructed P region 4;

[0064] S5. Form a Ni ohmic contact electrode on the back of the substrate 2 by electron beam metal evaporation to obtain the cathode ohmic electrode 1;

[0065] S6. Deposit a Ni metal layer on the surface of the P region 4 and SiO 2 by sputtering or electron beam evaporation. Define the electrode pattern by photolithography. Then, use BCl 3 and Ar gases to perform reactive ion etching (RIE) to remove the metal in the unmasked area. Finally, anneal the electrode to construct the anode ohmic electrode 6, and finally obtain the P-type -Si and N-type -Ga 2 O 3 heterojunction diode.

Claims

1. A P-type Si and N-type Ga2O3 heterojunction diode, comprising a cathode ohmic electrode (1), a substrate (2) and a drift layer (3) arranged in sequence from bottom to top, characterized in that: It also includes a P region (4) located above the drift layer (3), an oxide dielectric layer (5) located on both sides of the P region (4), and an anode ohmic electrode (6) located above the P region (4); the two ends of the P region (4) are stepped structures extending from bottom to top to both sides; the oxide dielectric layer (5) is adapted to the stepped contacts on both sides of the P region (4), the lower surface of the oxide dielectric layer (5) is located on the drift layer (3), and the upper surface is highly consistent with the P region (4); the anode ohmic electrode (6) covers the upper surface of the P region (4), and the two sides extend outward to cover part of the oxide dielectric layer (5) to form a metal field plate layer (7); the material of the substrate (2) is N-type heavily doped Ga2O3; the material of the drift layer (3) is N-type lightly doped Ga2O3; the material of the P region (4) is P-type heavily doped Si.

2. The P-type Si and N-type Ga2O3 heterojunction diode according to claim 1, characterized in that: The material of the cathode ohmic electrode (1) is one of Ni, Pt, a mixed material of Ti and Au, Au, Ag, Cu, and W; the material of the oxide dielectric layer (5) is one of SiO2, Al2O3, HfO2, Cu2O, ZnO, TiO2, and Si3N4; and the material of the anode ohmic electrode (6) is one of Ni, Pt, a mixed material of Ti and Au, Au, Ag, Cu, and W.

3. The P-type Si and N-type Ga2O3 heterojunction diode according to claim 1, characterized in that: The thickness of the cathode ohmic electrode (1) is 0.2-0.8 μm; the thickness of the anode ohmic electrode (6) is 0.4-1.0 μm.

4. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 1, characterized in that: The doping concentration N of the N-type heavily doped Ga2O3 in the material of the substrate (2) is d 1.8×10 19 cm -3 The doping concentration N of the N-type lightly doped Ga2O3 in the material of the drift layer (3) is d 3.0×10 15 cm -3 to 7.4×10 15 cm -3 ; The doping concentration N of the P-type heavily doped Si in the P region (4) material a 2.0×10 20 cm -3 .

5. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 4, characterized in that: The doping concentration N of the N-type lightly doped Ga2O3 in the material of the drift layer (3) is d 6.6×10 15 cm -3 .

6. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 1, characterized in that: The thickness T of the substrate (2) s The drift layer (3) has a thickness T of 2 to 6 μm. d 8~12μm.

7. The P-type Si and N-type Ga2O3 heterojunction diode according to claim 1, characterized in that: The number N of steps at both ends of the P region (4) is 2 to 8, and the height of each step is 0.5 to 1.0 μm and the width is 0.2 to 0.8 μm.

8. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 7, characterized in that: The number N of steps at both ends of the P region (4) is 6 to 8.

9. The P-type Si and N-type Ga2O3 heterojunction diode according to claim 1, characterized in that: The length L of the metal field plate layer (7) is 2 to 5 μm.

10. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 9, characterized in that: The length L of the metal field plate layer (7) is 4 μm.

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