Monolithic integrated bridge circuit structure
By forming a multi-layer semiconductor structure on the substrate of the GaN HEMT device, the device is integrated on chip and electrical isolation are achieved, and the device is restricted by parasitic effects during interconnection is solved, the on-line characteristics and voltage resistance are improved, and the device reliability is improved.
Patent Information
- Application Number
- CN202510173180.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-06-13
AI Technical Summary
Existing GaN HEMT devices are limited by parasitic effects during interconnection, resulting in limited operating frequency and lack of avalanche breakdown capability, affecting reliability.
A monolithic integrated bridge circuit structure is proposed. By forming a multi-layer semiconductor structure on the substrate, the electrical isolation of different switching devices is achieved, and the on-chip integration and voltage resistance of the devices are improved through PN junction reverse bias and forward bias.
The on-conductive characteristics and voltage resistance characteristics of the switching device are improved, avoiding the limitations of the substrate effect on the device and improving the reliability of the device.
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Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor devices and integrated circuits, and particularly to a monolithic integrated bridge circuit structure. Background Art
[0002] In gallium nitride (GaN) devices, a two-dimensional electron gas channel with high electron mobility can be formed between the barrier layer and the channel layer by using the polarization effect, so as to realize the preparation of high electron mobility transistors (HEMTs). Therefore, GaN HEMTs can achieve better on-resistance and operating frequency. However, for existing GaN HEMTs, especially GaN HEMTs based on gallium nitride on silicon technology, the parasitic effects during the interconnection process as discrete devices will limit the operating frequency of the HEMTs. The prior art can further improve the operating frequency of HEMTs by realizing the monolithic integration of GaN-on-Si HEMTs. However, in a conventional GaN-on-Si epitaxial substrate platform, the monolithic integration is limited by the substrate effect, resulting in serious degradation of the device on-characteristics. At the same time, GaN HEMTs lack avalanche breakdown ability, and overvoltage generated at the drain and source electrodes is likely to break down and burn out the device, greatly limiting the reliability of GaN HEMTs. Summary of the Invention
[0003] This application aims to solve at least one of the technical problems in the related art to some extent.
[0004] To this end, the first object of this application is to propose a monolithic integrated bridge circuit structure, which can enable the switch device structure to be free from the limitation of the substrate effect, realize the electrical isolation of different switch device structures, and thus improve the on-characteristics of the switch device.
[0005] The second object of this application is to propose a monolithic integrated bridge circuit structure, which can improve the breakdown voltage characteristics of the circuit structure.
[0006] To achieve the above object, the first aspect embodiment of this application proposes a monolithic integrated bridge circuit structure, including:
[0007] A substrate, the substrate includes a substrate, a buried oxide layer formed on the substrate, and a first semiconductor layer and a second semiconductor layer formed on the buried oxide layer. At least two of the second semiconductor layers are formed in the first semiconductor layer at intervals, and a first device region and a second device region are formed on the second semiconductor layer at intervals;
[0008] A first device structure and a second device structure, the first device structure being formed on the first device region and including a first gate layer, and a first source layer and a first drain layer located on both sides of the first gate layer; the second device structure being formed on the second device region and including a second gate layer, and a second source layer and a second drain layer located on both sides of the second gate layer;
[0009] Wherein, the second drain layer is connected to a power supply, the second source layer is connected to the first drain layer and the second semiconductor layer of the second device region, and the first source layer is connected to the second semiconductor layer of the first device region and grounded.
[0010] Optionally, at least one P-type heavily doped region is formed in the second semiconductor layer, the second source layer and the first drain layer are connected to the P-type heavily doped region of the second semiconductor layer of the second device region, and the first source layer is connected to the P-type heavily doped region of the second semiconductor layer of the first device region and grounded.
[0011] Optionally, a heavily doped implantation region is further formed in the first semiconductor layer, and the heavily doped implantation region is at least formed in the first semiconductor layer between the first device region and the second device region.
[0012] Optionally, the heavily doped implantation region includes at least one of a plurality of P-type heavily doped regions and N-type heavily doped regions.
[0013] Optionally, the heavily doped implantation region includes a plurality of alternately arranged P-type heavily doped regions and N-type heavily doped regions.
[0014] Optionally, the heavily doped implantation region is formed in the first semiconductor layer on both sides of the second device region, and the second source layer and the first drain layer are further connected to an N-type heavily doped region close to the second device region of the heavily doped implantation region between the first device region and the second device region; the second drain layer is further connected to an N-type heavily doped region on the side away from the first device region of the heavily doped implantation region.
[0015] Optionally, the first device structure and the second device structure include high electron mobility transistors.
[0016] Optionally, both the first device structure and the second device structure include a buffer layer, a channel layer and a barrier layer stacked in sequence on the second semiconductor layer of the first device region and the second device region respectively.
[0017] Optionally, the structure further includes a passivation layer, the passivation layer is formed on the substrate, fills the gap between the first device structure and the second device structure, and extends to cover the exposed surface of the barrier layer.
[0018] Optionally, the substrate electrode is formed on the surface of the substrate on the side away from the first semiconductor layer and is grounded.
[0019] The monolithic integrated bridge circuit structure provided by this application has at least the following beneficial effects:
[0020] This application provides a monolithic integrated bridge circuit structure, which includes a substrate, and a first device structure and a second device structure that are located on the substrate and are spaced apart from each other. The substrate includes a first semiconductor layer and a second semiconductor layer of different conductive types. The first device structure includes a first source layer, a first drain layer, and a first gate layer that are spaced apart. The second device structure includes a second source layer, a second drain layer, and a second gate layer that are spaced apart. The second drain layer is connected to a power supply, the second source layer is connected to the first drain layer and the second semiconductor layer under the second device structure, and the first source layer is connected to the second semiconductor layer under the first device structure and is grounded. When the voltages of the second gate layer and the first gate layer are controlled to turn off the first device structure and turn on the second device structure, the PN junction formed by the second semiconductor layer and the first semiconductor layer under the first device structure is reverse-biased, and the PN junction formed by the second semiconductor layer and the first semiconductor layer under the second device structure is forward-biased, thereby realizing the on-chip integration and electrical isolation of the first device structure and the second device structure and improving the voltage withstand capacity of the circuit structure.
[0021] The additional aspects and advantages of this application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of this application. Description of the Drawings
[0022] The above-mentioned and / or additional aspects and advantages of this application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:
[0023] Figure 1 FIG. is a schematic structural diagram of a bridge circuit structure shown according to the prior art.
[0024] Figure 2 FIG. is a schematic structural diagram of a bridge circuit structure shown according to the output of this application.
[0025] Figure 3 For Figure 2 FIG. shows a schematic structural equivalent circuit diagram of a bridge circuit structure.
[0026] Figure 4 For Figure 2 FIG. shows a schematic diagram of the equivalent electric field strength of a heavily doped implantation region.
[0027] Figure 5It is a schematic structural diagram of a bridge circuit structure shown according to the present application.
[0028] Figure 6 It is according to Figure 5 A schematic diagram of an equivalent circuit structure of a bridge circuit structure shown.
[0029] Figure 7 It is according to Figure 5 A schematic diagram of an equivalent curve showing the clamping voltage of an avalanche diode shown.
[0030] 100 substrate; 110 base plate; 120 buried oxide layer; 130 first semiconductor layer; 131 heavily doped implantation region; 132 avalanche diode; 140 second semiconductor layer; 150 substrate electrode; 201 buffer layer; 202 channel layer; 203 barrier layer; 204 third electrode post; 205 fourth electrode post; 210 first device structure; 211 first source layer; 212 first P-type gallium nitride layer; 213 first gate layer; 214 first drain layer; 214 first electrode post; 220 second device structure; 221 second source layer; 222 second P-type gallium nitride layer; 223 second gate layer; 224 second drain layer; 225 second electrode post; 300 passivation layer; I first device region; II second device region. Detailed implementation manners
[0031] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described by referring to the drawings below are exemplary and are intended to explain the present application and should not be construed as a limitation to the present application.
[0032] Traditional GaN-on-Si bridge circuits are as Figure 1 shown, including an Si substrate and two switching transistors located on the substrate and spaced apart. Among them, the Si substrate is generally composed of P-type low-resistance Si. The high-frequency switching of the two switching transistors in the bridge circuit will cause the source reference potential of the high- and low-voltage side switching transistors to change, and the high-frequency changing potential will propagate electromagnetic interference along the low-resistance Si substrate, thereby causing changes in the space charge distribution in the GaN buffer layer 201. At the same time, since the conductive channel width of the GaN HEMT is extremely small, it is easily depleted due to the generation and change of space charge, and then the bridge circuit will experience current collapse and cannot conduct.
[0033] Based on the above problems, the embodiments of the present application provide a monolithic integrated bridge circuit structure, which can achieve electrical crosstalk between the high- and low-voltage side switching transistors, thereby improving the conduction performance of the bridge circuit structure.
[0034] According to one aspect of the embodiments of the present application, a monolithic integrated bridge circuit structure is provided, as Figures 2 to 5 shown, including a substrate 100, and a first device structure 210 and a second device structure 220 formed on the substrate 100.
[0035] In some embodiments, the substrate 100, as a multi-layer composite structure, may include a substrate 110 and a buried oxide layer 120 (BOX) formed on the substrate 110, and a first semiconductor layer 130 and a second semiconductor layer 140 formed on the buried oxide layer 120. At least two second semiconductor layers 140 are spaced apart from each other and formed within the first semiconductor layer 130, and then a first device region I and a second device region II spaced apart from each other are formed on the second semiconductor layer 140.
[0036] Among them, the substrate 110, the first semiconductor layer 130, and the second semiconductor layer 140 may be composed of single-crystal semiconductor materials such as single-crystalline silicon, and are in-situ doped with electroactive dopants such as N-type dopants (such as phosphorus or arsenic, etc.) or P-type dopants (such as boron or gallium, etc.) during epitaxial growth, or sputter doping with a preset depth is performed on a preset position of the single-crystalline silicon by using a magnetron sputtering injection method. The buried oxide layer 120 may be composed of a solid dielectric material layer such as silicon dioxide, and the buried oxide layer 120 is formed between the substrate 110 and the first semiconductor layer 130, and can electrically isolate the first semiconductor layer 130 from the substrate 110.
[0037] As an example, the substrate 110 is composed of P-type lightly doped single-crystalline silicon material, the first semiconductor layer 130 is composed of N-type lightly doped single-crystalline silicon material, the second semiconductor layer 140 is composed of P-type lightly doped single-crystalline silicon material, and the second semiconductor layer 140 is formed within the first semiconductor layer 130 by means of P-type dopant magnetron sputtering injection, and a PN junction is formed at the interface between the first semiconductor layer 130 and the second semiconductor layer 140.
[0038] In some embodiments, the first device structure 210, as a low-side switching device, is formed on the first device region I, and includes a first P-type gallium nitride layer 212 and a first gate layer 213 stacked, and a first source layer 211 and a first drain layer 214 formed on both sides of the first P-type gallium nitride layer 212, and the first gate layer 213 is formed on the first P-type gallium nitride layer 212.
[0039] The second device structure 220, as a high-side switching device, is formed on the second device region II, and includes a second P-type gallium nitride layer 222 and a second gate layer 223 stacked, and a second source layer 221 and a second drain layer 224 formed on both sides of the second P-type gallium nitride layer 222, and the second gate layer 223 is formed on the second P-type gallium nitride layer 222.
[0040] Thus, by separately adjusting the gate voltages connected to the first gate layer 213 and / or the second gate layer 223, the first device structure 210 and / or the second device structure 220 can be switched between the on state and the off state, thereby changing the switching states of the first device structure 210 and / or the second device structure 220.
[0041] As an example, both the first device structure 210 and the second device structure 220 are high electron mobility transistors, and both include a stack of a buffer layer 201, a channel layer 202, and a barrier layer 203 that are continuously deposited and formed on the second semiconductor layer 140 in the first device region I and the second device region II using an epitaxial growth process such as metalorganic chemical vapor deposition, vapor phase epitaxy, or molecular beam epitaxy. Among them, the buffer layer 201, the channel layer 202, and the barrier layer 203 can all be composed of semiconductor materials containing binary III-V compounds, such as gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of these materials. Setting the buffer layer 201 between the channel layer 202 and the second semiconductor layer 140 is beneficial to alleviating the lattice mismatch, thermal property difference, and mechanical property difference between the materials of the second semiconductor layer 140 and the channel layer 202. The barrier layer 203 is an electron supply layer, which is formed on the channel layer 202, and then forms a heterojunction with the channel layer 202, and generates a two-dimensional electron gas (2DEG) on the side close to the channel layer 202 through piezoelectric polarization and spontaneous polarization effects.
[0042] Furthermore, the second drain layer 224 is connected to the power supply Vin, the second source layer 221 is connected to the first drain layer 214 and the second semiconductor layer 140 in the second device region II, the first source layer 211 is connected to the second semiconductor layer 140 in the first device region I and grounded, and the substrate electrode 150 is disposed on the side of the substrate 110 away from the first semiconductor layer 130 and grounded.
[0043] Thus, when the first device structure 210 remains off and the second device structure 220 remains on, since the second source layer 221, the first drain layer 214, and the second semiconductor layer 140 in the second device region II are connected, both the first drain layer 214 and the second semiconductor layer 140 located under the second device region II are at a high potential, equivalent to the power supply Vin. As a result, the PN junction between the second semiconductor layer 140 located under the second device region II and the first semiconductor layer 130 is forward-biased and turned on, and the potential of the first semiconductor layer 130 is basically the same as the potentials of the second source layer 221 and the first drain layer 214.
[0044] Meanwhile, since the first source layer 211 is connected to the second semiconductor layer 140 in the first device region I and grounded, the second semiconductor layer 140 located under the first device region I is at a low potential, while the first semiconductor layer 130 is at a high potential. As a result, the PN junction between the second semiconductor layer 140 and the first semiconductor layer 130 under the first device region I is reversely biased and turned off, thereby isolating the influence brought by the conduction of the second device structure 220. In addition, the PN junction between the second semiconductor layer 140 and the first semiconductor layer 130 under the first device region I can provide an avalanche breakdown function for the half-bridge circuit, thereby improving the voltage withstand capacity of the circuit structure.
[0045] It should be noted that the first device structure 210 and the second device structure 220 in the above embodiments are both GaN HEMTs. In other embodiments of the present application, the first device structure 210 and the second device structure 220 can also be other non-GaN-based HEMTs, and other non-GaN-based HEMTs can include, but are not limited to, any one of compound semiconductor transistors such as GaAs HEMT and InP HEMT based on heterojunction structures such as GaAs / AlGaAs and InP / InGaAs.
[0046] In some embodiments, the first device structure 210 includes a first electrode post 214, and the first electrode post 214 penetrates through the buffer layer 201, the channel layer 202, and the barrier layer 203 stack of the first device structure 210 and is connected to the second semiconductor layer 140 located under the first device region I. The second device structure 220 includes a second electrode post 225, and the second electrode post 225 penetrates through the buffer layer 201, the channel layer 202, and the barrier layer 203 stack of the second device structure 220 and is connected to the second semiconductor layer 140 located under the second device region II.
[0047] As an example, in order to further improve the electrical connection characteristics between the first electrode post 214 and the second electrode post 225 and the corresponding second semiconductor layer 140, at least one P-type heavily doped region is further formed in each second semiconductor layer 140, and the doping concentration of the P-type dopant in the P-type heavily doped region is much greater than the doping concentration of the P-type dopant in the second semiconductor layer 140, so as to reduce the contact resistance between the first electrode post 214 and the second electrode post 225 and the P-type heavily doped region.
[0048] As an example, as Figure 2 and 4 shown, a heavily doped implantation region 131 is also formed in the first semiconductor layer 130, and the heavily doped implantation region 131 is formed at least in the first semiconductor layer 130 between two adjacent second semiconductor layers 140 to balance the internal electric field of the first semiconductor layer 130 and improve the conduction stability of the first switching device 210 and the second switching device 220.
[0049] Among them, the heavily doped implantation region 131 includes at least one of a plurality of P-type heavily doped regions and N-type heavily doped regions, and the plurality of P-type heavily doped regions and N-type heavily doped regions are arranged at intervals within the heavily doped implantation region 131. That is to say, in this application, the number and doping type of the heavily doped regions in the heavily doped implantation region 131 are not specifically limited. It can be a plurality of N-type heavily doped regions, or a plurality of P-type heavily doped regions, or a combination of a plurality of alternately arranged N-type heavily doped regions and P-type heavily doped regions.
[0050] As Figure 5 and Figure 6 shown, the heavily doped implantation region 131 is formed in the first semiconductor layer 130 on both sides of the second device region II. Each heavily doped implantation region 131 is composed of a plurality of alternately arranged N-type heavily doped regions and P-type heavily doped regions, and the plurality of alternately arranged N-type heavily doped regions and P-type heavily doped regions (in the order of P-N-P-N-) are connected to form an avalanche diode 132 together.
[0051] Furthermore, the second source layer 221 and the first drain layer 214 are also connected to the end N-type heavily doped region of the avalanche diode 132 between the first device region I and the second device region II through the third electrode post 204; the second drain layer 224 is also connected to the end N-type heavily doped region of the avalanche diode 132 far from the first device region I through the fourth electrode post 205, so that when the third electrode post 204 and / or the fourth electrode post 205 is in an overvoltage state, the PN junction in the corresponding avalanche diode 132 can be in a reverse bias state, thereby clamping the transient spike voltage input to the first device structure 210 and / or the second device structure 220 within a certain threshold range, as Figure 7 shown, thereby improving the breakdown voltage of the circuit structure.
[0052] It should be noted that in this application, the specific number of the alternately arranged N-type heavily doped regions and P-type heavily doped regions in the avalanche diode 132 region is not specifically limited. Those skilled in the art can control the number of alternately arranged N-type heavily doped regions and P-type heavily doped regions to control the input voltage clamping threshold range of the first device structure 210 and the second device structure 220, thereby improving the breakdown resistance performance of the circuit structure.
[0053] In some embodiments, the circuit structure further includes a passivation layer 300 formed on the substrate 100, which fills the gap between the first device structure 210 and the second device structure 220 and extends to cover the exposed surface of the barrier layer 203, so as to passivate and protect the exposed surfaces of the first device structure 210, the second device structure 220 and the substrate 100, and laterally isolate the first device structure 210 and the second device structure 220. The material of the passivation layer 300 includes any one of materials with surface passivation functions such as silicon nitride, silicon oxide, and aluminum oxide.
[0054] In summary, the present application provides a monolithic integrated bridge circuit structure, which includes a substrate 100, and a first device structure 210 and a second device structure 220 that are located on the substrate 100 and are spaced apart from each other. The substrate 100 includes a first semiconductor layer 130 and a second semiconductor layer 140 of different conductive types. The first device structure 210 includes a first source layer 211, a first drain layer 214, and a first gate layer 213 that are spaced apart. The second device structure 220 includes a second source layer 221, a second drain layer 224, and a second gate layer 223 that are spaced apart. The second drain layer 224 is connected to a power supply, the second source layer 221 is connected to the first drain layer 214 and the second semiconductor layer 140 under the second device structure 220, and the first source layer 211 is connected to the second semiconductor layer 140 under the first device structure 210 and grounded. When the voltages of the second gate layer 223 and the first gate layer 213 are controlled to turn off the first device structure 210 and turn on the second device structure 220, the PN junction formed by the second semiconductor layer 140 and the first semiconductor layer 130 under the first device structure 210 is reverse-biased, and the PN junction formed by the second semiconductor layer 140 and the first semiconductor layer 130 under the second device structure 220 is forward-biased, which not only realizes the on-chip integration and electrical isolation of the first device structure 210 and the second device structure 220, but also improves the voltage withstand capacity of the circuit structure.
[0055] In the description of the foregoing embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.
Claims
1. A monolithic integrated bridge circuit structure, characterized in that: include: A substrate, the substrate comprising a base plate, a buried oxide layer formed on the base plate, and a first semiconductor layer and a second semiconductor layer formed on the buried oxide layer, at least two of the second semiconductor layers are formed in the first semiconductor layer at intervals, and a first device region and a second device region are formed on the second semiconductor layer at intervals; A first device structure and a second device structure, wherein the first device structure is formed on the first device region and includes a first gate layer, and a first source layer and a first drain layer located on both sides of the first gate layer; and the second device structure is formed on the second device region and includes a second gate layer, and a second source layer and a second drain layer located on both sides of the second gate layer; The second drain layer is connected to a power source, the second source layer is connected to the first drain layer and the second semiconductor layer in the second device region, and the first source layer is connected to the second semiconductor layer in the first device region and is grounded.
2. The structure according to claim 1, characterized in that: At least one P-type heavily doped region is formed in the second semiconductor layer, the second source layer and the first drain layer are connected to the P-type heavily doped region of the second semiconductor layer in the second device region, and the first source layer is connected to the P-type heavily doped region of the second semiconductor layer in the first device region and is grounded.
3. The structure according to claim 2, characterized in that: A heavily doped implantation region is also formed in the first semiconductor layer. The heavily doped implantation region is at least formed in the first semiconductor layer between the first device region and the second device region.
4. The structure according to claim 3, characterized in that The heavily doped implantation region includes at least one of a plurality of P-type heavily doped regions and N-type heavily doped regions.
5. The structure according to claim 4, characterized in that: The heavily doped injection region includes an avalanche diode composed of a plurality of P-type heavily doped regions and N-type heavily doped regions alternately arranged in sequence.
6. The structure according to claim 5, characterized in that The heavily doped injection region is formed in the first semiconductor layer on both sides of the second device region, and the second source layer and the first drain layer are also connected to an N-type heavily doped region of the heavily doped injection region between the first device region and the second device region, which is close to the second device region; the second drain layer is also connected to an N-type heavily doped region of the heavily doped injection region on the side away from the first device region.
7. The structure according to claim 1, characterized in that The first device structure and the second device structure include high electron mobility transistors.
8. The structure according to claim 1, characterized in that The first device structure and the second device structure each include a buffer layer, a channel layer, and a barrier layer sequentially stacked on the second semiconductor layer in the first device region and the second device region, respectively.
9. The structure according to claim 8, characterized in that The structure further includes a passivation layer, which is formed on the substrate, fills the gap between the first device structure and the second device structure, and extends to cover the exposed surface of the barrier layer.
10. The structure according to claim 1, characterized in that The substrate electrode is formed on a surface of the substrate away from the first semiconductor layer and is grounded.