Integrated passive component and method for manufacturing integrated passive component

Abstract

The invention relates to an integrated passive component and a method for manufacturing the integrated passive component. The integrated passive component has an upper surface and a lower surface facing opposite directions to each other. The integrated passive component includes: an insulating film having a first surface facing in the same direction as the upper surface and a second surface facing in the same direction as the lower surface; a capacitor disposed in the insulating film; and a multilayer wiring structure disposed on the first surface of the insulating film. The multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers alternately stacked, each of the plurality of wiring layers including a plurality of wirings, at least a portion of the plurality of wirings constituting an inductor. The insulating film includes an inorganic material layer composed of an inorganic insulating material, and a thickness of the inorganic material layer is thinner than a sum of thicknesses of each of the plurality of resin layers of the multilayer wiring structure. The second surface of the insulating film constitutes the lower surface of the integrated passive component.

Description

Technical Field

[0001] The present invention relates to an integrated passive component and a method for manufacturing the integrated passive component. Background Art

[0002] There is known an integrated passive component in which a smoothing layer is disposed on a substrate, and a capacitor and an inductor are disposed on the smoothing layer (Patent Document 1). The inductor is composed of a plurality of wirings having a multilayer wiring structure in which a plurality of resin layers and a plurality of wirings are alternately laminated. As the substrate, for example, single crystal silicon, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO 3 single crystal, silicon oxide on the surface, glass, quartz, ferrite, etc. are used.

[0003] Patent Document 1: International Publication No. 2021 / 193132

[0004] In an integrated passive component, in order to improve electrical characteristics, thickening and multilayerization of the wirings and resin layers constituting the inductor are required. If the wirings and resin layers become thick, cracks are likely to occur in the resin layer due to thermal stress caused by the difference in the linear expansion coefficients between the resin layer and the substrate. In addition, peeling is likely to occur at the interface between the resin layer and the smoothing layer. If cracks and peeling occur, the moisture resistance is reduced. In order not to cause cracks and peeling, the thickness and the number of stacked layers of the resin layer are restricted, and thus the improvement of the electrical characteristics of the integrated passive component is restricted. Summary of the Invention

[0005] An object of the present invention is to provide an integrated passive component and a method for manufacturing the same, which are less likely to cause cracks and peeling due to thermal stress.

[0006] According to one aspect of the present invention, there is provided an integrated passive component having an upper surface and a lower surface facing in opposite directions, wherein,

[0007] The above integrated passive component includes:

[0008] An insulating film having a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface;

[0009] A capacitor disposed in the insulating film; and

[0010] A multilayer wiring structure disposed on the first surface of the insulating film,

[0011] The multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers alternately laminated, each of the plurality of wiring layers includes a plurality of wirings, and at least a part of the plurality of wirings constitutes an inductor,

[0012] The above-mentioned insulating film includes an inorganic material layer made of an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the thicknesses of each of the resin layers in the above-mentioned multilayer wiring structure.

[0013] The second surface of the above-mentioned insulating film constitutes the lower surface.

[0014] According to another aspect of the present invention, there is provided an integrated passive component having an upper surface and a lower surface facing in opposite directions.

[0015] The above-mentioned integrated passive component includes:

[0016] An insulating film having a first surface facing the same direction as the above-mentioned upper surface and a second surface facing the same direction as the above-mentioned lower surface;

[0017] A capacitor disposed within the above-mentioned insulating film;

[0018] A multilayer wiring structure disposed on the first surface of the above-mentioned insulating film; and

[0019] A support member adhered to the second surface of the above-mentioned insulating film and made of an insulating resin.

[0020] The above-mentioned multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers laminated alternately, and each wiring layer in the above-mentioned plurality of wiring layers includes a plurality of wirings, and at least a part of the above-mentioned plurality of wirings constitutes an inductor.

[0021] The above-mentioned insulating film includes an inorganic material layer made of an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the thicknesses of each of the resin layers in the above-mentioned multilayer wiring structure.

[0022] According to still another aspect of the present invention, there is provided a method for manufacturing an integrated passive component, wherein

[0023] A lower insulating film is formed on one surface of a temporary substrate made of a semiconductor.

[0024] A capacitor is formed on a part of the area of the above-mentioned lower insulating film.

[0025] An upper insulating film is formed on the above-mentioned lower insulating film so as to cover the above-mentioned capacitor.

[0026] A multilayer wiring structure in which a plurality of resin layers and a plurality of wirings constituting an inductor are laminated alternately is formed on the above-mentioned upper insulating film.

[0027] The above-mentioned temporary substrate is removed to expose the above-mentioned lower insulating film.

[0028] The thickness of the inorganic material layer is thinner than the sum of the thicknesses of each of the resin layers in the multilayer wiring structure, so the generation of thermal stress can be suppressed. In addition, since the support member is made of resin, the difference in the coefficient of linear expansion between the support member and each of the resin layers in the multilayer wiring structure is small. Therefore, the generation of thermal stress can be suppressed. As a result, the generation of cracks and peeling caused by thermal stress can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A FIG. is a plan view showing the shapes and positional relationships of the respective components of the integrated passive component according to the first embodiment. Figure 1B FIG. is an equivalent circuit diagram of the integrated passive component according to the first embodiment.

[0030] Figure 2 is Figure 1A a cross-sectional view taken along the single-dot chain line 2-2 of

[0031] Figures 3A to 3C The respective drawings are cross-sectional views of the integrated passive component according to the first embodiment in an intermediate stage of manufacturing.

[0032] Figures 4A to 4C The respective drawings are cross-sectional views of the integrated passive component according to the first embodiment in an intermediate stage of manufacturing.

[0033] Figure 5A and Figure 5B is a cross-sectional view of the integrated passive component according to the first embodiment in an intermediate stage of manufacturing.

[0034] Figure 6A and Figure 6B is a cross-sectional view of the integrated passive component according to the first embodiment in an intermediate stage of manufacturing.

[0035] Figure 7 is a cross-sectional view of the integrated passive component according to the first embodiment in an intermediate stage of manufacturing.

[0036] Figure 8 is a cross-sectional view of the integrated passive component according to the second embodiment.

[0037] Figure 9 is a cross-sectional view of the integrated passive component according to the third embodiment.

[0038] Figure 10A FIG. is a plan view showing the shapes and positional relationships of the respective components of the integrated passive component according to the fourth embodiment. Figure 10B is an equivalent circuit diagram of the integrated passive component according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0039] [First Embodiment]

[0040] Reference Figures 1A to 7 The integrated passive component of the first embodiment and its manufacturing method will be described with reference to the accompanying drawings.

[0041] Figure 1A is a diagram showing the shape and positional relationship of each of the components of the integrated passive component 10 of the first embodiment when viewed from above, Figure 1B is an equivalent circuit diagram of the integrated passive component 10 of the first embodiment. The integrated passive component 10 of the first embodiment includes a capacitor 20, an inductor 40, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY provided on a common insulating film.

[0042] As Figure 1B shown, an inductor 40 is connected between the input terminal In and the output terminal Out, and a capacitor 20 is connected between the input terminal In and the ground terminal GND. The integrated passive component 10 of the first embodiment functions as a low-pass filter.

[0043] As Figure 1A shown, the integrated passive component 10 of the first embodiment includes three wiring layers, i.e., a first layer to a third layer. A plurality of external connection terminals such as an input terminal In, an output terminal Out, and a ground terminal GND are arranged on the wiring layer of the third layer. In Figure 1A it, relatively thick right-upper diagonal hatching is added to each wiring of the wiring layer of the first layer, and relatively light right-lower diagonal hatching is added to each wiring of the wiring layer of the second layer. The outline of the external connection terminals is represented by the thickest solid line, and the outline of each wiring of the wiring layer of the third layer is represented by the second thickest solid line.

[0044] The wiring of the first layer constituting the inductor 40 is wound approximately once along the outer peripheral line of a square. The wiring of the second layer has a spiral shape with approximately two turns, and the wiring of the third layer has a spiral shape with approximately 1 + 3 / 4 turns. The wirings of the first layer to the third layer are connected in series to form an inductor 40 with approximately 4 + 3 / 4 turns. One end of the wiring of the first layer is connected to the input terminal In via the wirings of the second layer and the third layer, and an output terminal Out is connected to one end of the wiring of the third layer.

[0045] And, one electrode of the capacitor 20 is connected to one end of the wiring of the first layer. The other electrode of the capacitor 20 is connected to the ground terminal GND via the wirings of the first layer to the third layer.

[0046] Figure 2 is Figure 1A a cross-sectional view taken along the single-dot chain line 2 - 2 of

[0047] The integrated passive component 10 of the first embodiment has an upper surface 10U and a lower surface 10L facing in opposite directions. The integrated passive component 10 includes an insulating film 11 and a multilayer wiring structure 30. The insulating film 11 has a first surface 11U facing the same direction as the upper surface 10U of the integrated passive component 10 and a second surface 11L facing the same direction as the lower surface 10L. The multilayer wiring structure 30 is disposed on the first surface 11U of the insulating film 11. The lower surface 10L of the integrated passive component 10 and the second surface 11L of the insulating film 11 are the same surface, and the lower surface 10L of the integrated passive component 10 is formed by the second surface 11L of the insulating film 11.

[0048] A capacitor 20 is disposed in the insulating film 11. Next, the structures of the insulating film 11 and the capacitor 20 will be described. The insulating film 11 includes a lower insulating film 11A having a second surface 11L and an upper insulating film 11B disposed thereon and having a first surface 11U. The capacitor 20 is disposed between the lower insulating film 11A and the upper insulating film 11B. For example, the capacitor 20 is disposed in a partial region of the upper surface of the lower insulating film 11A, and the upper insulating film 11B covers the capacitor 20. The lower insulating film 11A and the upper insulating film 11B are each formed of an inorganic insulating material, such as silicon oxide, silicon nitride, or the like.

[0049] The capacitor 20 includes a lower electrode layer 20L, a capacitor dielectric film 20D, and an upper electrode layer 20U laminated in this order on the lower insulating film 11A. An opening is provided in a part of the capacitor dielectric film 20D, and a contact electrode 20C disposed on the capacitor dielectric film 20D is connected to the lower electrode layer 20L through the opening. In addition, an opening may not be provided in the capacitor dielectric film 20D. In this case, two conductor patterns disposed on the capacitor dielectric film 20D constitute a pair of electrodes of the capacitor 20.

[0050] The multilayer wiring structure 30 includes a plurality of resin layers and a plurality of wiring layers laminated alternately. The integrated passive component 10 of the first embodiment includes three resin layers 31, 32, 33 and three wiring layers. A plurality of wirings 35 are disposed in the wiring layer of the first layer, a plurality of wirings 36 are disposed in the wiring layer of the second layer, and a plurality of wirings 37 are disposed in the wiring layer of the third layer. In addition, a multilayer structure of two layers or four or more layers may be provided as needed.

[0051] Two resin layers 31 and 32 are respectively present between two adjacent upper and lower wirings among the wirings 35, 36, and 37 of multiple wiring layers, and in a region where the wiring 36 is not disposed, the resin layer 31 and the resin layer 32 are in contact. The resin layer 33 is present between the wiring 37 of the uppermost wiring layer and the external connection terminal 38, and in a region where the wiring 37 is not disposed, the resin layer 32 and the resin layer 33 are in contact. In a region where two adjacent upper and lower resin layers are in contact with each other, sometimes the interface between the two cannot be clearly observed. The multilayer wiring structure 30 may also include at least one of a resin layer disposed between the wiring 35 of the lowermost wiring layer and the insulating film 11 forming its base, and a resin layer covering the surface of the external connection terminal 38 and the resin layer 33 forming its base.

[0052] A plurality of external connection terminals 38 are disposed on the uppermost resin layer 33. Solder 39 is mounted on the external connection terminal 38. The external connection terminal 38 is connected to the lower-layer wiring 37 through a via hole provided in the resin layer 33. A part of the multiple wirings of the multilayer wiring structure 30 constitutes an inductor 40. The wirings 35, 36, and 37 constituting the inductor 40 are disposed across three wiring layers of the first layer to the third layer.

[0053] One of the wirings 35 in the first layer is connected to the upper electrode layer 20U of the capacitor 20 through an opening provided in the upper insulating film 11B, and the other of the wirings 35 in the first layer is connected to the contact electrode 20C through an opening provided in the upper insulating film 11B and is connected to the lower electrode layer 20L of the capacitor 20 via the contact electrode 20C.

[0054] An input terminal In, which is one of the multiple external connection terminals 38, is connected to the lower electrode layer 20L of the capacitor 20 via the wirings 37, 36, 35 of each wiring layer and the contact electrode 20C. In addition, although not shown in the cross-sectional view Figure 2 shown, as Figure 1A shown, external connection terminals such as an output terminal Out, a ground terminal GND, and a dummy terminal DMY are disposed on the resin layer 33.

[0055] Next, a manufacturing method of the integrated passive component 10 of the first embodiment will be described with reference to Figures 3A to 7 the accompanying drawings. Figures 3A to 7 The respective drawings of

[0056] are cross-sectional views of the intermediate stage of manufacturing the integrated passive component 10 of the first embodiment. Figure 3AAs shown, a lower insulating film 11A is formed on one surface (hereinafter sometimes referred to as the upper surface) of a temporary substrate 55 made of semiconductor. As the temporary substrate 55, for example, a silicon substrate is used. The lower insulating film 11A is formed of an inorganic insulating material. For example, the lower insulating film 11A uses a material containing silicon and oxygen as constituent elements (e.g., silicon oxide), or a material containing silicon and nitrogen as constituent elements (e.g., silicon nitride). The lower insulating film 11A is formed, for example, by sputtering, plasma chemical vapor deposition (plasma CVD), metalorganic chemical vapor deposition (MOCVD), etc. In addition, impurities may also be contained in the silicon oxide or silicon nitride constituting the lower insulating film 11A.

[0057] As Figure 3B shown, a photoresist film 60 is formed on the lower insulating film 11A, and an opening 60H is formed in a region where the lower electrode layer 20L ( Figure 2 ) of the capacitor 20 is formed. A conductor film 61 is formed on the lower insulating film 11A and the photoresist film 60 exposed at the bottom surface of the opening. The conductor film 61 uses, for example, Cu or an alloy mainly composed of Cu, and the conductor film 61 is formed, for example, by vacuum evaporation.

[0058] As Figure 3C shown, the photoresist film 60 and the conductor film 61 deposited thereon ( Figure 3B ) are removed. As a result, the lower electrode layer 20L of the capacitor 20 remains on the lower insulating film 11A.

[0059] As Figure 4A shown, a dielectric film 62 is formed so as to cover the exposed surfaces of the lower electrode layer 20L and the lower insulating film 11A. The dielectric film 62 uses, for example, a dielectric material such as silicon oxide or silicon nitride. The dielectric film 62 is formed, for example, by sputtering, plasma CVD, MOCVD, etc.

[0060] As Figure 4B shown, when looking down on the upper surface of the temporary substrate 55 (hereinafter sometimes simply referred to as "looking down"), an opening 20H penetrating the dielectric film 62 is formed at a portion overlapping with a part of the lower insulating film 11A. At this time, unnecessary portions (portions deposited on the lower insulating film 11A) of the dielectric film 62 ( Figure 4A ) may also be removed. A capacitor dielectric film 20D formed of a part of the dielectric film 62 ( Figure 4A ) remains on the lower electrode layer 20L.

[0061] As Figure 4CAs shown, an upper electrode layer 20U and a contact electrode 20C are formed on a capacitor dielectric film 20D. The contact electrode 20C is connected to a lower electrode layer 20L through an opening 20H provided in the capacitor dielectric film 20D. The forming methods of the upper electrode layer 20U and the contact electrode 20C are the same as those of the lower electrode layer 20L.

[0062] An upper insulating film 11B is formed on the lower insulating film 11A so as to cover the upper electrode layer 20U and the contact electrode 20C. The upper insulating film 11B uses an inorganic insulating material, such as silicon oxide, silicon nitride, etc., and is formed by the same method as the lower insulating film 11A. In addition, impurities may also be contained in the silicon oxide or silicon nitride constituting the upper insulating film 11B. An opening 11H is formed in the upper insulating film 11B to expose respective parts of the upper electrode layer 20U and the contact electrode 20C.

[0063] As Figure 5A shown, a metal film 63 is formed so as to cover the upper insulating film 11B. The metal film 63 also covers the bottom surface and the side surface of the opening 11H provided in the upper insulating film 11B. The metal film 63 is composed of two layers, a Ti layer and a Cu layer disposed thereon. The metal film 63 is formed, for example, by sputtering.

[0064] A photoresist film 64 is formed on the metal film 63, and an opening 64H is formed in a region where the first-layer wiring 35 is to be formed. Using the metal film 63 as a seed layer, Cu is deposited by electroplating. Thus, the first-layer wiring 35 is formed within the opening 64H.

[0065] As Figure 5B shown, the photoresist film 64 ( Figure 5A ) is removed. Thus, a part of the metal film 63 ( Figure 5A ) is exposed. The exposed metal film 63 is removed by wet etching. The metal film 63 used as a seed layer remains between the first-layer wiring 35 and the upper insulating film 11B. Such a forming method of the wiring 35 is called a semi-additive method.

[0066] As Figure 6A shown, a first-layer resin layer 31 is formed on the first-layer wiring 35 and the upper insulating film 11B. The resin layer 31 can be formed by bonding a semi-cured resin film mixed with a photosensitive material using a vacuum lamination method. The resin film uses, for example, an epoxy resin film or a polyimide resin film. Although there are irregularities on the base surface of the resin layer 31, the upper surface of the resin layer 31 is substantially planarized.

[0067] After exposing a specified area of the resin layer 31 to light and developing, a plurality of vias are formed. For example, a part of a wiring 35 that is connected to the lower electrode layer 20L of the capacitor 20 via the contact electrode 20C is exposed by one via 31H. After forming the vias, the resin layer 31 in a semi-cured state is cured by performing heat treatment.

[0068] As Figure 6B shown, a wiring 36 of the second layer is formed on the resin layer 31 of the first layer. The formation of the wiring 36 of the second layer can use the same semi-additive method as the formation of the wiring 35 of the first layer.

[0069] As Figure 7 shown, a resin layer 32 of the second layer, a wiring 37 of the third layer, a resin layer 33 of the third layer, and an external connection terminal 38 are formed. The formation of the resin layers 32 and 33 can use a vacuum lamination method, and the formation of the wiring 37 and the external connection terminal 38 can use a semi-additive method. Solder 39 is placed on the upper surface of the external connection terminal 38.

[0070] Then, while protecting the upper surface of the resin layer 33 of the third layer and the external connection terminal 38 with a tape or the like, the temporary substrate 55 is removed. In Figure 7 , the removed temporary substrate 55 is indicated by a dashed line. After removing the temporary substrate 55, the integrated passive component 10 is singulated, and the protective tape is peeled off, thereby completing Figure 2 the integrated passive component 10 shown. The removal of the temporary substrate 55 can use wet etching based on tetramethylammonium hydroxide (TMAH) or the like. In addition, a part of the temporary substrate 55 may be ground or polished, and then the remaining part may be wet-etched. For example, when the thickness of the temporary substrate 55 is 700 μm, first, a 500-μm-thick portion may be ground or polished, and the remaining 200-μm-thick portion may be wet-etched.

[0071] Next, the excellent effects of the first embodiment will be described.

[0072] In a structure where the temporary substrate 55 ( Figure 7 ) is not removed, thermal stress is generated due to the difference in the linear expansion coefficients of the resin layers 31, 32, and 33 and the temporary substrate 55. For example, the linear expansion coefficients of resins such as polyimide and epoxy are about 20 ppm / °C or more and 65 ppm / °C or less. In contrast, the linear expansion coefficient of the single-crystalline silicon used for the temporary substrate 55 is about 3 ppm / °C. Due to the thermal stress, cracks are likely to occur in the resin layers 31, 32, and 33, and peeling is likely to occur at the interface between the insulating film 11 and the resin layer 31. If cracks and peeling occur, the moisture resistance decreases, and the quality of the integrated passive component 10 deteriorates.

[0073] In particular, if the wiring 35, 36, 37 and the resin layers 31, 32, 33 are thickened to improve the electrical characteristics of the integrated passive component 10 and the number of layers of the multilayer wiring structure 30 is increased, cracks and peeling are likely to occur. In the first embodiment, the temporary substrate 55 is removed, so thermal stress is not easily generated. As a result, cracks and peeling are not easily generated, and a decrease in the quality of the integrated passive component 10 can be suppressed.

[0074] In particular, if the thicknesses of the resin layers 31, 32, 33 and the wiring 35, 36, 37 of the multilayer wiring structure 30 are thickened, a remarkable effect of the structure in which the temporary substrate 55 is removed can be obtained. For example, when the respective thicknesses of the resin layers 31, 32, 33 are 10 μm or more and the thicknesses of the wiring 35, 36, 37 are 5 μm or more, a remarkable effect can be obtained. Further, in order to improve the electrical characteristics of the integrated passive component 10, it is more preferable that the respective thicknesses of the resin layers 31, 32, 33 are 20 μm or more and the thicknesses of the wiring 35, 36, 37 are 10 μm or more. In addition, even if the resin layers 31, 32, 33 and the wiring 35, 36, 37 are thickened more than necessary, hardly any further improvement in electrical characteristics can be seen, and instead, manufacturing difficulties increase. Therefore, it is preferable that the respective thicknesses of the resin layers 31, 32, 33 are 30 μm or less, and it is preferable that the respective thicknesses of the wiring 35, 36, 37 are 15 μm or less.

[0075] If the lower insulating film 11A and the upper insulating film 11B made of an inorganic insulating material are thickened, the thermal stress caused by the difference in the coefficient of linear expansion between the insulating film 11 and the resin layers 31, 32, 33 is significant. In order to make the influence of the thermal stress caused by the difference in the coefficient of linear expansion between the insulating film 11 and the resin layers 31, 32, 33 insignificant, it is preferable that the thickness of the inorganic material layer included in the insulating film 11, that is, the total thickness of the lower insulating film 11A and the upper insulating film 11B, is thinner than the sum of the thicknesses of each of the plurality of resin layers 31, 32, 33 of the multilayer wiring structure 30, and more preferably it is 1 / 2 or less of the sum of the thicknesses of each of the plurality of resin layers 31, 32, 33 of the multilayer wiring structure 30.

[0076] If silicon nitride is used as the lower insulating film 11A, an improvement in the moisture resistance of the integrated passive component 10 can be achieved. Further, if silicon oxide is used as the upper insulating film 11B, in the process of forming the opening 11H( Figure 4C ) in the upper insulating film 11B, a general semiconductor microfabrication process can be applied.

[0077] If the capacitor 20 is made too thick, the processing accuracy of the lower electrode layer 20L, the capacitor dielectric film 20D, and the upper electrode layer 20U decreases, and the accuracy of the capacitance decreases. In order to suppress the decrease in the accuracy of the capacitance of the capacitor 20, it is preferable that the total thickness of the lower electrode layer 20L, the capacitor dielectric film 20D, and the upper electrode layer 20U be 2 μm or less. In order to suppress the decrease in the accuracy of the capacitance of the capacitor 20 and suppress the degradation of the characteristics of the inductor 40, it is preferable that the minimum value of the thickness of each of the plurality of wirings 35, 36, 37 constituting the inductor 40 be greater than the thickness of the thicker one of the lower electrode layer 20L and the upper electrode layer 20U of the capacitor 20, and more preferably 5 times or more. By thickening the plurality of wirings 35, 36, 37 constituting the inductor 40, the resistance of the wiring can be reduced.

[0078] In addition, if the number of layers of the multilayer wiring structure 30 increases, a remarkable effect of adopting a structure in which the temporary substrate 55 is removed can be obtained. In particular, when the number of layers of the multilayer wiring structure 30 is three or more, a remarkable effect can be obtained. In a structure in which the number of layers of the multilayer wiring structure 30 is three or more, the plurality of wirings 35, 36, 37 constituting the inductor 40 are arranged over three or more wiring layers, thereby enabling improvement of the electrical characteristics of the inductor. Also, compared with a structure in which the plurality of wirings 35, 36, 37 constituting the inductor 40 are arranged over two or less wiring layers, the design inductance value per unit area can be increased.

[0079] If the distance in the stacking direction between two adjacent wirings 35, 36 and wirings 36, 37 in the multilayer wiring structure 30 becomes short, the characteristics of the inductor 40 deteriorate due to the influence of the parasitic capacitance between the wirings. In order to suppress the degradation of the characteristics of the inductor 40, it is preferable that the minimum value of the distance in the stacking direction between adjacent wirings in the multilayer wiring structure 30 (that is, the distance in the stacking direction between the wiring 35 and the wiring 36, the distance in the stacking direction between the wiring 36 and the wiring 37) be greater than or equal to the maximum value of the thickness of each of the plurality of wirings 35, 36, 37 constituting the inductor 40.

[0080] In addition, it may be configured such that in a part of the adjacent wirings in the multilayer wiring structure 30 in the stacking direction, the distance in the stacking direction is greater than or equal to the maximum value of the thickness of each of the plurality of wirings 35, 36, 37 constituting the inductor 40. In this case, the degradation of the characteristics of the inductor 40 caused by the influence of the parasitic capacitance between the wirings can be suppressed to some extent.

[0081] [Second Embodiment]

[0082] Next, refer to Figure 8The integrated passive components of the second embodiment will be described. Hereinafter, the description of the same structure as that of the integrated passive components of the first embodiment described with reference to Figures 1A to 7 is omitted.

[0083] Figure 8 is a cross-sectional view of the integrated passive component 10 of the second embodiment. In the first embodiment ( Figure 2 ), the upper insulating film 11B is formed of an inorganic insulating material. In contrast, in the second embodiment, the upper insulating film 11B is formed of an organic insulating material, for example, an insulating resin material containing epoxy, polyimide, etc. as main components. In addition, impurities may be contained in the resin constituting the upper insulating film 11B. The upper insulating film 11B made of an organic insulating material can be formed, for example, by a coating method. In this case, the upper surface of the upper insulating film 11B becomes substantially flat.

[0084] Next, the excellent effects of the second embodiment will be described. Also in the second embodiment, similar to the first embodiment, generation of cracks and peeling caused by thermal stress can be suppressed, and reduction of electrical characteristics can be suppressed.

[0085] Moreover, in the second embodiment, since the upper insulating film 11B is formed of an organic insulating material, it is easier to make the upper insulating film 11B thicker than in the first embodiment. If the upper insulating film 11B becomes thicker, the distance in the stacking direction between the capacitor 20 and the inductor 40 becomes longer. As a result, excellent effects such as good electrical separation between passive components and reduction of eddy current loss of the inductor 40 can be obtained.

[0086] In the first embodiment ( Figure 2 ), the thickness of the inorganic material layer of the insulating film 11 is equal to the sum of the thicknesses of the lower insulating film 11A and the upper insulating film 11B. In the first embodiment, it is preferable that the thickness of this inorganic material layer, that is, the sum of the thicknesses of the lower insulating film 11A and the upper insulating film 11B, is thinner than the sum of the thicknesses of each resin layer among the plurality of resin layers 31, 32, 33 of the multilayer wiring structure 30.

[0087] In contrast, in the second embodiment, the thickness of the inorganic material layer of the insulating film 11 is equal to the thickness of the lower insulating film 11A. Since the upper insulating film 11B is formed of an organic insulating material, the coefficient of linear expansion of the upper insulating film 11B is close to the coefficient of linear expansion of each resin layer among the resin layers 31, 32, 33. In order to reduce the influence of thermal stress, it is preferable that the thickness of the lower insulating film 11A as the inorganic material layer is thinner than the sum of the thicknesses of each resin layer among the plurality of resin layers 31, 32, 33 of the multilayer wiring structure 30.

[0088] [Third Embodiment]

[0089] Next, with reference to Figure 9 the integrated passive component of the third embodiment will be described. Hereinafter, the description of the structure identical to that of the integrated passive component of the first embodiment described with reference to Figures 1A to 7 the accompanying drawings will be omitted.

[0090] Figure 9 is a cross-sectional view of the integrated passive component 10 of the third embodiment. In the first embodiment ( Figure 2 ), the lower surface 10L of the integrated passive component 10 is constituted by the second surface 11L of the insulating film 11. In contrast, in the third embodiment, a support member 50 made of an insulating material is bonded to the second surface 11L of the insulating film 11, and the lower surface 10L of the integrated passive component 10 is constituted by the surface of the support member 50 opposite to the surface bonded to the insulating film 11.

[0091] As the support member 50, an insulating resin film is used. The support member 50 is bonded to the second surface 11L of the insulating film 11, for example, by the adhesiveness of the resin. In addition, the support member 50 may be bonded to the second surface 11L of the insulating film 11 using an adhesive. The difference in the coefficient of linear expansion between the support member 50 and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30 is smaller than the difference in the coefficient of linear expansion between the temporary substrate 55 ( Figure 7 ) and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30. Generally, a single crystal silicon substrate is used as the temporary substrate 55. In this case, the difference in the coefficient of linear expansion between the support member 50 and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30 is smaller than the difference in the coefficient of linear expansion between single crystal silicon and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30.

[0092] Next, the excellent effects of the third embodiment will be described. In the third embodiment, the support member 50 is bonded to the second surface 11L of the insulating film 11, but the difference in the coefficient of linear expansion between the support member 50 and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30 is smaller than the difference in the coefficient of linear expansion between the temporary substrate 55 ( Figure 7 ) and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30. Therefore, compared with the structure in which the temporary substrate 55 remains, the generation of cracks and peeling due to thermal stress can be suppressed.

[0093] Moreover, since the support member 50 is bonded to the insulating film 11, the mechanical strength of the integrated passive component 10 can be improved as compared with the first embodiment. In order to obtain sufficient mechanical strength, it is preferable that the thickness of the support member 50 is thicker than the thickness of the lower insulating film 11A.

[0094] In order to ensure sufficient heat dissipation through the support member 50, it is preferable to use a material having a lower thermal conductivity than that of the lower insulating film 11A as the material of the support member 50. For example, it is preferable to use a material called a high thermal conductivity resin as the support member 50.

[0095] Next, a modification of the third embodiment will be described.

[0096] In the third embodiment, the support member 50 is made of an insulating resin, but an inorganic insulating material may also be used. For example, ceramics, glass, etc. may be used. In this case, it is also preferable that the difference in the linear expansion coefficient between the support member 50 and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30 is smaller than the difference in the linear expansion coefficient between the temporary substrate 55 ( Figure 7 ) and each of the resin layers 31, 32, 33 of the multilayer wiring structure 30.

[0097] [Fourth Embodiment]

[0098] Next, with reference to Figure 10A and Figure 10B the integrated passive component of the fourth embodiment will be described. Hereinafter, the description of the same structure as that of the integrated passive component of the first embodiment described with reference to Figures 1A to 7 is omitted.

[0099] Figure 10A is a plan view showing the shape and positional relationship of the components of the integrated passive component 10 of the fourth embodiment, Figure 10B is an equivalent circuit diagram of the integrated passive component 10 of the fourth embodiment. The integrated passive component 10 of the fourth embodiment is also the same as the integrated passive component 10 of the first embodiment ( Figure 1A ) and has a capacitor, an inductor, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY provided on a common insulating film. However, the integrated passive component 10 of the fourth embodiment includes a plurality of capacitors C1, C2, C3, C4, C5, C6 and a plurality of inductors L1, L2, L3, L4, L5, and constitutes a band-pass filter.

[0100] As Figure 10BAs shown, between the input terminal In and the output terminal Out, a capacitor C1, an inductor L1, and a capacitor C2 are connected in series in this order from the input terminal In side. A series circuit of a capacitor C3 and an inductor L2 and a series circuit of a capacitor C4 and an inductor L3 are connected in parallel with each other between the input terminal In and the ground terminal GND. A series circuit of a capacitor C5 and an inductor L4 and a series circuit of a capacitor C6 and an inductor L5 are connected in parallel with each other between the output terminal Out and the ground terminal GND.

[0101] The multiple capacitors C1, C2, C3, C4, C5, and C6 are respectively the same as the capacitor 20 of the integrated passive component 10 of the first embodiment ( Figure 2 ). Similarly, it is composed of a lower electrode layer, a capacitor dielectric film, and an upper electrode layer. In addition, the upper electrode layer may be composed of two separate conductor patterns, and these two conductor patterns may be used as a pair of electrode terminals of the capacitor. The multiple inductors L1, L2, L3, L4, and L5 are respectively the same as the inductor 40 of the integrated passive component 10 of the first embodiment ( Figure 2 ). Similarly, they are composed of multiple wirings in the multilayer wiring structure 30.

[0102] In Figure 10A , relatively thick hatching lines slanting upward to the right are added to the wirings of the first-layer wiring layer, and relatively light hatching lines slanting downward to the right are added to the wirings of the second-layer wiring layer. The outline of the external connection terminal is represented by the thickest solid line, and the outline of the wirings of the third-layer wiring layer is represented by the second thickest solid line.

[0103] The five inductors L1, L2, L3, L4, and L5 and the six capacitors C1, C2, C3, C4, C5, and C6 are arranged so as not to overlap each other in a top view. The wirings constituting each of the inductors L1, L2, and L4 are arranged across three wiring layers. The wirings constituting each of the inductors L3 and L5 are arranged across two wiring layers.

[0104] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment as well as in the first embodiment, it is possible to suppress the generation of cracks and peeling caused by thermal stress and to suppress the degradation of electrical characteristics. In addition, as in the fourth embodiment, by arranging multiple capacitors and multiple inductors on the common insulating film 11, various passive circuits can be realized.

[0105] Taking the above-described embodiments as examples, of course, partial replacement or combination of the structures shown in different embodiments can be performed. The same effects brought about by the same structures in multiple embodiments are not mentioned in sequence in each embodiment. And the present invention is not limited to the above-described embodiments. For example, those skilled in the art can clearly make various changes, improvements, combinations, etc.

[0106] Description of reference numerals: 10... integrated passive component; 10L... lower surface of the integrated passive component; 10U... upper surface of the integrated passive component; 11... insulating film; 11A... lower insulating film; 11B... upper insulating film; 11H... opening; 11L... second surface of the insulating film; 11U... first surface of the insulating film; 20... capacitor; 20C... contact electrode; 20D... capacitor dielectric film; 20H... opening; 20L... lower electrode layer of the capacitor; 20U... upper electrode layer of the capacitor; 30... multilayer wiring structure; 31, 32, 33... resin layers; 31H... via hole; 35, 36, 37... wirings; 38... external connection terminal; 39... solder; 40... inductor; 50... support member; 55... temporary substrate; 60... photoresist film; 60H... opening; 61... conductor layer; 62... dielectric film; 63... metal film; 64... photoresist film; 64H... opening.

Claims

1. An integrated passive component having an upper surface and a lower surface facing in opposite directions, wherein, the integrated passive component includes: an insulating film having a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface; a capacitor disposed within the insulating film; and a multilayer wiring structure disposed on the first surface of the insulating film, the multilayer wiring structure including a plurality of resin layers and a plurality of wiring layers alternately stacked, each of the plurality of wiring layers including a plurality of wirings, at least a part of the plurality of wirings constituting an inductor, the insulating film including an inorganic material layer made of an inorganic insulating material, the thickness of the inorganic material layer being thinner than the sum of the thicknesses of each of the plurality of resin layers of the multilayer wiring structure, the second surface of the insulating film constituting the lower surface.

2. An integrated passive component having an upper surface and a lower surface facing in opposite directions, wherein, the integrated passive component includes: an insulating film having a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface; a capacitor disposed within the insulating film; a multilayer wiring structure disposed on the first surface of the insulating film; and a support member adhered to the second surface of the insulating film and made of an insulating resin, the multilayer wiring structure including a plurality of resin layers and a plurality of wiring layers alternately stacked, each of the plurality of wiring layers including a plurality of wirings, at least a part of the plurality of wirings constituting an inductor, the insulating film including an inorganic material layer made of an inorganic insulating material, the thickness of the inorganic material layer being thinner than the sum of the thicknesses of each of the plurality of resin layers of the multilayer wiring structure.

3. The integrated passive component according to claim 2, wherein, the support member is formed of a resin mainly composed of epoxy or polyimide.

4. The integrated passive component according to claim 2 or 3, wherein, the thermal conductivity of the support member is higher than the thermal conductivity of the inorganic material layer of the insulating film.

5. The integrated passive component according to any one of claims 1 to 4, wherein, the plurality of wirings constituting the inductor are disposed across three or more wiring layers of the plurality of wiring layers.

6. The integrated passive component according to claim 5, wherein, in at least a part of the wirings adjacent in the stacking direction of the multilayer wiring structure, the distance in the stacking direction is equal to or greater than the maximum value of the thickness of each of the plurality of wirings constituting the inductor.

7. The integrated passive component according to any one of claims 1 to 6, wherein, the capacitor includes a lower electrode layer, an upper electrode layer disposed on a side closer to the upper surface than the lower electrode layer, and a capacitor dielectric film disposed between the lower electrode layer and the upper electrode layer, the minimum value of the thickness of each of the plurality of wirings constituting the inductor is greater than the thickness of the thicker one of the lower electrode layer and the upper electrode layer of the capacitor.

8. The integrated passive component according to any one of claims 1 to 7, wherein, the plurality of wirings are formed of Cu or an alloy mainly composed of Cu.

9. The integrated passive component according to any one of claims 1 to 8, wherein, the insulating film includes a lower insulating film having the second surface and an upper insulating film having the first surface, the capacitor is disposed between the lower insulating film and the upper insulating film, and the upper insulating film is formed of silicon oxide.

10. The integrated passive component according to any one of claims 1 to 8, wherein, the insulating film includes a lower insulating film having the second surface and an upper insulating film having the first surface, the capacitor is disposed between the lower insulating film and the upper insulating film, and the upper insulating film is formed of resin.

11. The integrated passive component according to claim 9 or 10, wherein, the lower insulating film is formed of silicon nitride.

12. A method for manufacturing an integrated passive component, wherein, a lower insulating film is formed on one surface of a temporary substrate made of a semiconductor, a capacitor is formed on a part of the region of the lower insulating film, an upper insulating film is formed on the lower insulating film so as to cover the capacitor, a multilayer wiring structure in which a plurality of resin layers and a plurality of wirings constituting an inductor are alternately laminated is formed on the upper insulating film, and the temporary substrate is removed to expose the lower insulating film.

13. The method for manufacturing an integrated passive component according to claim 12, wherein, it includes the following step: after removing the temporary substrate, an insulating support member is pasted on the surface of the exposed lower insulating film, and the difference between the linear expansion coefficient of the support member and the linear expansion coefficient of each of the plurality of resin layers of the multilayer wiring structure is smaller than the difference between the linear expansion coefficient of the temporary substrate and the linear expansion coefficient of each of the plurality of resin layers of the multilayer wiring structure.

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