Methods of forming dual layer hard masks and related deposition methods using dual layer hard masks

Abstract

The invention discloses a method for forming a double-layer hard mask and a method for forming a semiconductor structure by using the double-layer hard mask. The disclosed method includes performing a first cyclic deposition process to form a first hard mask layer, and performing a second cyclic deposition process to form a second hard mask layer directly on the first hard mask layer. The method further includes forming a CMOS structure using the dual layer hard mask.

Description

Field of the Invention

[0001] The present disclosure generally relates to the field of semiconductor processing methods and related structures, as well as the field of device and integrated circuit fabrication. More specifically, the present disclosure generally relates to methods of forming a bilayer hard mask and related deposition methods using the bilayer hard mask. The present disclosure also generally relates to structures including the bilayer hard mask. Background of the Invention

[0002] The scaling down of semiconductor devices (such as complementary metal oxide semiconductor (CMOS) devices) has led to a significant increase in the speed and density of integrated circuits. However, traditional device scaling techniques face significant challenges for future technology nodes.

[0003] For example, one challenge is to find suitable hard mask materials for fabricating the PMOS region and the NMOS region of a CMOS device structure. Thus, novel hard mask materials and hard mask structures are desirable for improved CMOS fabrication methods.

[0004] Any discussion set forth in this section, including discussions of problems and solutions, is included in the present disclosure solely for the purpose of providing background for the present disclosure and should not be taken as an admission that any or all of the discussion was known at the time the invention was made or constitutes prior art. Summary of the Invention

[0005] This summary of the invention presents some concepts in a simplified form that will be further described in detail below. This summary of the invention is not intended to necessarily identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] According to an example of the present disclosure, a method of forming a bilayer hard mask on a substrate in a reaction chamber is provided. In such an example, the method includes performing one or more deposition cycles of a first cyclic deposition process to deposit a first hard mask layer on the substrate, and performing one or more deposition cycles of a second cyclic deposition process to deposit a second hard mask layer directly on the metal oxide layer. The method may further include, wherein a first unit deposition cycle of the first cyclic deposition process includes providing a first metal precursor to the reaction chamber and providing a first oxidant to the reaction chamber. The method may further include, wherein a second unit deposition cycle of the second cyclic deposition process includes providing a second metal precursor to the reaction chamber, providing a second oxidant to the reaction chamber, and providing a second dopant precursor to the reaction chamber. The method may further include, wherein the bilayer hard mask has an average layer thickness of less than 50 angstroms. Other technical features will be apparent to those skilled in the art from the following drawings, description, and claims. The method may further include, wherein the first hard mask layer includes aluminum oxide. The method may further include, wherein the first unit deposition cycle further includes providing a first dopant precursor to the reaction chamber. The method may further include, wherein the first hard mask layer includes first doped aluminum oxide. The method may further include, wherein the second hard mask layer includes second doped aluminum oxide. The method may further include, wherein the second hard mask layer includes hafnium-doped aluminum oxide (HfAlO). The method may further include, wherein the hafnium-doped aluminum oxide has a hafnium concentration between 20 atomic % and 60 atomic %. The method may further include, wherein the second hard mask layer includes zirconium-doped aluminum oxide (ZrAlO). The method may further include, wherein the zirconium-doped aluminum oxide has a zirconium concentration between 20 atomic % and 60 atomic %. Other technical features will be apparent to those skilled in the art from the following drawings, description, and claims.

[0007] According to an example of the present disclosure, a method of forming a semiconductor structure is disclosed. In such an example, the method includes placing a substrate including an NMOS region and a PMOS region into a reaction chamber, depositing a bilayer hard mask on the NMOS region and on the PMOS region, wherein depositing the bilayer hard mask includes depositing a metal oxide layer on both the NMOS region and the PMOS region, and depositing a doped metal oxide layer directly on the metal oxide layer. The method further includes selectively removing the bilayer hard mask on the NMOS region to expose the surface of the NMOS region. The method further includes performing a cleaning process on the exposed surface of the NMOS region to form a cleaned NMOS surface. The method further includes depositing a semiconductor layer on the cleaned NMOS surface. The method further includes removing the remaining portion of the bilayer hard mask disposed on the PMOS region. The method may further include that selectively removing the bilayer hard mask on the NMOS region further includes forming a patterned resist layer on the PMOS region and contacting the exposed region of the bilayer hard mask with a wet etchant selected from hydrofluoric acid, sulfuric acid, and phosphoric acid. The method may further include that the cleaning process removes the doped metal oxide layer on the PMOS region while at least retaining the metal oxide layer on the PMOS region. The method may further include that the metal oxide layer includes an aluminum oxide layer, and the doped metal oxide layer includes a doped aluminum oxide layer. Other technical features will be apparent to those skilled in the art from the following drawings, description, and claims. The method may further include that depositing the semiconductor layer includes a selective epitaxial deposition process. The method may further include that the selective epitaxial deposition process selectively deposits the semiconductor preferentially on the cleaned NMOS surface with respect to the surface of the metal oxide layer. The method may further include that the surface of the metal oxide layer includes an amorphous surface. The method may further include that the dopant concentration in the doped aluminum oxide layer is between 20 atomic % and 60 atomic %. Other technical features will be apparent to those skilled in the art from the following drawings, description, and claims.

[0008] To summarize the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it should be understood that not all of these objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be practiced or carried out in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein, without necessarily achieving other objects or advantages taught or suggested herein.

[0009] All such embodiments are within the scope of the invention disclosed herein. These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the drawings, and the invention is not limited to any particular embodiment disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To facilitate the discussion of any particular element or act, the most significant digit in a reference number refers to the figure number in which that element is first introduced.

[0011] A more complete understanding of embodiments of the present disclosure can be obtained by referring to the detailed description and the claims when considered in conjunction with the following illustrative drawings.

[0012] Figure 1 An exemplary method in accordance with one or more embodiments of the present disclosure is shown.

[0013] Figure 2 Additional exemplary methods in accordance with one or more embodiments of the present disclosure are shown.

[0014] Figure 3 A semiconductor structure including a substrate having a first region and a second region in accordance with one or more embodiments of the present disclosure is shown.

[0015] Figure 4 A semiconductor structure including a first hard mask layer in accordance with one or more embodiments of the present disclosure is shown.

[0016] Figure 5 A semiconductor structure including a second hard mask layer in accordance with one or more embodiments of the present disclosure is shown.

[0017] Figure 6 A semiconductor structure including a patterned resist layer in accordance with one or more embodiments of the present disclosure is shown.

[0018] Figure 7 A semiconductor structure after an etching process in accordance with one or more embodiments of the present disclosure is shown.

[0019] Figure 8 A semiconductor structure after a cleaning process in accordance with one or more embodiments of the present disclosure is shown.

[0020] Figure 9 A semiconductor structure including a semiconductor layer in accordance with one or more embodiments of the present disclosure is shown.

[0021] Figure 10 A semiconductor structure after removal of the first hard mask layer in accordance with one or more embodiments of the present disclosure is shown.

[0022] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to assist in improving understanding of the illustrated embodiments of the present disclosure. Detailed Description

[0023] The following description of exemplary embodiments of the methods and compositions provided is merely exemplary and for illustrative purposes only. The following description is not intended to limit the scope of the present disclosure or the claims. Additionally, the recitation of multiple embodiments having the indicated features or steps is not intended to exclude other embodiments having additional features or steps, or other embodiments incorporating different combinations of the recited features or steps.

[0024] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed by a method according to embodiments of the present invention. The substrate can include bulk materials such as silicon (e.g., single-crystalline silicon), other Group IV materials such as germanium, or other semiconductor materials such as Group II-VI or III-V semiconductor materials, and can include one or more layers covering or underlying the bulk material. Additionally, the substrate can include various features such as depressions, protrusions, etc. formed within or on at least a portion of the substrate layer. By way of example, the substrate can include a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. Further, the term "substrate" can refer to any one or more underlying materials that can be used or on which devices, circuits, or films can be formed. The "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous. The "substrate" can be in any form, such as a powder, a plate, or a workpiece. Plate-like substrates can include wafers of various shapes and sizes. The substrate can be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. A continuous substrate can extend beyond the boundaries of the processing chamber where the deposition process occurs and can be moved through the processing chamber such that the process continues until the end of the substrate is reached. A continuous substrate can be provided by a continuous substrate supply system that allows for the fabrication and output of the continuous substrate in any suitable form. Non-limiting examples of continuous substrates can include sheets, non-woven membranes, rolls, foils, meshes, flexible materials, a bundle of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). A continuous substrate can also include a carrier or sheet on which a discontinuous substrate is mounted. By way of example, the substrate can include a semiconductor material. The semiconductor material can include or be used to form one or more of the source, drain, or channel regions of a device. The substrate can also include an interlayer dielectric (e.g., silicon oxide) and / or a high-k dielectric material layer covering the semiconductor material. In the present context, a high-k dielectric material (or high-k dielectric) is a material having a dielectric constant greater than that of silicon dioxide.

[0025] As used herein, the terms "film" and / or "layer" may be used interchangeably and may refer to any continuous or discontinuous structure and material, such as a material deposited by a method disclosed herein. For example, a layer may include a two-dimensional material, a three-dimensional material, nanoparticles, a partial or complete molecular layer, or a partial or complete atomic layer, or an atomic and / or molecular cluster. A layer may be composed, in part or in whole, of a plurality of dispersed atoms on a substrate surface and / or embedded in a substrate and / or embedded in a device fabricated on the substrate. A layer may include a material or layer having pinholes and / or islands. A layer may be at least partially continuous. A layer may be patterned, e.g., subdivided, and may be composed of a plurality of semiconductor devices.

[0026] As used herein, a "structure" may be or include a substrate as described herein. A structure may include one or more layers covering or within a substrate, such as one or more layers formed according to the methods described herein. A complete device or a partial device portion may be included within or on the structure.

[0027] As used herein, the term "cyclic deposition process" or "cyclic deposition process" may refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include an ALD component and a cyclic CVD component.

[0028] The term "atomic layer deposition" may refer to a vapor deposition process in which deposition cycles (usually a plurality of consecutive deposition cycles) are carried out in a processing chamber. The term atomic layer deposition as used herein also means to include processes designated by related terms, such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when carried out with alternating pulses of precursor / reactant gas and purge gas (e.g., an inert carrier gas).

[0029] Typically, for an ALD process, during each deposition cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface that may include previously deposited material from a previous ALD cycle or other material), forming a monolayer or sub-monolayer of a material that does not readily react with additional precursor (i.e., a self-limiting reaction). Thereafter, in some cases, a reactant (e.g., another precursor or reaction gas) may subsequently be introduced into the processing chamber to convert the chemisorbed precursor into the desired material on the deposition surface. The reactant is capable of further reacting with the precursor. During one or more deposition cycles, e.g., during each step of each cycle, a purge step may be utilized to remove any excess precursor from the processing chamber and / or any excess reactant and / or reaction by-products from the reaction chamber.

[0030] In the present disclosure, any two numbers of a variable can constitute a viable range of the variable, and any indicated range may or may not include endpoints. Further, any value of the indicated variable (whether or not denoted by "about") may refer to an exact value or an approximate value, and includes equivalents, and in some embodiments may refer to an average value, a median value, a representative value, a majority value, etc. Further, in the present disclosure, the terms "comprising", "consisting of", and "having" may independently refer to "generally or broadly comprising", "including", "substantially consisting of", or "consisting of" in some embodiments. In the present disclosure, the meaning of any defined term does not necessarily exclude the ordinary and customary meaning in some embodiments. In some cases, the percentages referred to herein may be relative or absolute percentages.

[0031] In the presently disclosed embodiments, a number of exemplary materials are given, and it should be noted that the chemical formulas given for each exemplary material should not be construed as limiting, and the non-limiting exemplary materials given should not be limited by the exemplary stoichiometry given.

[0032] In the specification, it should be understood that the terms "on" or "above" may be used to describe a relative positional relationship. Another element, film, or layer may be directly on the layer, or another layer (intermediate layer) or element may be interposed therebetween, or a layer may be disposed on the layer but not completely cover the surface of the layer. Thus, unless the term "directly" is used alone, the terms "on" or "above" will be interpreted as relative concepts. Similarly, it should be understood that the terms "under", "below", or "beneath" will be interpreted as relative concepts.

[0033] Various embodiments of the present disclosure relate to methods for forming semiconductor structures, particularly semiconductor structures including a bilayer hard mask. Various embodiments of the present disclosure also relate to deposition methods employing a bilayer hard mask. More particularly, the processes employed in the fabrication of CMOS device structures may employ optimized hard mask materials to avoid epitaxial deposition of semiconductor layers, such as silicon germanium (SiGe) and phosphorous-doped silicon (SiP), at undesired locations.

[0034] In some CMOS fabrication methods, a metal oxide hard mask, such as an aluminum oxide (AlO x ) hard mask, may be used during an etching process. However, a single-layer metal oxide hard mask may include pinholes formed during the CMOS fabrication process, and such pinholes may cause problems in downstream CMOS fabrication processes.

[0035] Various embodiments of the present disclosure include methods for forming and using a dual hard mask including a first hard mask layer and a second hard mask layer. For example, the first hard mask layer may include a metal oxide, such as aluminum oxide, and the second hard mask layer may include a doped metal oxide, such as hafnium-doped aluminum oxide or zirconium-doped aluminum oxide. In such an example, the second hard mask layer has a lower dry etch rate relative to the first hard mask layer.

[0036] Accordingly, embodiments of the present disclosure employ a dual hard mask, such as a metal oxide and a doped metal oxide, rather than a single metal oxide hard mask layer, particularly during manufacturing processes where masking regions are required to prevent unwanted epitaxial deposition in undesired regions of a substrate, thereby enabling a selective deposition method. In some embodiments, the dual hard mask composed of a metal oxide and a doped metal oxide may be in the form of a laminated structure. In some embodiments, the dual hard mask composed of a metal oxide and a doped metal oxide may be in the form of a mixed doped metal oxide structure.

[0037] In an example according to the present disclosure, the upper hard mask layer (the second hard mask layer) may have a lower dry etch rate than the lower hard mask layer (the first hard mask layer). In such an example, the upper hard mask layer may be formed to a thickness low enough such that it can be removed by a wet etch process employed during a CMOS manufacturing process. The CMOS manufacturing process of the present disclosure may employ a first wet etch step (e.g., using dilute hydrofluoric acid) that can remove the dual hard mask from a first region of the substrate (e.g., the NMOS region) while leaving the dual hard mask in place to protect a second region of the substrate (e.g., the PMOS region).

[0038] In a subsequent manufacturing process of the present disclosure step, after epitaxially depositing a semiconductor layer on the first region of the substrate (e.g., depositing on the NMOS region), the remaining dual hard mask on the second region of the substrate (e.g., the PMOS region) can be removed. The uppermost hard mask layer with a lower etch rate can be removed while still leaving the underlying lower hard mask layer intact, thereby avoiding the formation of any pinholes in the lower hard mask layer. As a result, for example, subsequent epitaxial deposition processes on the NMOS region remain protected from the PMOS region. In some embodiments, the use of the dual hard mask and the method of forming such a dual hard mask can be repeated again to protect the NMOS region during epitaxial deposition of a semiconductor layer (e.g., a SiGe semiconductor layer) on the PMOS region.

[0039] Accordingly, the present disclosure may include a method for forming a semiconductor structure. In some embodiments, the method may include disposing a substrate including a first region and a second region into a reaction chamber and forming a bilayer hard mask on the substrate. In some embodiments, forming the bilayer first hard mask layer may include performing one or more deposition cycles of a first cyclic deposition process to deposit a first hard mask layer including a metal oxide on the substrate; and performing one or more deposition cycles of a second cyclic deposition process to directly deposit a second hard mask layer including a doped metal oxide layer on the first hard mask layer.

[0040] Turning now to the drawings, Figure 1 an exemplary method 100 is shown that can be used to form a bilayer hard mask on a substrate including a first region and a second region. Briefly, method 100 includes the steps of providing a substrate in a reaction chamber, performing a first cyclic deposition process 102 to deposit a first hard mask layer including a metal oxide layer, and subsequently performing a second cyclic deposition process 110 to directly deposit a second hard mask layer including a doped metal oxide layer on the first hard mask layer, i.e., directly on the metal oxide layer. The first hard mask layer (i.e., the metal oxide layer) is disposed adjacent to the substrate, and the second hard mask layer (i.e., the doped metal oxide layer) is disposed away from the substrate, and the combination of the first hard mask layer and the second hard mask layer constitutes the bilayer hard mask.

[0041] According to an example of the present disclosure, method 100 includes the step of providing a substrate in a reaction chamber. In such an example, the reaction chamber for forming the bilayer hard mask is configured and arranged to perform an atomic layer deposition (ALD) process. In other examples, the reaction chamber for forming the bilayer hard mask is configured and arranged to perform a cyclic chemical vapor deposition (CCVD) process. In other examples, the reaction chamber for forming the bilayer hard mask is configured and arranged to perform a hybrid ALD / CCVD process. In some embodiments, the reaction chamber is an independent reaction chamber or part of a cluster tool. In some embodiments, the reaction chamber is a batch tool. In some embodiments, a flow-type reactor may be utilized. In some embodiments, a showerhead-type reactor may be used. In some embodiments, a spatial separation reactor may be utilized. In some embodiments, a single-wafer reactor with high-volume manufacturing capabilities may be utilized. In other embodiments, a batch reactor including multiple substrates may be utilized. For embodiments using a batch reactor, the number of substrates may be in the range of 10 to 200 or 50 to 150 or even 100 to 130. The reactor may be configured as a thermal reactor—without a plasma excitation device. Alternatively, the reactor may include a direct and / or remote plasma device.

[0042] According to an example of the present disclosure, a substrate disposed in a reaction chamber is heated to a deposition temperature required for a deposition process. In such an example, the substrate is heated to a substrate temperature below 800 °C, below 600 °C, below 400 °C, or below 200 °C. In some embodiments of the present disclosure, the substrate temperature may be higher than room temperature, between 200 °C and 800 °C, or between 200 °C and 600 °C, or between 200 °C and 400 °C.

[0043] In addition to controlling the temperature of the substrate, the pressure in the reaction chamber can also be adjusted to enable the deposition of a bilayer hard mask. For example, in some embodiments of the present disclosure, the pressure in the reaction chamber can be less than 760 Torr, or between 0.1 Torr and 10 Torr, or between 0.5 Torr and 5 Torr, or between 1 Torr and 4 Torr.

[0044] According to an example of the present disclosure, method 100( Figure 1 ) includes performing a first cycle deposition process 102 to deposit a first hard mask layer including a metal oxide layer on a substrate surface, particularly on a first region and a second region of the substrate. For example, embodiments of the present disclosure may include performing one or more deposition cycles of the first cycle deposition process 102 to deposit a metal oxide layer containing alumina on the surface of the substrate, particularly on the surfaces of the first region and the second region.

[0045] In some embodiments, the first cycle deposition process 102 may include providing a first metal precursor to the reaction chamber (step 104) and providing a first oxidant to the reaction chamber (step 106). The first metal precursor and the first oxidant may be provided to the reaction chamber separately and / or sequentially, with or without an intervening reaction chamber purge sequence. In some embodiments, steps 104 and 106 (and any intervening purge sequences) may constitute a first unit deposition cycle, and the first unit deposition cycle may be repeated one or more times to deposit the first hard mask layer (e.g., a metal oxide layer) on the substrate, particularly on the first region and the second region of the substrate, to a desired thickness.

[0046] According to an example of the present disclosure, step 104 includes providing a first metal precursor to the reaction chamber. The first metal precursor may be pulsed into the reaction chamber. The term "pulsed" can be understood to include feeding the precursor into the reaction chamber within a predetermined amount of time. Unless otherwise specified, the term "pulsed" does not limit the length or duration of the pulse, and the pulse can be of any length. The first metal precursor pulse may be supplied to the reaction chamber together with a carrier gas stream. In some embodiments, the first metal precursor may include a volatile metal species that reacts with the substrate surface. The first metal precursor pulse may saturate the substrate surface such that the excess component of the first metal precursor pulse does not further react with the molecular layer formed by the process.

[0047] The first metal precursor pulse is preferably provided as a gaseous reactant. For the purposes of the present disclosure, a first metal precursor gas may be considered "volatile" if the substance exhibits a sufficient vapor pressure under the process conditions to transport the substance to the substrate surface at a sufficient concentration to saturate the exposed surface.

[0048] According to an example of the present disclosure, the first hard mask layer may include an alumina layer, and the step of providing the first metal precursor to the reaction chamber (step 104) may include providing an aluminum precursor to the reaction chamber. In such an example, the aluminum precursor is selected from trimethylaluminum (TMA), dimethylaluminum chloride, aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), tris(tert-butyl)aluminum (TTBA), tris(isopropanol)aluminum (TIPA), and triethylaluminum (TEA). In some embodiments, the aluminum precursor is dimethylaluminum isopropoxide (DMAI).

[0049] According to an example of the present disclosure, method 100 includes providing a first oxidant to the reaction chamber (step 106). In such an example, the first oxidant is selected from water (H2O), hydrogen peroxide (H2O2), ozone (O3), nitrogen oxides such as nitric oxide (NO), nitrous oxide (N2O), and nitrogen dioxide (NO2). In some embodiments, the first oxidant includes an organic alcohol such as isopropanol.

[0050] According to an example of the present disclosure, the first cyclic deposition process 102 is repeated one or more times until a desired end criterion is reached (decision block 108). In such an example, the end criterion of the first cyclic deposition process 102 is reached when a first hard mask layer (such as a metal oxide layer) of a desired thickness is deposited, or alternatively, when a predetermined number of deposition cycles of the first cyclic deposition process 102 have been performed. As a non-limiting example, the first cyclic deposition process 102 may terminate after an alumina layer of a desired thickness has been deposited on the substrate, particularly on the first and second regions of the substrate.

[0051] According to an example of the present disclosure, the first hard mask layer (such as an alumina layer) is deposited to an average layer thickness of less than 50 angstroms, less than 45 angstroms, less than 40 angstroms, less than 35 angstroms, less than 30 angstroms, less than 25 angstroms, less than 20 angstroms, less than 15 angstroms, or less than 10 angstroms. In some embodiments, the first hard mask layer (such as an alumina layer) is deposited to an average layer thickness between 10 angstroms and 50 angstroms.

[0052] According to an example of the present disclosure, the first hard mask layer (such as an alumina layer) is deposited in an amorphous state. In such an example, the amorphous first hard mask layer may improve the subsequent selective epitaxial deposition process by suppressing deposition on the amorphous surface of the amorphous first hard mask layer. In such an example, for example, X-ray diffraction analysis may be employed to determine the crystallinity of the first hard mask layer.

[0053] According to an example of the present disclosure, method 100 includes performing one or more deposition cycles of a second cyclic deposition process 110 to deposit a second hard mask layer including a doped metal oxide layer. In such an example, the second hard mask layer (i.e., the doped metal oxide layer) is deposited on the first hard mask layer (i.e., the metal oxide layer). In some embodiments, the second hard mask layer is directly deposited on the first hard mask layer, thereby forming a double-layer hard mask.

[0054] According to an example of the present disclosure, the second cyclic deposition process 110 is performed to deposit a second hard mask layer (e.g., a doped metal oxide layer) on the first hard mask layer, and in certain embodiments, directly on the first hard mask layer, thereby forming a double-layer hard mask.

[0055] According to an example of the present disclosure, the second cyclic deposition process 110 includes providing a second metal precursor to the reaction chamber (step 112), providing a second oxidant to the reaction chamber (step 114), and providing a dopant precursor to the reaction chamber (step 116). In such an example, the second hard mask layer may include doped alumina. In some embodiments, the doped alumina includes hafnium-doped alumina (HfAlO). In some embodiments, the doped alumina includes zirconium-doped alumina.

[0056] According to an example of the present disclosure, the second cyclic deposition process 110 includes providing a second metal precursor to the reaction chamber (step 112). In such an example, the second metal precursor may include an aluminum precursor. In such an example, the aluminum precursor is selected from trimethylaluminum (TMA), dimethylaluminum chloride, aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), tris(tert-butyl)aluminum (TTBA), tris(isopropanol)aluminum (TIPA), and triethylaluminum (TEA). In some embodiments, the aluminum precursor includes dimethylaluminum isopropoxide (DMAI).

[0057] According to an example of the present disclosure, the second cyclic deposition process 110 includes providing a second oxidant to the reaction chamber (step 114). In such an example, the second oxidant is selected from water (H2O), hydrogen peroxide (H2O2), ozone (O3), nitrogen oxides such as nitric oxide (NO), nitrous oxide (N2O), and nitrogen dioxide (NO2). In some embodiments, the second oxidant includes an organic alcohol such as isopropanol.

[0058] According to an example of the present disclosure, the second cycle deposition process 110 includes providing a dopant precursor to the reaction chamber (step 116). In some embodiments, the dopant precursor is a hafnium dopant precursor. In such embodiments, the hafnium dopant precursor is selected from hafnium tetrachloride (HfCl4), hafnium tetraiodide (HfI4), hafnium tetrabromide (HfBr4), hafnium tetrakis(ethylmethylamino) (Hf(NEtMe)4), hafnium tetrakis(dimethylamino) (Hf(NMe2)4), hafnium tetrakis(diethylamino) (Hf(NEt2)4), hafnium tris(dimethylamino) cyclopentadienyl HfCp(NMe2)3, and bis(methylcyclopentadienyl)methoxymethyl hafnium (MeCp)2Hf(CH)3(OCH3). In some embodiments, the dopant precursor is a zirconium dopant precursor. In such embodiments, the zirconium dopant precursor is selected from Zr(NEtMe)4, ZrCp2(NMe2)2, Zr(O t Bu)4.

[0059] According to an example of the present disclosure, the second cycle deposition process 110 is repeated one or more times until a desired end criterion is reached (decision block 118). In such an example, the end criterion of the second cycle deposition process 110 is reached when a second hard mask layer of a desired thickness (e.g., a doped metal oxide layer) is deposited, or alternatively, when a predetermined number of deposition cycles of the second cycle deposition process 110 have been performed. As a non-limiting example, the second cycle deposition process 110 may terminate after a hafnium-doped alumina layer or a zirconium-doped alumina layer of a desired thickness has been deposited on the substrate, particularly on the first and second regions of the substrate.

[0060] According to an example of the present disclosure, the second hard mask layer (e.g., a hafnium- or zirconium-doped alumina layer) is deposited to an average layer thickness of less than 25 angstroms, less than 20 angstroms, less than 15 angstroms, less than 10 angstroms, or less than 5 angstroms. In some embodiments, the second hard mask layer (e.g., a hafnium- or zirconium-doped alumina layer) is deposited to an average layer thickness between 5 angstroms and 50 angstroms.

[0061] According to examples of the present disclosure, the various steps of the second cycle deposition process 110 (i.e., steps 112, 114, and 116) can be performed in any order or sequence in parallel (or at least partially in parallel), and can include multiple repetitions of one or more steps. In such examples, each of steps 112, 114, and 116 can be repeated before subsequent steps of the second cycle deposition process 110 are performed. In some embodiments, step 112 can be repeated one or more times before proceeding to step 114. In some embodiments, step 114 can be repeated one or more times before proceeding to step 116. By varying the ratio of the number of execution steps within one or more unit deposition cycles of the second cycle deposition process 110, the dopant concentration (e.g., hafnium or zirconium) in the deposited doped metal oxide layer can be manipulated or controlled.

[0062] According to examples of the present invention, the doped metal oxide layer deposited by the second cycle deposition process 110 has the following dopant concentrations: greater than 0 atomic %, greater than 5 atomic %, greater than 10 atomic %, greater than 15 atomic %, greater than 20 atomic %, greater than 25 atomic %, greater than 30 atomic %, greater than 35 atomic %, greater than 40 atomic %, greater than 45 atomic %, greater than 50 atomic %, greater than 55 atomic %, or greater than 60 atomic %. In some embodiments, the doped metal oxide layer deposited by the second cycle deposition process 110 has a dopant concentration between 20 atomic % and 60 atomic %.

[0063] In some embodiments, the doped metal oxide layer deposited by the second cycle deposition process 110 is hafnium-doped aluminum oxide, which has the following hafnium dopant concentrations: greater than 0 atomic %, greater than 5 atomic %, greater than 10 atomic %, greater than 15 atomic %, greater than 20 atomic %, greater than 25 atomic %, greater than 30 atomic %, greater than 35 atomic %, greater than 40 atomic %, greater than 45 atomic %, greater than 50 atomic %, greater than 55 atomic %, or greater than 60 atomic %. In some embodiments, the hafnium-doped aluminum oxide deposited by the second cycle deposition process 110 has a hafnium dopant concentration between 20 atomic % and 60 atomic %.

[0064] In some embodiments, the doped metal oxide layer deposited by the second cycle deposition process 110 is zirconium-doped aluminum oxide, which has the following zirconium dopant concentrations: greater than 0 atomic %, greater than 5 atomic %, greater than 10 atomic %, greater than 15 atomic %, greater than 20 atomic %, greater than 25 atomic %, greater than 30 atomic %, greater than 35 atomic %, greater than 40 atomic %, greater than 45 atomic %, greater than 50 atomic %, greater than 55 atomic %, or greater than 60 atomic %. In some embodiments, the zirconium-doped aluminum oxide deposited by the second cycle deposition process 110 has a zirconium dopant concentration between 20 atomic % and 60 atomic %.

[0065] In the above embodiments, for example, X-ray fluorescence (XRF) can be used to determine the dopant concentration.

[0066] According to other examples of the present disclosure, the first hard mask layer can include a doped metal oxide layer. In such an example, the first cyclic deposition process 102 includes an additional step of supplying a first dopant precursor to the reaction chamber. In such an example, the first unit deposition cycle of the first cyclic deposition process 102 includes: supplying a first metal precursor to the reaction chamber, supplying a first oxidant to the reaction chamber, and supplying a first dopant precursor to the reaction chamber. The additional step of supplying the first dopant precursor to the reaction chamber can be the same as or similar to step 116 of method 100. In such an example, the first cyclic deposition process 102 is used to deposit the first doped metal oxide layer, and the second cyclic deposition process 110 is used to directly deposit a second doped metal oxide layer on the first doped metal oxide layer. In such an example, the second unit deposition cycle of the second cyclic deposition process 110 includes: supplying a second metal precursor to the reaction chamber, supplying a second oxidant to the reaction chamber, and supplying a second dopant precursor to the reaction chamber. In such an example, the first doped metal oxide layer can include first doped alumina doped with hafnium or zirconium as described above.

[0067] According to other examples of the present disclosure, the first hard mask layer can include a doped metal oxide layer, and the second hard mask layer can include a metal oxide layer. In such an example, the first cyclic deposition process 102 includes an additional step of supplying a first dopant precursor to the reaction chamber. In such an example, the first unit deposition cycle of the first cyclic deposition process 102 includes: supplying a first metal precursor to the reaction chamber, supplying a first oxidant to the reaction chamber, and supplying a first dopant precursor to the reaction chamber. In such an example, the second unit deposition cycle of the second cyclic deposition process 110 omits the step of supplying a dopant precursor to the reaction chamber (step 116), such that the second cyclic deposition process deposits a metal oxide layer, i.e., an undoped metal oxide layer. In such an example, the second hard mask layer can include an alumina layer.

[0068] The additional step of supplying the first dopant precursor to the reaction chamber can be the same as or similar to step 116 of method 100. In such an example, the first cyclic deposition process 102 is used to deposit the first doped metal oxide layer, and the second cyclic deposition process 110 is used to directly deposit a second doped metal oxide layer on the first doped metal oxide layer. In such an example, the second unit deposition cycle of the second cyclic deposition process 110 includes: supplying a second metal precursor to the reaction chamber, supplying a second oxidant to the reaction chamber, and supplying a second dopant precursor to the reaction chamber. In such an example, the first doped metal oxide layer can include first doped alumina doped with hafnium or zirconium as described above.

[0069] Various embodiments of the present disclosure also relate to methods for semiconductor structures including a double hard mask and semiconductor structures formed by employing such a double hard mask. In some embodiments, the double hard mask of the present disclosure can be used in the fabrication of CMOS device structures. According to an example of the present disclosure, method 200( Figure 2 ) illustrates the use of the double hard mask of the present disclosure in the fabrication of a CMOS device structure.

[0070] According to an example of the present disclosure, method 200 includes placing a substrate including a first region and a second region in a reaction chamber and forming a double hard mask (method 100) on the substrate, as previously referenced Figure 1 as described.

[0071] According to an example of the present disclosure, method 200 includes selectively removing the double hard mask from the first region of the substrate to expose the surface of the first region of the substrate (step 204). In such an example, selectively removing the double hard mask from the first region of the substrate further includes forming a patterned resist layer on the second region of the substrate and contacting the exposed area of the double hard mask with a wet etchant. In such an example, the wet etchant is selected from hydrofluoric acid, sulfuric acid, and phosphoric acid, and diluted and hydrogen peroxide mixtures of the foregoing wet etchants.

[0072] According to an example of the present disclosure, method 200 includes performing a cleaning process on the exposed surface of the first region of the substrate, thereby forming a cleaned first region surface (step 206). In such an example, the cleaning process includes contacting the exposed surface of the first region of the substrate with a plasma generated from a gas mixture including a fluorine-containing gas (e.g., hydrofluoric acid, NF3, NF3*) and ammonia. In such an example, the cleaning process removes at least a portion of the second hard mask layer from the second region of the substrate. In such an example, the cleaning process removes the second hard mask layer from the second region of the substrate. In other examples, the cleaning process includes a gas phase etching process. In such an example, the gas phase etching process includes heating the substrate (e.g., to a temperature between 20 °C and 100 °C) and contacting the substrate with a gas phase etchant (e.g., hydrofluoric acid vapor).

[0073] According to an example of the present disclosure, method 200 includes forming a semiconductor layer on the cleaned first region surface (step 208). In such an example, forming the semiconductor layer includes directly depositing a semiconductor layer on the cleaned first region surface by an epitaxial deposition process. In such an example, the epitaxial deposition process is a selective epitaxial deposition process. In some embodiments, the epitaxial deposition process can be used to deposit a SiGe layer or a SiP layer on the cleaned first surface.

[0074] According to an example of the present disclosure, method 200 includes removing any remaining portion of the bilayer hard mask from a second region of the substrate (step 210).

[0075] According to an example of the present disclosure, the bilayer hard mask of the present disclosure can be used in other methods for manufacturing CMOS device structures. In such an example, the process includes placing a substrate including an NMOS region and a PMOS region into a reaction chamber and depositing a bilayer hard mask on the NMOS region and the PMOS region. In such an example, depositing the bilayer hard mask includes depositing a metal oxide layer on both the NMOS region and the PMOS region, and depositing a doped metal oxide layer on the first hard mask layer. In some embodiments, the bilayer hard mask is deposited by a cyclic deposition process, such as an atomic layer deposition process. In such an example, the process may further include selectively removing the bilayer hard mask on the NMOS region to expose the surface of the NMOS region and performing a cleaning process on the exposed surface of the NMOS region to form a clean NMOS surface. In such an example, selectively removing the bilayer hard mask on the NMOS region may further include forming a patterned resist layer on the PMOS region and contacting the exposed area of the bilayer hard mask with a wet etchant selected from hydrofluoric acid, sulfuric acid, and phosphoric acid. In such an example, the process may further include depositing a semiconductor layer on the clean NMOS surface. In such an example, the semiconductor layer is deposited by an epitaxial deposition process.

[0076] Various embodiments of the present disclosure also include semiconductor structures formed by the methods disclosed herein. According to an example of the present disclosure, Figure 3 A semiconductor structure 300 including a substrate 302 is shown. The substrate 302 includes a first region 304 (e.g., an NMOS region) and a second region 306 (e.g., a PMOS region).

[0077] According to an example of the present disclosure, Figure 4 A semiconductor structure 400 including a first hard mask layer is shown. The first hard mask layer includes a metal oxide layer 402 (e.g., an alumina layer) directly deposited on the first region 304 and the second region 306 of the substrate 302. In such an example, the metal oxide layer 402 is deposited by the first cyclic deposition process 102 of method 100 ( Figure 1 ).

[0078] According to an example of the present disclosure, Figure 5 A semiconductor structure 500 including a second hard mask layer is shown. The second hard mask layer includes a doped metal oxide layer 502 (e.g., a hafnium- or zirconium-doped alumina layer) directly deposited on the metal oxide layer 402. As Figure 5As shown, the metal oxide layer 402 and the doped metal oxide layer 502 together form a double hard mask 504. In such an example, the doped metal oxide layer 502 is deposited by the second cycle deposition process 110 of the method 100 ( Figure 1 ).

[0079] According to an example of the present disclosure, Figure 6 a semiconductor structure 600 is shown, which includes a patterned resist layer 602 formed on a second region 306 (e.g., a PMOS region) of a substrate 302.

[0080] According to an example of the present disclosure, Figure 7 a semiconductor structure 700 is shown after selectively removing the double hard mask 504 from the first region 304 of the substrate 302 while retaining the double hard mask 504 on the second region 306 of the substrate 302, as described above with reference to step 204 of the method 200 ( Figure 2 ). In such an example, any remaining portion of the patterned resist layer can be removed after the etching process.

[0081] According to an example of the present disclosure, Figure 8 a semiconductor structure 800 is shown after performing a pre-cleaning process to clean the surface of the first region 304 of the substrate 302, as described above with reference to step 206 of the method 200 ( Figure 2 ). In such an example, the cleaned surface of the first region may include a cleaned NMOS surface region. In such an example, the pre-cleaning process removes the second hard mask layer, i.e., the doped metal oxide layer 502 provided on the second region 306 of the substrate 302. In such an example, the pre-cleaning process may remove a portion of the first hard mask layer, i.e., a portion of the metal oxide layer 402.

[0082] According to an example of the present disclosure, Figure 9 a semiconductor structure 900 is shown after depositing a semiconductor layer 902 on the first region 304 of the substrate 302. In such an example, the semiconductor layer 902 is deposited on the first region 304 (e.g., on the NMOS region) by an epitaxial deposition process. In some embodiments of the present disclosure, the epitaxial deposition process is a selective epitaxial deposition process. In such an embodiment, the semiconductor layer 902 is selectively deposited on the first region 304 with respect to the top surface of the metal oxide layer 402. In such an example, with respect to the surface of the metal oxide layer (e.g., the amorphous surface of the metal oxide layer), the selective epitaxial deposition process selectively preferentially deposits the semiconductor layer 902 on the cleaned NMOS surface.

[0083] As used herein, the selectivity of a deposition process on surface A relative to surface B can be given by the percentage calculated as [(deposition on surface A)-(deposition on surface B)] / (deposition on surface A). The deposition can be measured by any of a variety of methods. For example, the deposition can be given as a measured thickness of the deposited material, or can be given as a measured amount of the deposited material.

[0084] In an example according to the present disclosure, the selectivity of a selective epitaxial deposition process for depositing a semiconductor layer 902 on a first region 304 relative to the top surface of a metal oxide layer 402 is greater than 10%, greater than 50%, greater than 75%, greater than 85%, greater than 90%, greater than 93%, greater than 95%, greater than 98%, greater than 99%, greater than 99.5%, equal to approximately 100%.

[0085] In an example according to the present disclosure, Figure 10 A semiconductor structure 1000 is shown after removing the remaining portion of a bilayer hard mask disposed on a second region 306 (e.g., on a PMOS region). In such an example, the remaining portion of the bilayer hard mask includes the remaining portion of a doped metal oxide layer 502. In such an example, the remaining portion of the doped metal oxide layer 502 can be removed by various etching methods.

[0086] To summarize the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it should be understood that not all of these objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be implemented or carried out in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein, without necessarily achieving other objects or advantages taught or suggested herein.

[0087] All such embodiments are within the scope of the invention disclosed herein. From the following detailed description of certain embodiments with reference to the accompanying drawings, these and other embodiments will become apparent to those skilled in the art, and the invention is not limited to any particular embodiment disclosed.

Claims

1. A method for forming a double-layer hard mask on a substrate in a reaction chamber, the method comprising: performing one or more deposition cycles of a first cyclic deposition process to deposit a first hard mask layer including a metal oxide layer on the substrate; as well as One or more deposition cycles of the second cyclic deposition process are performed to deposit a second hard mask layer including a doped metal oxide layer directly on the metal oxide layer.

2. The method according to claim 1, wherein: The first unit deposition cycle of the first cyclic deposition process includes providing a first metal precursor to the reaction chamber and providing a first oxidant to the reaction chamber.

3. The method according to claim 2, wherein: The first hard mask layer includes aluminum oxide.

4. The method according to claim 2, wherein: The first unit deposition cycle also includes providing a first dopant precursor to the reaction chamber.

5. The method according to claim 4, wherein: The first hard mask layer includes a first doped aluminum oxide.

6. The method according to claim 2, wherein: The second unit deposition cycle of the second cyclic deposition process includes providing a second metal precursor to the reaction chamber, providing a second oxidant to the reaction chamber, and providing a second dopant precursor to the reaction chamber.

7. The method according to claim 6, wherein: The second hard mask layer includes a second doped aluminum oxide.

8. The method according to claim 7, wherein: The second hard mask layer includes hafnium-doped aluminum oxide (HfAlO).

9. The method according to claim 8, wherein: The hafnium-doped aluminum oxide has a hafnium concentration between 20 atomic % and 60 atomic %.

10. The method according to claim 7, wherein: The second hard mask layer includes zirconium-doped aluminum oxide (ZrAlO).

11. The method according to claim 10, wherein: The zirconium-doped alumina has a zirconium concentration between 20 atomic % and 60 atomic %.

12. The method according to claim 1, wherein: The dual-layer hard mask has an average layer thickness of less than 50 angstroms.

13. A method of forming a semiconductor structure, the method comprising: placing a substrate including an NMOS region and a PMOS region into a reaction chamber; Depositing a double-layer hard mask on the NMOS region and on the PMOS region, wherein depositing the double-layer hard mask comprises: Depositing a metal oxide layer on both the NMOS region and the PMOS region; depositing a doped metal oxide layer directly on the metal oxide layer; selectively removing the double-layer hard mask on the NMOS region to expose the surface of the NMOS region; performing a cleaning process on the exposed surface of the NMOS region to form a clean NMOS surface; depositing a semiconductor layer on the clean NMOS surface; and The remaining portion of the double-layer hard mask disposed on the PMOS region is removed.

14. The method according to claim 13, wherein: Selectively removing the double-layer hard mask on the NMOS region further includes forming a patterned resist layer on the PMOS region and contacting the exposed region of the double-layer hard mask with a wet etchant selected from hydrofluoric acid, sulfuric acid, and phosphoric acid.

15. The method according to claim 13, wherein: The cleaning process removes the doped metal oxide layer on the PMOS region while at least retaining the metal oxide layer on the PMOS region.

16. The method according to claim 15, wherein: Depositing the semiconductor layer includes a selective epitaxial deposition process.

17. The method according to claim 16, wherein: The selective epitaxial deposition process selectively and preferentially deposits the semiconductor layer on the clean NMOS surface relative to the surface of the metal oxide layer.

18. The method according to claim 17, wherein: The surface of the metal oxide layer includes an amorphous surface.

19. The method according to claim 13, wherein: The metal oxide layer includes an aluminum oxide layer, and the doped metal oxide layer includes a doped aluminum oxide layer.

20. The method according to claim 19, wherein: The dopant concentration in the doped aluminum oxide layer is between 20 atomic % and 60 atomic %.

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