Method for improving overlay precision by optimizing wafer edge voltage
By optimizing the wafer edge voltage and using rapid heat treatment equipment to form a heat field reduction distribution, the problems of poor lithography erection accuracy, high cost or affecting wafer surface uniformity in the prior art are solved, and the photolithography accuracy is significantly improved.
Patent Information
- Application Number
- CN202510640489.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2025-06-17
AI Technical Summary
When the prior art improves the accuracy of lithography engraving, the cost is high and the stability is difficult to promote, or it may affect the uniformity of the wafer surface.
By optimizing the wafer edge voltage, a heating device in a fast heat treatment equipment forms a heat field reduction distribution, which promotes stress release in the wafer, thereby improving the intercalation accuracy in the lithography process.
The photolithography accuracy is significantly improved without affecting the performance of process menus of other layers, and the overall performance of OVL has increased by 32.9% to 40.2%.
Smart Images
Figure CN120161688A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for improving overlay accuracy by optimizing the voltage at the wafer edge. Background Art
[0002] In the complex process of chip manufacturing, the lithography process is a key link that determines whether the transistor pattern can be accurately "copied" onto the silicon wafer. The lithography overlay accuracy (Overlay, OVL, or lithography accuracy) is a key indicator for measuring the alignment accuracy of different layer circuit patterns by the lithography machine. In the field of chip manufacturing, the error of the overlay accuracy will directly affect the chip yield (CP) and performance. Therefore, in the chip manufacturing process, stable overlay accuracy results are crucial for device performance and yield.
[0003] Currently, common methods for improving overlay accuracy include: 1. Extreme optimization of lithography machine hardware: For example, dual wafer stage systems, high numerical aperture (NA) objectives, laser interferometers, and deformation compensation; 2. Collaborative innovation of materials and processes: For example, energy lithography resist, planarization process, stress matching materials; 3. Closed-loop control of algorithms and data: For example, real-time feedback systems, machine learning prediction models, virtual metrology; 4. Multiple exposure and process collaboration: For example, self-aligned double patterning (SADP / SAQP), design-process co-optimization (DTCO) 5. Optimizing the wafer edge temperature at specific steps, for example, appropriately reducing the temperature of T7.
[0004] The above methods 1 to 4 can improve the overlay accuracy to a certain extent and enhance the overall performance of the device. However, the above methods are to modify the equipment / materials / algorithms, etc., which are relatively complex to optimize and have high costs, and it is difficult to promote them in stable manufacturing Fabs; the disadvantage of method 5 is that it will sacrifice the film thickness uniformity within the wafer surface. Summary of the Invention
[0005] Based on the technical problems existing in the prior art, the present invention provides a method for improving overlay accuracy by optimizing the voltage at the wafer edge, which solves the problems of poor overlay accuracy, high optimization cost, or affecting the wafer surface uniformity in the existing process, and realizes more sufficient release of the wafer internal stress through simple adjustment of the heat treatment process parameters, thereby improving the overlay accuracy in the lithography process.
[0006] According to the technical solution of the present invention, the present invention provides a method for improving overlay accuracy by optimizing the wafer edge voltage, including performing heat treatment on the wafer using a rapid thermal processing equipment before the lithography process; the rapid thermal processing equipment has a heating device for heating the wafer, the position of the wafer in the rapid thermal processing equipment is directly opposite to the heating device, and the size of the heating device is larger than the size of the wafer; the heating device is formed with a plurality of heating regions, and each heating region has at least one heating lamp.
[0007] Further, the input voltages of the heating lamps in different heating regions can be independently controlled respectively to control the heating power of each heating region; the heating regions include an outermost region, a second outermost region, and an inner region arranged in sequence from the outside to the inside; the orthographic projection of the outermost region on the wafer plane is entirely located outside the wafer edge, at least a part of the orthographic projection of the second outermost region on the wafer plane is located inside the wafer near the wafer edge, and the orthographic projection of the inner region on the wafer plane is entirely located inside the wafer near the wafer edge.
[0008] Furthermore, during the heat treatment, by increasing the input voltage of the heating lamp in the outermost region, the input voltages of the heating lamps from the inner region to the second outermost region show a decreasing distribution.
[0009] In some embodiments, the input voltage of the heating lamp in the outermost region is higher than the input voltages of the heating lamps in the inner region and the second outermost region.
[0010] In some embodiments, the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is any value within a set threshold range.
[0011] In a preferred embodiment, the set threshold range of the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is 60% ± 38%.
[0012] In a more preferred embodiment, the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is 90% ± 5%.
[0013] In an optimal embodiment, the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is 97% ± 1%.
[0014] In some embodiments, the input voltage of the heating lamp in the outermost region does not exceed 55% of the rated voltage of the heating lamp.
[0015] In some embodiments, before increasing the input voltage of the heating lamps in the outermost region, the input voltage of the heating lamps in the outermost region is 38.3% ± 0.5% of the rated voltage of the heating lamps, the input voltage of the heating lamps in the second outermost region is 45.2% ± 0.5% of the rated voltage of the heating lamps, and the input voltage of the heating lamps in the inner region is 45.5% ± 0.5% of the rated voltage of the heating lamps; after only increasing the input voltage of the heating lamps in the outermost region to 48.7% ± 0.5% of the rated voltage of the heating lamps, the input voltage of the heating lamps in the second outermost region decreases to 44.5% ± 0.5% of the rated voltage of the heating lamps, and the input voltage of the heating lamps in the inner region increases to 45.9% ± 0.5% of the rated voltage of the heating lamps.
[0016] In some embodiments, the radius of the wafer is 150 mm, the radius of the inner edge of the second outermost region is 140 mm ± 5 mm, the outer edge of the inner region is adjacent to the inner edge of the second outermost region, and the radius of the inner edge of the inner region is 126 mm ± 5 mm.
[0017] In some embodiments, it is used for the thin gate oxide process, and the thin gate oxide process includes the following steps: Step S1, growing a thick gate oxide layer; Step S2, cleaning the thick gate oxide layer that does not need to be retained; Step S3, growing a thin gate oxide layer; which includes the method of improving the overlay accuracy by optimizing the wafer edge voltage of the present invention; Step S4, applying photoresist by a lithography machine.
[0018] Compared with the prior art, the beneficial technical effects of the present invention are as follows: The method of improving the overlay accuracy by optimizing the wafer edge voltage of the present invention realizes the improvement of the lithography accuracy OVL in the wafer manufacturing process by optimizing the voltage at the wafer edge. Its theory relies on the coupling effect of the voltage between the heating regions of the heating device in the rapid thermal processing (RTP) equipment. By changing the voltage of the outermost circle of the wafer, the relationship between the voltages of the second outermost circle and the inner circle is affected, that is, the effect of a decreasing thermal field distribution is achieved, and then the internal stress suffered by the wafer in the previous layer process is fully released, improving the OVL problem after the lithography process; the present invention does not require hardware modification of the equipment machine platform. Without affecting the process menu of other layers (Layer), only by optimizing the outermost circle voltage (or edge voltage) of the corresponding menu can the OVL be effectively improved; for different product types in the Fab, this method can be adopted, which has universality; it is not only simple and easy to operate, but also does not affect the menu performance (such as film thickness) before optimizing the voltage; compared with the original process, the overall performance of the OVL after optimizing the voltage by the method of the present invention has an X-improvement of nearly 32.9% and a Y-improvement of nearly 40.2%. Description of the Drawings
[0019] Figure 1 It is a schematic structural diagram of the orthographic projection relationship between the wafer and the heating area in the method provided by the present invention.
[0020] Figure 2 It is a schematic structural diagram of the rapid thermal processing equipment adopted in the method provided by the present invention.
[0021] Figure 3 It is a schematic structural diagram of the subdivided heating area in the rapid thermal processing equipment adopted in the method provided by the present invention.
[0022] Figure 4 It is a voltage result diagram of each heating area before and after optimizing the voltage by adopting the method of the present invention.
[0023] Figure 5 It is a measurement result diagram of the overlay accuracy before and after optimizing the voltage by adopting the method of the present invention.
[0024] Explanation of the reference numerals in the drawings: 1. Heating device; 11. Outermost ring area; 12. Second outermost ring area; 13. Inner ring area; 2. Wafer; 21. Wafer outer edge line; 3. Edge ring; 31. Edge ring outer edge line; 41. Equipment cavity edge line. Detailed implementation manners
[0025] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.
[0026] In addition, it should be noted that for the convenience of description, only the parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.
[0027] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence relationship of the functions performed by these devices, modules or units.
[0028] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly specified otherwise in the context, it should be understood as "one or more".
[0029] The present invention provides a method for improving overlay accuracy by optimizing the edge voltage of a wafer, belonging to the field of semiconductor manufacturing technology. During the semiconductor manufacturing process, the wafer needs to undergo multiple processes such as film deposition, cleaning, photoresist coating, etching, and high-temperature annealing, so large internal stresses will be generated inside it; the wafer OVL problem is an embodiment of insufficient release of internal stresses, and the high-risk area where this OVL problem occurs is usually at the edge of the wafer. The main purpose of the present invention is to solve the problems existing in the existing processes, such as poor overlay accuracy, the problem that the lithography accuracy OVL during wafer manufacturing is prone to exceed the specification control, or the optimization cost is relatively high, or it affects the surface uniformity of the wafer. By simply adjusting the process parameters of the heat treatment process, the surface voltage distribution of the wafer is optimized, that is, the surface thermal field distribution of the wafer is optimized, so that the internal stresses of the wafer are released more fully, and thus the overlay accuracy in the lithography process is improved.
[0030] On the other hand, the method for improving overlay accuracy by optimizing the edge voltage of the wafer according to the present invention includes, before performing the lithography process, performing heat treatment on the wafer using a rapid thermal processing equipment; the rapid thermal processing equipment has a heating device for heating the wafer, and the size of the heating device is larger than the size of the wafer; the heating device is formed with a plurality of heating regions, and the heating regions include an outermost ring region, a second outermost ring region, and an inner ring region arranged in sequence from outside to inside; during the heat treatment, by increasing the input voltage of the heating lamps in the outermost ring region, the input voltages of the heating lamps from the inner ring region to the second outermost ring region show a decreasing distribution. The present invention affects the relationship between the voltages of the second outermost ring and the inner ring by changing the voltage of the outermost ring of the wafer, that is, achieves the effect that the thermal field shows a decreasing distribution, and further fully releases the internal stresses suffered by the wafer in the previous process layer, and improves the OVL problem after the lithography process.
[0031] Please refer to Figures 1 to 4 , the method for improving overlay accuracy by optimizing the edge voltage of the wafer according to the present invention includes, before performing the lithography process, performing heat treatment on the wafer using a rapid thermal processing equipment. The heat treatment step, such as the annealing step, already exists in the original process. The present invention can eliminate the internal stresses more thoroughly by optimizing the voltage in this heat treatment step, thereby improving the effect of the subsequent lithography process.
[0032] The main structure of the rapid thermal processing equipment is, for example Figure 2As shown, there is a heating device 1 for heating the wafer, such as a lamp panel, on which a plurality of heating lamps are densely distributed. The position of the wafer 2 in the rapid thermal processing equipment is directly opposite to the heating device 1, for example, the wafer 2 is placed on the edge ring 3 in the equipment cavity, and the wafer is located directly below the heating device 1. The size of the heating device 1 is larger than the size of the wafer. In other words, the range of the heating device 1 completely covers the wafer, so that the edge and the inside of the wafer can receive basically the same heating effect. General semiconductor thermal processing equipment has this type of structure, and the present invention can be applied to various existing or similar specific equipment.
[0033] Furthermore, the heating device 1 is formed with a plurality of heating zones, each of which has at least one heating lamp; the input voltages of the heating lamps in different heating zones can be independently controlled to control the heating power of each heating zone. Figure 3 In the structure shown ( Figure 3 It is only a schematic diagram and does not represent the actual distribution, number and size of the heating lamps. The densely distributed heating lamps are distributed in a concentric circle-like manner to form a total of 15 subdivided heating areas, namely Zone 1 to Zone 15, so as to control the heating power of the lamp panel from the inside to the outside.
[0034] In summary, if Figure 1 As shown, the heating area includes an outermost ring area 11, a sub-outer ring area 12 and an inner ring area 13, which are arranged in sequence from the outside to the inside. The orthographic projection of the outermost ring area 11 on the wafer plane is all located outside the edge of the wafer, that is, outside the outer edge line 21 of the wafer, the edge line 41 of the equipment cavity, etc., so that compared with other areas, the thermal radiation of the outermost ring area 11 does not directly irradiate the wafer. At least a part of the orthographic projection of the sub-outer ring area 12 on the wafer plane is located inside the wafer near the edge of the wafer; wherein, "at least a part" includes "all" and "not all". The orthographic projection of the inner ring area 13 on the wafer plane is completely located inside the wafer near the edge of the wafer. Of course, the heating device 1 has other heating areas in the inner ring area 13.
[0035] Preferably, for a common 300 mm wafer, the wafer radius is 150 mm, the radius of the inner edge of the secondary outer ring region 12 is about 140 mm (e.g., 140 mm ± 5 mm), the outer edge of the inner ring region 13 is adjacent to the inner edge of the secondary outer ring region 12, and the radius of the inner edge of the inner ring region 13 is about 126 mm (e.g., 126 mm ± 5 mm). Figure 3 In the embodiment shown, there are 15 subdivided heating zones in total, and Zone 14 and Zone 15 can be defined as the outermost zone 11, Zone 10 to Zone 13 can be defined as the sub-outer zone 12, and Zone 7 to Zone 9 can be defined as the inner zone 13.
[0036] When performing heat treatment, by increasing the input voltage of the heating lamp in the outermost region 11, the input voltages of the heating lamps in the inner region 13 to the second outermost region 12 are made to show a decreasing distribution. If the temperature at the periphery of the wafer is relatively high, stress is not easily released; as the radius increases and the temperature decreases, it helps with stress release. It should be noted that since the voltage in the outermost region 11 acts on the edge ring 3, it will not affect the film thickness, etc. within the wafer surface.
[0037] As Figure 4 shown, in the original process, the voltage in the outermost region 11 is usually set to be relatively low. In this solution, the voltage in the outermost region 11 is increased. Specifically, for example, the input voltage of the heating lamp in the outermost region 11 is made higher than the input voltages of the heating lamps in the inner region 13 and the second outermost region 12. Due to the coupling interaction between regions (such a coupling effect exists due to the specific structure of the RTP equipment), the voltage in the second outermost region 12 will decrease and the voltage in the inner region 13 will increase, making the voltage in the second outermost region 12 slightly lower than the voltage in the inner region 13, thus forming a thermal field with a decreasing gradient from the inside to the outside at the edge of the wafer.
[0038] In some embodiments, the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is any value within a set threshold range. The set threshold range can be set according to the working site, and can be set as a range value or several point values of the voltage ratio can be selected. In a preferred embodiment, the set threshold range of the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is 60% ± 38%. In a more preferred embodiment, the ratio of the input voltage of the heating lamp in the second outermost region to the input voltage of the heating lamp in the inner region is 90% ± 5%.
[0039] In a relatively preferred embodiment, the ratio of the input voltage of the heating lamp in the second outermost region 12 to the input voltage of the heating lamp in the inner region 13 is 97% ± 1%. At this time, the thermal field with a decreasing gradient from the inside to the outside formed at the edge of the wafer is very stable and the working efficiency is optimal.
[0040] As Figure 4In the specific embodiments shown, before increasing the input voltage of the heating lamps in the outermost region 11, the input voltage of the heating lamps in the outermost region 11 is 38.3% ± 0.5% of the rated voltage of the heating lamps, the input voltage of the heating lamps in the second outermost region 12 is 45.2% ± 0.5% of the rated voltage of the heating lamps, and the input voltage of the heating lamps in the innermost region 13 is 45.5% ± 0.5% of the rated voltage of the heating lamps. After only increasing the input voltage of the heating lamps in the outermost region 11 to 48.7% ± 0.5% of the rated voltage of the heating lamps, the input voltage of the heating lamps in the second outermost region 12 decreases to 44.5% ± 0.5% of the rated voltage of the heating lamps, and the input voltage of the heating lamps in the innermost region 13 increases to 45.9% ± 0.5% of the rated voltage of the heating lamps. Considering the service life of the heating lamps, preferably, after increasing the voltage by using the method of the present invention, the input voltage of the heating lamps in the outermost region 11 does not exceed 55% of the rated voltage of the heating lamps.
[0041] As a more specific embodiment, the present invention can be used in the thin gate oxide process, and the thin gate oxide process includes the following steps (only some of the processes).
[0042] Step S1, growing a thick gate oxide; specifically, it is carried out on a furnace tube machine.
[0043] Step S2, cleaning the unnecessary thick gate oxide to prepare for growing the thin gate oxide; specifically, it is cleaned by using the WET cleaning process.
[0044] Step S3, growing a thin gate oxide on a rapid thermal processing machine; it includes the method of improving the overlay accuracy by optimizing the wafer edge voltage described in the present invention. Specifically, for example, before, during, or after growing the thin gate oxide, the voltage distribution, that is, the thermal field distribution, is optimized by increasing the voltage in the outermost region 11, so as to eliminate the internal stress.
[0045] Step S4, applying photoresist by a lithography machine. Then measure the OVL situation.
[0046] In the embodiment, the OVL measurement results are as Figure 5 shown. Among them, 5 wafers are tested under different process conditions and compared with the results of the original process. It can be seen that after increasing the edge voltage to a certain extent, the performance of the OVL is significantly improved; compared with the original process without optimizing the voltage, the overall performance of the OVL after optimizing the voltage by using the method of the present invention has an X - improvement of nearly 32.9% and a Y - improvement of nearly 40.2% (the smaller the OVL measurement value X - / Y - OVL data, the better; the same wafers are compared).
[0047] It should be noted that please refer to Figure 1, In a rapid thermal processing equipment, there are usually multiple thermometers on the back side of the wafer 3, typically 7 for example, which are T1 to T7 in sequence from the inside to the outside. The wafer will be driven to rotate by the edge ring 3 during the heat treatment process, and the thermometers are used to measure the temperature at various radial positions of the wafer. The correspondence between these 7 thermometers and the 15 subdivided heating regions of the heating device 1 is as follows: for example, T1 corresponds to zone1, T2 corresponds to zone2, T3 corresponds to zone3, T4 corresponds to zone4, T5 corresponds to zone5-6, T6 corresponds to zone7-9, and T7 corresponds to zone10-15. In the prior art, the monitoring of the wafer temperature situation is usually directly based on the measurement by the thermometers. In the equipment system, the temperature outside compensation can control to reduce the temperature of the outer ring of the wafer (such as the temperature corresponding to T7 in the outermost ring), in order to form the required thermal field gradient, but this is not the case in reality. These 7 thermometers are equivalent to only being able to measure the temperature at 7 points on the wafer and cannot directly and completely reflect the actual thermal field formed by the 15 subdivided heating regions. Through actual operation tests, with the conventional temperature outside compensation temperature control method, the voltage situation of the heating region hardly changes and cannot form Figure 4 the shown effect, and it sacrifices the thickness uniformity of the film within the wafer surface. After increasing the voltage by using the method of the present invention, the actually formed spatial temperature field will change accordingly, but the temperature measurement results of the thermometers may not change or do not change significantly (which can be further adjusted in a conventional manner to make the temperatures of the 7 thermometers meet the process requirements).
[0048] In summary, the key point of the present invention lies in the optimization of the voltage field, i.e., the thermal field distribution on the wafer surface. The main technical means is to optimize the input voltage of the heating device of the rapid thermal processing equipment, including optimizing the outermost ring voltage (or called edge voltage, such as Zone14~zone15), but not limited to simultaneously optimizing the voltage of specific regions (such as Zone7~zone9, etc.), to form the required thermal field gradient to improve the overlay accuracy. Its theory relies on the coupling effect of the voltages between the heating regions of the heating device in the rapid thermal processing equipment. By changing the voltage of the outermost ring of the wafer, the relationship between the voltages of the second outermost ring and the inner ring is affected, that is, to achieve the effect that the thermal field shows a decreasing distribution, and then the internal stress suffered by the wafer in the previous layer process is fully released, and the OVL problem after the lithography process is improved; the present invention does not require hardware modification of the equipment machine. Without affecting the process menu of other layers (Layer), only by optimizing the outermost ring voltage (or called edge voltage) of the corresponding menu can the OVL be effectively improved; for different product types within the Fab, this method can be adopted, which has universality; it is not only simple and easy to operate, but also does not affect the menu performance (such as film thickness) before optimizing the voltage.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for improving overlay accuracy by optimizing wafer edge voltage, characterized in that: This includes using rapid thermal processing equipment to heat treat the wafer before the photolithography process; A rapid thermal processing device is provided with a heating device (1) for heating a wafer. The wafer is located in the rapid thermal processing device opposite to the heating device (1), and the size of the heating device (1) is larger than the size of the wafer. The heating device (1) is formed with a plurality of heating areas, and each heating area has at least one heating lamp.
2. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 1, characterized in that: The input voltages of the heating lamps in different heating areas can be independently controlled to control the heating power of each heating area; the heating areas include an outermost ring area (11), a sub-outer ring area (12) and an inner ring area (13) arranged in sequence from the outside to the inside; the orthographic projection of the outermost ring area (11) on the wafer plane is completely located outside the edge of the wafer, the orthographic projection of the sub-outer ring area (12) on the wafer plane is at least partially located inside the wafer near the edge of the wafer, and the orthographic projection of the inner ring area (13) on the wafer plane is completely located inside the wafer near the edge of the wafer.
3. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 2, characterized in that: During heat treatment, the input voltage of the heating lamp in the outermost region (11) is increased, so that the input voltage of the heating lamp from the inner region (13) to the second outer region (12) presents a decreasing distribution.
4. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 2 or 3, characterized in that: The input voltage of the heating lamp in the outermost circle area (11) is higher than the input voltage of the heating lamp in the inner circle area (13) and the second outer circle area (12).
5. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 2, characterized in that: The ratio of the input voltage of the heating lamp in the sub-outer circle area (12) to the input voltage of the heating lamp in the inner circle area (13) is any value within a set threshold range.
6. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 5, characterized in that: The set threshold range of the ratio of the input voltage of the heating lamp in the sub-outer circle area (12) to the input voltage of the heating lamp in the inner circle area (13) is 60%±38%.
7. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 6, characterized in that: The ratio of the input voltage of the heating lamps in the sub-outer circle area to the input voltage of the heating lamps in the inner circle area is 90%±5%.
8. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 6, characterized in that: The ratio of the input voltage of the heating lamps in the sub-outer circle area to the input voltage of the heating lamps in the inner circle area is 97%±1%.
9. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 2, characterized in that: The radius of the wafer is 150 mm, the radius of the inner edge of the sub-outer ring area (12) is 140 mm ± 5 mm, the outer edge of the inner ring area (13) is adjacent to the inner edge of the sub-outer ring area (12), and the radius of the inner edge of the inner ring area (13) is 126 mm ± 5 mm.
10. The method for improving overlay accuracy by optimizing wafer edge voltage according to claim 3, characterized in that: It is used for thin gate oxide process, which includes the following steps: Step S1, growing a thick gate oxide layer; Step S2, cleaning away the thick gate oxide layer that does not need to be retained; Step S3, growing a thin gate oxide layer; including the method for improving overlay accuracy by optimizing wafer edge voltage according to claim 1; Step S4, photolithography machine spreads glue.